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adrv9002 Reference Design Integration

This page outlines the HDL reference design integration for the adrv9002 reference design for the Analog Devices ADRV9002 component. The IP-Core Generation follow is available on the based on the following base HDL reference design for the following board and design variants:

Reference Design

HDL Reference Design with Custom IP from HDL-Coder. Click on sub-blocks for more documentation.

The IP-Core generation flow will integrate IP generated from Simulink subsystem into an ADI authored reference design. Depending on the FPGA carrier and FMC card or SoM, this will support different IP locations based on the diagram above.

HDL Worflow Advisor Port Mappings

When using the HDL Worflow Advisor, the following port mappings are used to connect the reference design to the HDL-Coder generated IP-Core:

Type Target Platform Interface (MATLAB) Reference Design Connection (Vivado) Width Reference Design Variant
VALID-OUT IP Data Valid OUT util_adc_1_pack/fifo_wr_en 1 RX
VALID-IN IP Valid Rx Data IN axi_adrv9001/adc_1_valid_i0 1 RX
DATA-OUT IP Data 0 OUT util_adc_1_pack/fifo_wr_data_0 16 RX
DATA-OUT IP Data 1 OUT util_adc_1_pack/fifo_wr_data_1 16 RX
DATA-OUT IP Data 2 OUT util_adc_1_pack/fifo_wr_data_2 16 RX
DATA-OUT IP Data 3 OUT util_adc_1_pack/fifo_wr_data_3 16 RX
DATA-IN ADRV9002 ADC Data Q0 axi_adrv9001/adc_1_data_i0 16 RX
DATA-IN ADRV9002 ADC Data I0 axi_adrv9001/adc_1_data_i1 16 RX
DATA-IN ADRV9002 ADC Data Q0 axi_adrv9001/adc_1_data_q0 16 RX
DATA-IN ADRV9002 ADC Data I0 axi_adrv9001/adc_1_data_q1 16 RX
VALID-IN IP Valid Tx Data IN util_dac_1_upack/fifo_rd_valid 1 TX
VALID-OUT IP Load Tx Data OUT util_dac_1_upack/fifo_rd_en 1 TX
DATA-OUT ADRV9002 DAC Data Q0 axi_adrv9001/dac_1_data_i0 16 TX
DATA-OUT ADRV9002 DAC Data I0 axi_adrv9001/dac_1_data_i1 16 TX
DATA-OUT ADRV9002 DAC Data Q0 axi_adrv9001/dac_1_data_q0 16 TX
DATA-OUT ADRV9002 DAC Data I0 axi_adrv9001/dac_1_data_q1 16 TX
DATA-IN IP Data 0 IN util_dac_1_upack/fifo_rd_data_0 16 TX
DATA-IN IP Data 1 IN util_dac_1_upack/fifo_rd_data_1 16 TX
DATA-IN IP Data 2 IN util_dac_1_upack/fifo_rd_data_2 16 TX
DATA-IN IP Data 3 IN util_dac_1_upack/fifo_rd_data_3 16 TX