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adrv9371 Reference Design Integration

This page outlines the HDL reference design integration for the adrv9371 reference design for the Analog Devices AD9371 component. The IP-Core Generation follow is available on the based on the following base HDL reference design for the following board and design variants:

Reference Design

HDL Reference Design with Custom IP from HDL-Coder. Click on sub-blocks for more documentation.

The IP-Core generation flow will integrate IP generated from Simulink subsystem into an ADI authored reference design. Depending on the FPGA carrier and FMC card or SoM, this will support different IP locations based on the diagram above.

HDL Worflow Advisor Port Mappings

When using the HDL Worflow Advisor, the following port mappings are used to connect the reference design to the HDL-Coder generated IP-Core:

Type Target Platform Interface (MATLAB) Reference Design Connection (Vivado) Width Reference Design Variant
VALID-OUT IP Data Valid OUT util_ad9371_rx_cpack/fifo_wr_en 1 RX
VALID-IN IP Valid Rx Data IN rx_ad9371_tpl_core/adc_valid_0 1 RX
DATA-OUT IP Data 0 OUT util_ad9361_adc_pack/fifo_wr_data_0 16 RX
DATA-OUT IP Data 1 OUT util_ad9361_adc_pack/fifo_wr_data_1 16 RX
DATA-OUT IP Data 2 OUT util_ad9361_adc_pack/fifo_wr_data_2 16 RX
DATA-OUT IP Data 3 OUT util_ad9361_adc_pack/fifo_wr_data_3 16 RX
DATA-IN AD9371 ADC Data Q0 rx_ad9371_tpl_core/adc_data_0 16 RX
DATA-IN AD9371 ADC Data I0 rx_ad9371_tpl_core/adc_data_1 16 RX
DATA-IN AD9371 ADC Data Q1 rx_ad9371_tpl_core/adc_data_2 16 RX
DATA-IN AD9371 ADC Data I1 rx_ad9371_tpl_core/adc_data_3 16 RX
VALID-IN IP Valid Tx Data IN util_ad9371_tx_upack/fifo_rd_valid 1 TX
VALID-OUT IP Load Tx Data OUT util_ad9371_tx_upack/fifo_rd_en 1 TX
DATA-OUT AD9371 DAC Data Q0 tx_ad9371_tpl_core/dac_data_0 32 TX
DATA-OUT AD9371 DAC Data I0 tx_ad9371_tpl_core/dac_data_1 32 TX
DATA-OUT AD9371 DAC Data Q1 tx_ad9371_tpl_core/dac_data_2 32 TX
DATA-OUT AD9371 DAC Data I1 tx_ad9371_tpl_core/dac_data_3 32 TX
DATA-IN IP Data 0 IN util_ad9371_tx_upack/fifo_rd_data_0 32 TX
DATA-IN IP Data 1 IN util_ad9371_tx_upack/fifo_rd_data_1 32 TX
DATA-IN IP Data 2 IN util_ad9371_tx_upack/fifo_rd_data_2 32 TX
DATA-IN IP Data 3 IN util_ad9371_tx_upack/fifo_rd_data_3 32 TX