AXI HSCI

The AXI HSCI (High-Speed Communication Interface) is an FPGA IP core driver that provides a high-speed serial communication interface for AD9084/AD9088 MxFE data converters. It enables efficient register access and data transfer between the FPGA and the MxFE devices at speeds up to 800 MHz.

The driver implements:

High-speed serial read/write operations to MxFE registers
Automatic and manual link-up modes
Built-in self-test (BIST) with LFSR pattern generation
Debug and diagnostic interfaces via debugfs
Silent mode for reduced verbosity

Supported IP Cores

AXI HSCI IP v1.0.a

Status

Source	Mainlined?
drivers/misc/adi-axi-hsci.c	No

Files

Function	File
driver	drivers/misc/adi-axi-hsci.c
header	drivers/misc/adi-axi-hsci.h

Overview

The AXI HSCI interface provides a high-speed alternative to traditional SPI for communicating with AD9084/AD9088 MxFE data converters. Operating at up to 800 MHz, it significantly reduces the time required for device configuration and calibration operations.

The interface supports:

Streaming read/write operations with configurable address and data lengths
Automatic link-up with clock phase adjustment
Manual link-up with explicit control over link parameters
MISO/MOSI test modes for link verification

Adding Linux driver support

Enabling the driver

Configure kernel with make menuconfig:

Linux Kernel Configuration
    Device Drivers  --->
        Misc devices  --->
            <*>   Analog Devices AXI HSCI driver

Adding a device tree entry

Required properties

compatible: Must be "adi,axi-hsci-1.0.a"
reg: Physical base address and size of the IP core registers
clocks: Reference to the peripheral clock
clock-names: Must be "pclk"

Optional properties

adi,hsci-interface-speed-mhz: Interface speed in MHz (default: 800)

Device tree example

Clock generator for HSCI:

hsci_clkgen: axi-clkgen@44ad0000  {
    compatible = "adi,axi-clkgen-2.00.a";
    reg = <0x44ad0000 0x10000>;
    #clock-cells = <0>;
    clocks = <&clk_bus_0>, <&clk_bus_0>;
    clock-names = "s_axi_aclk", "clkin1";
    clock-output-names = "hsci_clkgen";
};

HSCI interface:

axi_hsci_0: axi_hsci_0@7c500000 {
    compatible = "adi,axi-hsci-1.0.a";
    reg = <0x7c500000 0x40000>;
    clocks = <&hsci_clkgen>;
    clock-names = "pclk";
    adi,hsci-interface-speed-mhz = <800>;
};

Connecting to AD9084/AD9088

The MxFE device references the HSCI interface using the adi,axi-hsci-connected property:

ad9084: ad9084@0 {
    compatible = "adi,ad9084";
    reg = <0>;
    spi-max-frequency = <1000000>;

    /* HSCI connection */
    adi,axi-hsci-connected = <&axi_hsci>;
    adi,hsci-auto-linkup-mode-en;

    /* Optional: disable HSCI after boot for power savings */
    // adi,hsci-disable-after-boot-en;

};

Driver testing

The HSCI driver exposes a debugfs interface for testing and diagnostics.

Debugfs interface

The driver creates a debugfs directory under /sys/kernel/debug/adi-axi-hsci/ with the following entries:

status (read-only): Shows current link status, PHY status, and error counters.
linkup_ctrl (read/write): Manual link-up control register.
linkup_status (read-only): Link-up state machine status.
scratch (read/write): Scratch register for testing register access.
silent (read/write): Enable/disable silent mode.
statistics (read-only): Read/write transfer statistics.

Example debugfs usage:

~$

cd /sys/kernel/debug/adi-axi-hsci/axi_hsci@bc500000

/sys/kernel/debug/adi-axi-hsci/axi_hsci@bc500000$

cat status

/sys/kernel/debug/adi-axi-hsci/axi_hsci@bc500000$

cat linkup_status

/sys/kernel/debug/adi-axi-hsci/axi_hsci@bc500000$

cat statistics

Theory of operation

Link establishment

The HSCI link can be established in two modes:

Automatic Link-up Mode:

The master sends training patterns
The slave detects patterns and adjusts clock phase
Both sides exchange alignment tables
Link becomes active when alignment is achieved

Manual Link-up Mode:

User configures specific link-up word via linkup_ctrl
Clock inversion settings are applied manually
Link is established with fixed parameters

Data transfer

The HSCI interface supports streaming transfers:

Configure transfer parameters (address size, data length, target)
Write data to BRAM buffer (for write operations)
Trigger transfer via RUN register
Wait for completion (DONE status)
Read data from BRAM buffer (for read operations)

The driver provides kernel APIs for other drivers to use:

int axi_hsci_readm(struct axi_hsci_state *st, const u8 tx_data[],
                   u8 rx_data[], u32 num_tx_rx_bytes, u8 addr_len,
                   u8 data_len, u32 stream_len);

int axi_hsci_writem(struct axi_hsci_state *st, const u8 tx_data[],
                    u32 num_tx_rx_bytes, u8 addr_len, u8 data_len,
                    u32 stream_len);

Register map

Address	Name	Description
0x0000	REVISION_ID	IP core revision
0x8001	HSCI_MASTER_MODE	Transfer mode configuration
0x8002	HSCI_MASTER_XFER_NUM	Number of transfers
0x8003	HSCI_MASTER_ADDR_SIZE	Address size (bytes)
0x8004	HSCI_MASTER_BYTE_NUM	Number of bytes per transfer
0x8005	HSCI_MASTER_TARGET	SPI target selection
0x8006	HSCI_MASTER_CTRL	Master control register
0x8007	HSCI_MASTER_BRAM_ADDRESS	BRAM start address
0x8008	HSCI_MASTER_RUN	Start transfer
0x8009	HSCI_MASTER_STATUS	Transfer status (done, running, etc.)
0x800A	HSCI_MASTER_LINKUP_CTRL	Link-up control (manual/auto mode)
0x800B	HSCI_MASTER_TEST_CTRL	Test mode control (MOSI/MISO test)
0x800C	HSCI_MASTER_LINKUP_STATUS	Link-up status (active, clock adj)
0x800D	HSCI_MASTER_LINKUP_STATUS2	Extended link-up status
0x800E	HSCI_DEBUG_STATUS	Debug/error status
0x800F	MISO_TEST_BER	MISO test bit error rate
0x8010	HSCI_MASTER_LINK_ERR_INFO	Link error information
0x8011	HSCI_RATE_CTRL	Rate control and PLL settings
0x8012	HSCI_MASTER_RST	Master reset and error clear
0x8013	HSCI_PHY_STATUS	PHY status (PLL lock, VTC ready)
0x801F	HSCI_MASTER_SCRATCH	Scratch register