MAX32520 Peripheral Driver API
Peripheral Driver API for the MAX32520
ctb_regs.h
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1
8/******************************************************************************
9 *
10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
11 * Analog Devices, Inc.),
12 * Copyright (C) 2023-2024 Analog Devices, Inc.
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 * http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *
26 ******************************************************************************/
27
28#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_CTB_REGS_H_
29#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_CTB_REGS_H_
30
31/* **** Includes **** */
32#include <stdint.h>
33
34#ifdef __cplusplus
35extern "C" {
36#endif
37
38#if defined (__ICCARM__)
39 #pragma system_include
40#endif
41
42#if defined (__CC_ARM)
43 #pragma anon_unions
44#endif
46/*
47 If types are not defined elsewhere (CMSIS) define them here
48*/
49#ifndef __IO
50#define __IO volatile
51#endif
52#ifndef __I
53#define __I volatile const
54#endif
55#ifndef __O
56#define __O volatile
57#endif
58#ifndef __R
59#define __R volatile const
60#endif
62
63/* **** Definitions **** */
64
76typedef struct {
77 __IO uint32_t crypto_ctrl;
78 __IO uint32_t cipher_ctrl;
79 __IO uint32_t hash_ctrl;
80 __IO uint32_t crc_ctrl;
81 __IO uint32_t dma_src;
82 __IO uint32_t dma_dest;
83 __IO uint32_t dma_cnt;
84 __R uint32_t rsv_0x1c;
85 __O uint32_t crypto_din[4];
86 __I uint32_t crypto_dout[4];
87 __IO uint32_t crc_poly;
88 __IO uint32_t crc_val;
89 __IO uint32_t crc_prng;
90 __IO uint32_t ham_ecc;
91 __IO uint32_t cipher_init[4];
92 __O uint32_t cipher_key[8];
93 __IO uint32_t hash_digest[16];
94 __IO uint32_t hash_msg_sz[4];
95 __IO uint32_t a_length_0;
96 __IO uint32_t a_length_1;
97 __IO uint32_t pld_length_0;
98 __IO uint32_t pld_length_1;
99 __IO uint32_t tagmic[4];
100 __R uint32_t rsv_0xf0_0xff[4];
101 __IO uint32_t sca_cn;
102 __IO uint32_t sca_acn;
103 __IO uint32_t sca_st;
104 __IO uint32_t sca_ppx_addr;
105 __IO uint32_t sca_ppy_addr;
106 __IO uint32_t sca_ppz_addr;
107 __IO uint32_t sca_pqx_addr;
108 __IO uint32_t sca_pqy_addr;
109 __IO uint32_t sca_pqz_addr;
110 __IO uint32_t sca_rdsa_addr;
111 __IO uint32_t sca_res_addr;
112 __IO uint32_t sca_op_buff_addr;
113 __IO uint32_t sca_moddata;
115
116/* Register offsets for module CTB */
123#define MXC_R_CTB_CRYPTO_CTRL ((uint32_t)0x00000000UL)
124#define MXC_R_CTB_CIPHER_CTRL ((uint32_t)0x00000004UL)
125#define MXC_R_CTB_HASH_CTRL ((uint32_t)0x00000008UL)
126#define MXC_R_CTB_CRC_CTRL ((uint32_t)0x0000000CUL)
127#define MXC_R_CTB_DMA_SRC ((uint32_t)0x00000010UL)
128#define MXC_R_CTB_DMA_DEST ((uint32_t)0x00000014UL)
129#define MXC_R_CTB_DMA_CNT ((uint32_t)0x00000018UL)
130#define MXC_R_CTB_CRYPTO_DIN ((uint32_t)0x00000020UL)
131#define MXC_R_CTB_CRYPTO_DOUT ((uint32_t)0x00000030UL)
132#define MXC_R_CTB_CRC_POLY ((uint32_t)0x00000040UL)
133#define MXC_R_CTB_CRC_VAL ((uint32_t)0x00000044UL)
134#define MXC_R_CTB_CRC_PRNG ((uint32_t)0x00000048UL)
135#define MXC_R_CTB_HAM_ECC ((uint32_t)0x0000004CUL)
136#define MXC_R_CTB_CIPHER_INIT ((uint32_t)0x00000050UL)
137#define MXC_R_CTB_CIPHER_KEY ((uint32_t)0x00000060UL)
138#define MXC_R_CTB_HASH_DIGEST ((uint32_t)0x00000080UL)
139#define MXC_R_CTB_HASH_MSG_SZ ((uint32_t)0x000000C0UL)
140#define MXC_R_CTB_A_LENGTH_0 ((uint32_t)0x000000D0UL)
141#define MXC_R_CTB_A_LENGTH_1 ((uint32_t)0x000000D4UL)
142#define MXC_R_CTB_PLD_LENGTH_0 ((uint32_t)0x000000D8UL)
143#define MXC_R_CTB_PLD_LENGTH_1 ((uint32_t)0x000000DCUL)
144#define MXC_R_CTB_TAGMIC ((uint32_t)0x000000E0UL)
145#define MXC_R_CTB_SCA_CN ((uint32_t)0x00000100UL)
146#define MXC_R_CTB_SCA_ACN ((uint32_t)0x00000104UL)
147#define MXC_R_CTB_SCA_ST ((uint32_t)0x00000108UL)
148#define MXC_R_CTB_SCA_PPX_ADDR ((uint32_t)0x0000010CUL)
149#define MXC_R_CTB_SCA_PPY_ADDR ((uint32_t)0x00000110UL)
150#define MXC_R_CTB_SCA_PPZ_ADDR ((uint32_t)0x00000114UL)
151#define MXC_R_CTB_SCA_PQX_ADDR ((uint32_t)0x00000118UL)
152#define MXC_R_CTB_SCA_PQY_ADDR ((uint32_t)0x0000011CUL)
153#define MXC_R_CTB_SCA_PQZ_ADDR ((uint32_t)0x00000120UL)
154#define MXC_R_CTB_SCA_RDSA_ADDR ((uint32_t)0x00000124UL)
155#define MXC_R_CTB_SCA_RES_ADDR ((uint32_t)0x00000128UL)
156#define MXC_R_CTB_SCA_OP_BUFF_ADDR ((uint32_t)0x0000012CUL)
157#define MXC_R_CTB_SCA_MODDATA ((uint32_t)0x00000130UL)
166#define MXC_F_CTB_CRYPTO_CTRL_RST_POS 0
167#define MXC_F_CTB_CRYPTO_CTRL_RST ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_RST_POS))
169#define MXC_F_CTB_CRYPTO_CTRL_INT_POS 1
170#define MXC_F_CTB_CRYPTO_CTRL_INT ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_INT_POS))
172#define MXC_F_CTB_CRYPTO_CTRL_SRC_POS 2
173#define MXC_F_CTB_CRYPTO_CTRL_SRC ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_SRC_POS))
175#define MXC_F_CTB_CRYPTO_CTRL_BSO_POS 4
176#define MXC_F_CTB_CRYPTO_CTRL_BSO ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_BSO_POS))
178#define MXC_F_CTB_CRYPTO_CTRL_BSI_POS 5
179#define MXC_F_CTB_CRYPTO_CTRL_BSI ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_BSI_POS))
181#define MXC_F_CTB_CRYPTO_CTRL_WAIT_EN_POS 6
182#define MXC_F_CTB_CRYPTO_CTRL_WAIT_EN ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_WAIT_EN_POS))
184#define MXC_F_CTB_CRYPTO_CTRL_WAIT_POL_POS 7
185#define MXC_F_CTB_CRYPTO_CTRL_WAIT_POL ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_WAIT_POL_POS))
187#define MXC_F_CTB_CRYPTO_CTRL_WRSRC_POS 8
188#define MXC_F_CTB_CRYPTO_CTRL_WRSRC ((uint32_t)(0x3UL << MXC_F_CTB_CRYPTO_CTRL_WRSRC_POS))
189#define MXC_V_CTB_CRYPTO_CTRL_WRSRC_NONE ((uint32_t)0x0UL)
190#define MXC_S_CTB_CRYPTO_CTRL_WRSRC_NONE (MXC_V_CTB_CRYPTO_CTRL_WRSRC_NONE << MXC_F_CTB_CRYPTO_CTRL_WRSRC_POS)
191#define MXC_V_CTB_CRYPTO_CTRL_WRSRC_CIPHEROUTPUT ((uint32_t)0x1UL)
192#define MXC_S_CTB_CRYPTO_CTRL_WRSRC_CIPHEROUTPUT (MXC_V_CTB_CRYPTO_CTRL_WRSRC_CIPHEROUTPUT << MXC_F_CTB_CRYPTO_CTRL_WRSRC_POS)
193#define MXC_V_CTB_CRYPTO_CTRL_WRSRC_READFIFO ((uint32_t)0x2UL)
194#define MXC_S_CTB_CRYPTO_CTRL_WRSRC_READFIFO (MXC_V_CTB_CRYPTO_CTRL_WRSRC_READFIFO << MXC_F_CTB_CRYPTO_CTRL_WRSRC_POS)
196#define MXC_F_CTB_CRYPTO_CTRL_RDSRC_POS 10
197#define MXC_F_CTB_CRYPTO_CTRL_RDSRC ((uint32_t)(0x3UL << MXC_F_CTB_CRYPTO_CTRL_RDSRC_POS))
198#define MXC_V_CTB_CRYPTO_CTRL_RDSRC_DMADISABLED ((uint32_t)0x0UL)
199#define MXC_S_CTB_CRYPTO_CTRL_RDSRC_DMADISABLED (MXC_V_CTB_CRYPTO_CTRL_RDSRC_DMADISABLED << MXC_F_CTB_CRYPTO_CTRL_RDSRC_POS)
200#define MXC_V_CTB_CRYPTO_CTRL_RDSRC_DMAORAPB ((uint32_t)0x1UL)
201#define MXC_S_CTB_CRYPTO_CTRL_RDSRC_DMAORAPB (MXC_V_CTB_CRYPTO_CTRL_RDSRC_DMAORAPB << MXC_F_CTB_CRYPTO_CTRL_RDSRC_POS)
202#define MXC_V_CTB_CRYPTO_CTRL_RDSRC_RNG ((uint32_t)0x2UL)
203#define MXC_S_CTB_CRYPTO_CTRL_RDSRC_RNG (MXC_V_CTB_CRYPTO_CTRL_RDSRC_RNG << MXC_F_CTB_CRYPTO_CTRL_RDSRC_POS)
205#define MXC_F_CTB_CRYPTO_CTRL_FLAG_MODE_POS 14
206#define MXC_F_CTB_CRYPTO_CTRL_FLAG_MODE ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_FLAG_MODE_POS))
208#define MXC_F_CTB_CRYPTO_CTRL_DMADNEMSK_POS 15
209#define MXC_F_CTB_CRYPTO_CTRL_DMADNEMSK ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_DMADNEMSK_POS))
211#define MXC_F_CTB_CRYPTO_CTRL_DMA_DONE_POS 24
212#define MXC_F_CTB_CRYPTO_CTRL_DMA_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_DMA_DONE_POS))
214#define MXC_F_CTB_CRYPTO_CTRL_GLS_DONE_POS 25
215#define MXC_F_CTB_CRYPTO_CTRL_GLS_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_GLS_DONE_POS))
217#define MXC_F_CTB_CRYPTO_CTRL_HSH_DONE_POS 26
218#define MXC_F_CTB_CRYPTO_CTRL_HSH_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_HSH_DONE_POS))
220#define MXC_F_CTB_CRYPTO_CTRL_CPH_DONE_POS 27
221#define MXC_F_CTB_CRYPTO_CTRL_CPH_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_CPH_DONE_POS))
223#define MXC_F_CTB_CRYPTO_CTRL_ERR_POS 29
224#define MXC_F_CTB_CRYPTO_CTRL_ERR ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_ERR_POS))
226#define MXC_F_CTB_CRYPTO_CTRL_RDY_POS 30
227#define MXC_F_CTB_CRYPTO_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_RDY_POS))
229#define MXC_F_CTB_CRYPTO_CTRL_DONE_POS 31
230#define MXC_F_CTB_CRYPTO_CTRL_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_DONE_POS))
240#define MXC_F_CTB_CIPHER_CTRL_ENC_POS 0
241#define MXC_F_CTB_CIPHER_CTRL_ENC ((uint32_t)(0x1UL << MXC_F_CTB_CIPHER_CTRL_ENC_POS))
243#define MXC_F_CTB_CIPHER_CTRL_KEY_POS 1
244#define MXC_F_CTB_CIPHER_CTRL_KEY ((uint32_t)(0x1UL << MXC_F_CTB_CIPHER_CTRL_KEY_POS))
246#define MXC_F_CTB_CIPHER_CTRL_SRC_POS 2
247#define MXC_F_CTB_CIPHER_CTRL_SRC ((uint32_t)(0x3UL << MXC_F_CTB_CIPHER_CTRL_SRC_POS))
248#define MXC_V_CTB_CIPHER_CTRL_SRC_CIPHERKEY ((uint32_t)0x0UL)
249#define MXC_S_CTB_CIPHER_CTRL_SRC_CIPHERKEY (MXC_V_CTB_CIPHER_CTRL_SRC_CIPHERKEY << MXC_F_CTB_CIPHER_CTRL_SRC_POS)
250#define MXC_V_CTB_CIPHER_CTRL_SRC_REGFILE ((uint32_t)0x2UL)
251#define MXC_S_CTB_CIPHER_CTRL_SRC_REGFILE (MXC_V_CTB_CIPHER_CTRL_SRC_REGFILE << MXC_F_CTB_CIPHER_CTRL_SRC_POS)
252#define MXC_V_CTB_CIPHER_CTRL_SRC_QSPIKEY_REGFILE ((uint32_t)0x3UL)
253#define MXC_S_CTB_CIPHER_CTRL_SRC_QSPIKEY_REGFILE (MXC_V_CTB_CIPHER_CTRL_SRC_QSPIKEY_REGFILE << MXC_F_CTB_CIPHER_CTRL_SRC_POS)
255#define MXC_F_CTB_CIPHER_CTRL_CIPHER_POS 4
256#define MXC_F_CTB_CIPHER_CTRL_CIPHER ((uint32_t)(0x7UL << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS))
257#define MXC_V_CTB_CIPHER_CTRL_CIPHER_DIS ((uint32_t)0x0UL)
258#define MXC_S_CTB_CIPHER_CTRL_CIPHER_DIS (MXC_V_CTB_CIPHER_CTRL_CIPHER_DIS << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS)
259#define MXC_V_CTB_CIPHER_CTRL_CIPHER_AES128 ((uint32_t)0x1UL)
260#define MXC_S_CTB_CIPHER_CTRL_CIPHER_AES128 (MXC_V_CTB_CIPHER_CTRL_CIPHER_AES128 << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS)
261#define MXC_V_CTB_CIPHER_CTRL_CIPHER_AES192 ((uint32_t)0x2UL)
262#define MXC_S_CTB_CIPHER_CTRL_CIPHER_AES192 (MXC_V_CTB_CIPHER_CTRL_CIPHER_AES192 << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS)
263#define MXC_V_CTB_CIPHER_CTRL_CIPHER_AES256 ((uint32_t)0x3UL)
264#define MXC_S_CTB_CIPHER_CTRL_CIPHER_AES256 (MXC_V_CTB_CIPHER_CTRL_CIPHER_AES256 << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS)
265#define MXC_V_CTB_CIPHER_CTRL_CIPHER_DES ((uint32_t)0x4UL)
266#define MXC_S_CTB_CIPHER_CTRL_CIPHER_DES (MXC_V_CTB_CIPHER_CTRL_CIPHER_DES << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS)
267#define MXC_V_CTB_CIPHER_CTRL_CIPHER_TDES ((uint32_t)0x5UL)
268#define MXC_S_CTB_CIPHER_CTRL_CIPHER_TDES (MXC_V_CTB_CIPHER_CTRL_CIPHER_TDES << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS)
270#define MXC_F_CTB_CIPHER_CTRL_MODE_POS 8
271#define MXC_F_CTB_CIPHER_CTRL_MODE ((uint32_t)(0x7UL << MXC_F_CTB_CIPHER_CTRL_MODE_POS))
272#define MXC_V_CTB_CIPHER_CTRL_MODE_ECB ((uint32_t)0x0UL)
273#define MXC_S_CTB_CIPHER_CTRL_MODE_ECB (MXC_V_CTB_CIPHER_CTRL_MODE_ECB << MXC_F_CTB_CIPHER_CTRL_MODE_POS)
274#define MXC_V_CTB_CIPHER_CTRL_MODE_CBC ((uint32_t)0x1UL)
275#define MXC_S_CTB_CIPHER_CTRL_MODE_CBC (MXC_V_CTB_CIPHER_CTRL_MODE_CBC << MXC_F_CTB_CIPHER_CTRL_MODE_POS)
276#define MXC_V_CTB_CIPHER_CTRL_MODE_CFB ((uint32_t)0x2UL)
277#define MXC_S_CTB_CIPHER_CTRL_MODE_CFB (MXC_V_CTB_CIPHER_CTRL_MODE_CFB << MXC_F_CTB_CIPHER_CTRL_MODE_POS)
278#define MXC_V_CTB_CIPHER_CTRL_MODE_OFB ((uint32_t)0x3UL)
279#define MXC_S_CTB_CIPHER_CTRL_MODE_OFB (MXC_V_CTB_CIPHER_CTRL_MODE_OFB << MXC_F_CTB_CIPHER_CTRL_MODE_POS)
280#define MXC_V_CTB_CIPHER_CTRL_MODE_CTR ((uint32_t)0x4UL)
281#define MXC_S_CTB_CIPHER_CTRL_MODE_CTR (MXC_V_CTB_CIPHER_CTRL_MODE_CTR << MXC_F_CTB_CIPHER_CTRL_MODE_POS)
283#define MXC_F_CTB_CIPHER_CTRL_COMPH_POS 11
284#define MXC_F_CTB_CIPHER_CTRL_COMPH ((uint32_t)(0x1UL << MXC_F_CTB_CIPHER_CTRL_COMPH_POS))
286#define MXC_F_CTB_CIPHER_CTRL_DTYPE_POS 12
287#define MXC_F_CTB_CIPHER_CTRL_DTYPE ((uint32_t)(0x1UL << MXC_F_CTB_CIPHER_CTRL_DTYPE_POS))
289#define MXC_F_CTB_CIPHER_CTRL_CCMM_POS 13
290#define MXC_F_CTB_CIPHER_CTRL_CCMM ((uint32_t)(0x7UL << MXC_F_CTB_CIPHER_CTRL_CCMM_POS))
292#define MXC_F_CTB_CIPHER_CTRL_CCML_POS 16
293#define MXC_F_CTB_CIPHER_CTRL_CCML ((uint32_t)(0x7UL << MXC_F_CTB_CIPHER_CTRL_CCML_POS))
303#define MXC_F_CTB_HASH_CTRL_INIT_POS 0
304#define MXC_F_CTB_HASH_CTRL_INIT ((uint32_t)(0x1UL << MXC_F_CTB_HASH_CTRL_INIT_POS))
306#define MXC_F_CTB_HASH_CTRL_XOR_POS 1
307#define MXC_F_CTB_HASH_CTRL_XOR ((uint32_t)(0x1UL << MXC_F_CTB_HASH_CTRL_XOR_POS))
309#define MXC_F_CTB_HASH_CTRL_HASH_POS 2
310#define MXC_F_CTB_HASH_CTRL_HASH ((uint32_t)(0x7UL << MXC_F_CTB_HASH_CTRL_HASH_POS))
311#define MXC_V_CTB_HASH_CTRL_HASH_DIS ((uint32_t)0x0UL)
312#define MXC_S_CTB_HASH_CTRL_HASH_DIS (MXC_V_CTB_HASH_CTRL_HASH_DIS << MXC_F_CTB_HASH_CTRL_HASH_POS)
313#define MXC_V_CTB_HASH_CTRL_HASH_SHA1 ((uint32_t)0x1UL)
314#define MXC_S_CTB_HASH_CTRL_HASH_SHA1 (MXC_V_CTB_HASH_CTRL_HASH_SHA1 << MXC_F_CTB_HASH_CTRL_HASH_POS)
315#define MXC_V_CTB_HASH_CTRL_HASH_SHA224 ((uint32_t)0x2UL)
316#define MXC_S_CTB_HASH_CTRL_HASH_SHA224 (MXC_V_CTB_HASH_CTRL_HASH_SHA224 << MXC_F_CTB_HASH_CTRL_HASH_POS)
317#define MXC_V_CTB_HASH_CTRL_HASH_SHA256 ((uint32_t)0x3UL)
318#define MXC_S_CTB_HASH_CTRL_HASH_SHA256 (MXC_V_CTB_HASH_CTRL_HASH_SHA256 << MXC_F_CTB_HASH_CTRL_HASH_POS)
319#define MXC_V_CTB_HASH_CTRL_HASH_SHA384 ((uint32_t)0x4UL)
320#define MXC_S_CTB_HASH_CTRL_HASH_SHA384 (MXC_V_CTB_HASH_CTRL_HASH_SHA384 << MXC_F_CTB_HASH_CTRL_HASH_POS)
321#define MXC_V_CTB_HASH_CTRL_HASH_SHA512 ((uint32_t)0x5UL)
322#define MXC_S_CTB_HASH_CTRL_HASH_SHA512 (MXC_V_CTB_HASH_CTRL_HASH_SHA512 << MXC_F_CTB_HASH_CTRL_HASH_POS)
324#define MXC_F_CTB_HASH_CTRL_LAST_POS 5
325#define MXC_F_CTB_HASH_CTRL_LAST ((uint32_t)(0x1UL << MXC_F_CTB_HASH_CTRL_LAST_POS))
335#define MXC_F_CTB_CRC_CTRL_CRC_POS 0
336#define MXC_F_CTB_CRC_CTRL_CRC ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_CRC_POS))
338#define MXC_F_CTB_CRC_CTRL_MSB_POS 1
339#define MXC_F_CTB_CRC_CTRL_MSB ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_MSB_POS))
341#define MXC_F_CTB_CRC_CTRL_PRNG_POS 2
342#define MXC_F_CTB_CRC_CTRL_PRNG ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_PRNG_POS))
344#define MXC_F_CTB_CRC_CTRL_ENT_POS 3
345#define MXC_F_CTB_CRC_CTRL_ENT ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_ENT_POS))
347#define MXC_F_CTB_CRC_CTRL_HAM_POS 4
348#define MXC_F_CTB_CRC_CTRL_HAM ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_HAM_POS))
350#define MXC_F_CTB_CRC_CTRL_HRST_POS 5
351#define MXC_F_CTB_CRC_CTRL_HRST ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_HRST_POS))
361#define MXC_F_CTB_DMA_SRC_ADDR_POS 0
362#define MXC_F_CTB_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_DMA_SRC_ADDR_POS))
372#define MXC_F_CTB_DMA_DEST_ADDR_POS 0
373#define MXC_F_CTB_DMA_DEST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_DMA_DEST_ADDR_POS))
383#define MXC_F_CTB_DMA_CNT_CNT_POS 0
384#define MXC_F_CTB_DMA_CNT_CNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_DMA_CNT_CNT_POS))
398#define MXC_F_CTB_CRYPTO_DIN_DATA_POS 0
399#define MXC_F_CTB_CRYPTO_DIN_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CRYPTO_DIN_DATA_POS))
412#define MXC_F_CTB_CRYPTO_DOUT_DATA_POS 0
413#define MXC_F_CTB_CRYPTO_DOUT_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CRYPTO_DOUT_DATA_POS))
425#define MXC_F_CTB_CRC_POLY_POLY_POS 0
426#define MXC_F_CTB_CRC_POLY_POLY ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CRC_POLY_POLY_POS))
438#define MXC_F_CTB_CRC_VAL_VAL_POS 0
439#define MXC_F_CTB_CRC_VAL_VAL ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CRC_VAL_VAL_POS))
451#define MXC_F_CTB_CRC_PRNG_PRNG_POS 0
452#define MXC_F_CTB_CRC_PRNG_PRNG ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CRC_PRNG_PRNG_POS))
462#define MXC_F_CTB_HAM_ECC_ECC_POS 0
463#define MXC_F_CTB_HAM_ECC_ECC ((uint32_t)(0xFFFFUL << MXC_F_CTB_HAM_ECC_ECC_POS))
465#define MXC_F_CTB_HAM_ECC_PAR_POS 16
466#define MXC_F_CTB_HAM_ECC_PAR ((uint32_t)(0x1UL << MXC_F_CTB_HAM_ECC_PAR_POS))
479#define MXC_F_CTB_CIPHER_INIT_IVEC_POS 0
480#define MXC_F_CTB_CIPHER_INIT_IVEC ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CIPHER_INIT_IVEC_POS))
492#define MXC_F_CTB_CIPHER_KEY_KEY_POS 0
493#define MXC_F_CTB_CIPHER_KEY_KEY ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CIPHER_KEY_KEY_POS))
504#define MXC_F_CTB_HASH_DIGEST_HASH_POS 0
505#define MXC_F_CTB_HASH_DIGEST_HASH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_HASH_DIGEST_HASH_POS))
515#define MXC_F_CTB_HASH_MSG_SZ_MSGSZ_POS 0
516#define MXC_F_CTB_HASH_MSG_SZ_MSGSZ ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_HASH_MSG_SZ_MSGSZ_POS))
526#define MXC_F_CTB_A_LENGTH_0_A_LENGTH_POS 0
527#define MXC_F_CTB_A_LENGTH_0_A_LENGTH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_A_LENGTH_0_A_LENGTH_POS))
537#define MXC_F_CTB_A_LENGTH_1_A_LENGTH_POS 0
538#define MXC_F_CTB_A_LENGTH_1_A_LENGTH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_A_LENGTH_1_A_LENGTH_POS))
548#define MXC_F_CTB_PLD_LENGTH_0_PLD_LENGTH_POS 0
549#define MXC_F_CTB_PLD_LENGTH_0_PLD_LENGTH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_PLD_LENGTH_0_PLD_LENGTH_POS))
559#define MXC_F_CTB_PLD_LENGTH_1_PLD_LENGTH_POS 0
560#define MXC_F_CTB_PLD_LENGTH_1_PLD_LENGTH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_PLD_LENGTH_1_PLD_LENGTH_POS))
570#define MXC_F_CTB_TAGMIC_TAGMIC_POS 0
571#define MXC_F_CTB_TAGMIC_TAGMIC ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_TAGMIC_TAGMIC_POS))
581#define MXC_F_CTB_SCA_CN_STC_POS 0
582#define MXC_F_CTB_SCA_CN_STC ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CN_STC_POS))
584#define MXC_F_CTB_SCA_CN_SCAIE_POS 1
585#define MXC_F_CTB_SCA_CN_SCAIE ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CN_SCAIE_POS))
587#define MXC_F_CTB_SCA_CN_ABORT_POS 2
588#define MXC_F_CTB_SCA_CN_ABORT ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CN_ABORT_POS))
590#define MXC_F_CTB_SCA_CN_ERMEM_POS 4
591#define MXC_F_CTB_SCA_CN_ERMEM ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CN_ERMEM_POS))
593#define MXC_F_CTB_SCA_CN_MANPARAM_POS 5
594#define MXC_F_CTB_SCA_CN_MANPARAM ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CN_MANPARAM_POS))
596#define MXC_F_CTB_SCA_CN_HWKEY_POS 6
597#define MXC_F_CTB_SCA_CN_HWKEY ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CN_HWKEY_POS))
599#define MXC_F_CTB_SCA_CN_OPCODE_POS 8
600#define MXC_F_CTB_SCA_CN_OPCODE ((uint32_t)(0x1FUL << MXC_F_CTB_SCA_CN_OPCODE_POS))
602#define MXC_F_CTB_SCA_CN_MODADDR_POS 16
603#define MXC_F_CTB_SCA_CN_MODADDR ((uint32_t)(0x1FUL << MXC_F_CTB_SCA_CN_MODADDR_POS))
605#define MXC_F_CTB_SCA_CN_ECCSIZE_POS 24
606#define MXC_F_CTB_SCA_CN_ECCSIZE ((uint32_t)(0x3UL << MXC_F_CTB_SCA_CN_ECCSIZE_POS))
616#define MXC_F_CTB_SCA_ACN_MAN_POS 0
617#define MXC_F_CTB_SCA_ACN_MAN ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ACN_MAN_POS))
619#define MXC_F_CTB_SCA_ACN_AUTOCARRY_POS 1
620#define MXC_F_CTB_SCA_ACN_AUTOCARRY ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ACN_AUTOCARRY_POS))
622#define MXC_F_CTB_SCA_ACN_PLUSONE_POS 2
623#define MXC_F_CTB_SCA_ACN_PLUSONE ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ACN_PLUSONE_POS))
625#define MXC_F_CTB_SCA_ACN_RESSELECT_POS 3
626#define MXC_F_CTB_SCA_ACN_RESSELECT ((uint32_t)(0x3UL << MXC_F_CTB_SCA_ACN_RESSELECT_POS))
628#define MXC_F_CTB_SCA_ACN_CARRYPOS_POS 8
629#define MXC_F_CTB_SCA_ACN_CARRYPOS ((uint32_t)(0x3FFUL << MXC_F_CTB_SCA_ACN_CARRYPOS_POS))
639#define MXC_F_CTB_SCA_ST_BUSY_POS 0
640#define MXC_F_CTB_SCA_ST_BUSY ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ST_BUSY_POS))
642#define MXC_F_CTB_SCA_ST_SCAIF_POS 1
643#define MXC_F_CTB_SCA_ST_SCAIF ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ST_SCAIF_POS))
645#define MXC_F_CTB_SCA_ST_PVF1_POS 2
646#define MXC_F_CTB_SCA_ST_PVF1 ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ST_PVF1_POS))
648#define MXC_F_CTB_SCA_ST_PVF2_POS 3
649#define MXC_F_CTB_SCA_ST_PVF2 ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ST_PVF2_POS))
651#define MXC_F_CTB_SCA_ST_FSMERR_POS 4
652#define MXC_F_CTB_SCA_ST_FSMERR ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ST_FSMERR_POS))
654#define MXC_F_CTB_SCA_ST_COMPERR_POS 5
655#define MXC_F_CTB_SCA_ST_COMPERR ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ST_COMPERR_POS))
657#define MXC_F_CTB_SCA_ST_MEMERR_POS 6
658#define MXC_F_CTB_SCA_ST_MEMERR ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ST_MEMERR_POS))
660#define MXC_F_CTB_SCA_ST_CARRY_POS 8
661#define MXC_F_CTB_SCA_ST_CARRY ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ST_CARRY_POS))
663#define MXC_F_CTB_SCA_ST_GTE2I2_POS 9
664#define MXC_F_CTB_SCA_ST_GTE2I2 ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ST_GTE2I2_POS))
666#define MXC_F_CTB_SCA_ST_ALUNEG1_POS 10
667#define MXC_F_CTB_SCA_ST_ALUNEG1 ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ST_ALUNEG1_POS))
669#define MXC_F_CTB_SCA_ST_ALUNEG2_POS 11
670#define MXC_F_CTB_SCA_ST_ALUNEG2 ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ST_ALUNEG2_POS))
680#define MXC_F_CTB_SCA_PPX_ADDR_PPX_ADDR_POS 0
681#define MXC_F_CTB_SCA_PPX_ADDR_PPX_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PPX_ADDR_PPX_ADDR_POS))
691#define MXC_F_CTB_SCA_PPY_ADDR_PPY_ADDR_POS 0
692#define MXC_F_CTB_SCA_PPY_ADDR_PPY_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PPY_ADDR_PPY_ADDR_POS))
702#define MXC_F_CTB_SCA_PPZ_ADDR_PPZ_ADDR_POS 0
703#define MXC_F_CTB_SCA_PPZ_ADDR_PPZ_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PPZ_ADDR_PPZ_ADDR_POS))
713#define MXC_F_CTB_SCA_PQX_ADDR_PQX_ADDR_POS 0
714#define MXC_F_CTB_SCA_PQX_ADDR_PQX_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PQX_ADDR_PQX_ADDR_POS))
724#define MXC_F_CTB_SCA_PQY_ADDR_PQY_ADDR_POS 0
725#define MXC_F_CTB_SCA_PQY_ADDR_PQY_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PQY_ADDR_PQY_ADDR_POS))
735#define MXC_F_CTB_SCA_PQZ_ADDR_PQZ_ADDR_POS 0
736#define MXC_F_CTB_SCA_PQZ_ADDR_PQZ_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PQZ_ADDR_PQZ_ADDR_POS))
746#define MXC_F_CTB_SCA_RDSA_ADDR_RDSA_ADDR_POS 0
747#define MXC_F_CTB_SCA_RDSA_ADDR_RDSA_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_RDSA_ADDR_RDSA_ADDR_POS))
757#define MXC_F_CTB_SCA_RES_ADDR_RES_ADDR_POS 0
758#define MXC_F_CTB_SCA_RES_ADDR_RES_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_RES_ADDR_RES_ADDR_POS))
768#define MXC_F_CTB_SCA_OP_BUFF_ADDR_OPBUFF_ADDR_POS 0
769#define MXC_F_CTB_SCA_OP_BUFF_ADDR_OPBUFF_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_OP_BUFF_ADDR_OPBUFF_ADDR_POS))
779#define MXC_F_CTB_SCA_MODDATA_MODDATA_POS 0
780#define MXC_F_CTB_SCA_MODDATA_MODDATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_MODDATA_MODDATA_POS))
784#ifdef __cplusplus
785}
786#endif
787
788#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_CTB_REGS_H_
__IO uint32_t crc_ctrl
Definition: ctb_regs.h:80
__IO uint32_t crc_poly
Definition: ctb_regs.h:87
__IO uint32_t sca_ppy_addr
Definition: ctb_regs.h:105
__IO uint32_t crc_val
Definition: ctb_regs.h:88
__IO uint32_t pld_length_0
Definition: ctb_regs.h:97
__IO uint32_t dma_dest
Definition: ctb_regs.h:82
__IO uint32_t dma_cnt
Definition: ctb_regs.h:83
__IO uint32_t sca_pqz_addr
Definition: ctb_regs.h:109
__IO uint32_t crypto_ctrl
Definition: ctb_regs.h:77
__IO uint32_t sca_acn
Definition: ctb_regs.h:102
__IO uint32_t dma_src
Definition: ctb_regs.h:81
__IO uint32_t crc_prng
Definition: ctb_regs.h:89
__IO uint32_t sca_cn
Definition: ctb_regs.h:101
__IO uint32_t sca_rdsa_addr
Definition: ctb_regs.h:110
__IO uint32_t pld_length_1
Definition: ctb_regs.h:98
__IO uint32_t sca_pqx_addr
Definition: ctb_regs.h:107
__IO uint32_t sca_ppz_addr
Definition: ctb_regs.h:106
__IO uint32_t a_length_0
Definition: ctb_regs.h:95
__IO uint32_t hash_ctrl
Definition: ctb_regs.h:79
__IO uint32_t sca_pqy_addr
Definition: ctb_regs.h:108
__IO uint32_t sca_res_addr
Definition: ctb_regs.h:111
__IO uint32_t sca_st
Definition: ctb_regs.h:103
__IO uint32_t cipher_ctrl
Definition: ctb_regs.h:78
__IO uint32_t ham_ecc
Definition: ctb_regs.h:90
__IO uint32_t a_length_1
Definition: ctb_regs.h:96
__IO uint32_t sca_ppx_addr
Definition: ctb_regs.h:104
__IO uint32_t sca_op_buff_addr
Definition: ctb_regs.h:112
__IO uint32_t sca_moddata
Definition: ctb_regs.h:113
Definition: ctb_regs.h:76