flc_regs.h

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/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_FLC_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_FLC_REGS_H_
 
/* **** Includes **** */
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined (__ICCARM__)
  #pragma system_include
#endif
 
#if defined (__CC_ARM)
  #pragma anon_unions
#endif
/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif
#ifndef __R
#define __R  volatile const
#endif
 
/* **** Definitions **** */
 
typedef struct {
    __IO uint32_t flsh_addr;            
    __IO uint32_t flsh_clkdiv;          
    __IO uint32_t flsh_cn;              
    __R  uint32_t rsv_0xc_0x23[6];
    __IO uint32_t flsh_int;             
    __R  uint32_t rsv_0x28_0x2f[2];
    __IO uint32_t flsh_data[4];         
    __O  uint32_t acntl;                
} mxc_flc_regs_t;
 
/* Register offsets for module FLC */
#define MXC_R_FLC_FLSH_ADDR                ((uint32_t)0x00000000UL) 
#define MXC_R_FLC_FLSH_CLKDIV              ((uint32_t)0x00000004UL) 
#define MXC_R_FLC_FLSH_CN                  ((uint32_t)0x00000008UL) 
#define MXC_R_FLC_FLSH_INT                 ((uint32_t)0x00000024UL) 
#define MXC_R_FLC_FLSH_DATA                ((uint32_t)0x00000030UL) 
#define MXC_R_FLC_ACNTL                    ((uint32_t)0x00000040UL) 
#define MXC_F_FLC_FLSH_ADDR_ADDR_POS                   0 
#define MXC_F_FLC_FLSH_ADDR_ADDR                       ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_FLSH_ADDR_ADDR_POS)) 
#define MXC_F_FLC_FLSH_CLKDIV_CLKDIV_POS               0 
#define MXC_F_FLC_FLSH_CLKDIV_CLKDIV                   ((uint32_t)(0xFFUL << MXC_F_FLC_FLSH_CLKDIV_CLKDIV_POS)) 
#define MXC_F_FLC_FLSH_CN_WR_POS                       0 
#define MXC_F_FLC_FLSH_CN_WR                           ((uint32_t)(0x1UL << MXC_F_FLC_FLSH_CN_WR_POS)) 
#define MXC_F_FLC_FLSH_CN_ME_POS                       1 
#define MXC_F_FLC_FLSH_CN_ME                           ((uint32_t)(0x1UL << MXC_F_FLC_FLSH_CN_ME_POS)) 
#define MXC_F_FLC_FLSH_CN_PGE_POS                      2 
#define MXC_F_FLC_FLSH_CN_PGE                          ((uint32_t)(0x1UL << MXC_F_FLC_FLSH_CN_PGE_POS)) 
#define MXC_F_FLC_FLSH_CN_ERASE_CODE_POS               8 
#define MXC_F_FLC_FLSH_CN_ERASE_CODE                   ((uint32_t)(0xFFUL << MXC_F_FLC_FLSH_CN_ERASE_CODE_POS)) 
#define MXC_V_FLC_FLSH_CN_ERASE_CODE_NOP               ((uint32_t)0x0UL) 
#define MXC_S_FLC_FLSH_CN_ERASE_CODE_NOP               (MXC_V_FLC_FLSH_CN_ERASE_CODE_NOP << MXC_F_FLC_FLSH_CN_ERASE_CODE_POS) 
#define MXC_V_FLC_FLSH_CN_ERASE_CODE_ERASEPAGE         ((uint32_t)0x55UL) 
#define MXC_S_FLC_FLSH_CN_ERASE_CODE_ERASEPAGE         (MXC_V_FLC_FLSH_CN_ERASE_CODE_ERASEPAGE << MXC_F_FLC_FLSH_CN_ERASE_CODE_POS) 
#define MXC_V_FLC_FLSH_CN_ERASE_CODE_ERASEALL          ((uint32_t)0xAAUL) 
#define MXC_S_FLC_FLSH_CN_ERASE_CODE_ERASEALL          (MXC_V_FLC_FLSH_CN_ERASE_CODE_ERASEALL << MXC_F_FLC_FLSH_CN_ERASE_CODE_POS) 
#define MXC_F_FLC_FLSH_CN_PEND_POS                     24 
#define MXC_F_FLC_FLSH_CN_PEND                         ((uint32_t)(0x1UL << MXC_F_FLC_FLSH_CN_PEND_POS)) 
#define MXC_F_FLC_FLSH_CN_UNLOCK_POS                   28 
#define MXC_F_FLC_FLSH_CN_UNLOCK                       ((uint32_t)(0xFUL << MXC_F_FLC_FLSH_CN_UNLOCK_POS)) 
#define MXC_V_FLC_FLSH_CN_UNLOCK_UNLOCKED              ((uint32_t)0x2UL) 
#define MXC_S_FLC_FLSH_CN_UNLOCK_UNLOCKED              (MXC_V_FLC_FLSH_CN_UNLOCK_UNLOCKED << MXC_F_FLC_FLSH_CN_UNLOCK_POS) 
#define MXC_V_FLC_FLSH_CN_UNLOCK_LOCKED                ((uint32_t)0x3UL) 
#define MXC_S_FLC_FLSH_CN_UNLOCK_LOCKED                (MXC_V_FLC_FLSH_CN_UNLOCK_LOCKED << MXC_F_FLC_FLSH_CN_UNLOCK_POS) 
#define MXC_F_FLC_FLSH_INT_DONE_POS                    0 
#define MXC_F_FLC_FLSH_INT_DONE                        ((uint32_t)(0x1UL << MXC_F_FLC_FLSH_INT_DONE_POS)) 
#define MXC_F_FLC_FLSH_INT_AF_POS                      1 
#define MXC_F_FLC_FLSH_INT_AF                          ((uint32_t)(0x1UL << MXC_F_FLC_FLSH_INT_AF_POS)) 
#define MXC_F_FLC_FLSH_INT_DONEIE_POS                  8 
#define MXC_F_FLC_FLSH_INT_DONEIE                      ((uint32_t)(0x1UL << MXC_F_FLC_FLSH_INT_DONEIE_POS)) 
#define MXC_F_FLC_FLSH_INT_AFIE_POS                    9 
#define MXC_F_FLC_FLSH_INT_AFIE                        ((uint32_t)(0x1UL << MXC_F_FLC_FLSH_INT_AFIE_POS)) 
#define MXC_F_FLC_FLSH_DATA_DATA_POS                   0 
#define MXC_F_FLC_FLSH_DATA_DATA                       ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_FLSH_DATA_DATA_POS)) 
#define MXC_F_FLC_ACNTL_ADATA_POS                      0 
#define MXC_F_FLC_ACNTL_ADATA                          ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACNTL_ADATA_POS)) 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_FLC_REGS_H_