pwrseq_regs.h

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/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_PWRSEQ_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_PWRSEQ_REGS_H_
 
/* **** Includes **** */
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined (__ICCARM__)
  #pragma system_include
#endif
 
#if defined (__CC_ARM)
  #pragma anon_unions
#endif
/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif
#ifndef __R
#define __R  volatile const
#endif
 
/* **** Definitions **** */
 
typedef struct {
    __IO uint32_t lpcn;                 
    __IO uint32_t lpwkst0;              
    __IO uint32_t lpwken0;              
    __IO uint32_t lpwkst1;              
    __IO uint32_t lpwken1;              
    __R  uint32_t rsv_0x14_0x2f[7];
    __IO uint32_t lppwkst;              
    __R  uint32_t rsv_0x34_0x3f[3];
    __IO uint32_t lpmemsd;              
    __R  uint32_t rsv_0x44;
    __IO uint32_t gp0;                  
    __IO uint32_t gp1;                  
} mxc_pwrseq_regs_t;
 
/* Register offsets for module PWRSEQ */
#define MXC_R_PWRSEQ_LPCN                  ((uint32_t)0x00000000UL) 
#define MXC_R_PWRSEQ_LPWKST0               ((uint32_t)0x00000004UL) 
#define MXC_R_PWRSEQ_LPWKEN0               ((uint32_t)0x00000008UL) 
#define MXC_R_PWRSEQ_LPWKST1               ((uint32_t)0x0000000CUL) 
#define MXC_R_PWRSEQ_LPWKEN1               ((uint32_t)0x00000010UL) 
#define MXC_R_PWRSEQ_LPPWKST               ((uint32_t)0x00000030UL) 
#define MXC_R_PWRSEQ_LPMEMSD               ((uint32_t)0x00000040UL) 
#define MXC_R_PWRSEQ_GP0                   ((uint32_t)0x00000048UL) 
#define MXC_R_PWRSEQ_GP1                   ((uint32_t)0x0000004CUL) 
#define MXC_F_PWRSEQ_LPCN_RAMRET_EN_POS                0 
#define MXC_F_PWRSEQ_LPCN_RAMRET_EN                    ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCN_RAMRET_EN_POS)) 
#define MXC_F_PWRSEQ_LPCN_LDO_DIS_POS                  16 
#define MXC_F_PWRSEQ_LPCN_LDO_DIS                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_LDO_DIS_POS)) 
#define MXC_F_PWRSEQ_LPCN_VCOREMON_DIS_POS             20 
#define MXC_F_PWRSEQ_LPCN_VCOREMON_DIS                 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREMON_DIS_POS)) 
#define MXC_F_PWRSEQ_LPCN_VDDAMON_DIS_POS              22 
#define MXC_F_PWRSEQ_LPCN_VDDAMON_DIS                  ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDAMON_DIS_POS)) 
#define MXC_F_PWRSEQ_LPWKST0_ST_POS                    0 
#define MXC_F_PWRSEQ_LPWKST0_ST                        ((uint32_t)(0xFFFFUL << MXC_F_PWRSEQ_LPWKST0_ST_POS)) 
#define MXC_F_PWRSEQ_LPWKEN0_EN_POS                    0 
#define MXC_F_PWRSEQ_LPWKEN0_EN                        ((uint32_t)(0xFFFFUL << MXC_F_PWRSEQ_LPWKEN0_EN_POS)) 
#define MXC_F_PWRSEQ_LPWKST1_ST_POS                    0 
#define MXC_F_PWRSEQ_LPWKST1_ST                        ((uint32_t)(0x7FFUL << MXC_F_PWRSEQ_LPWKST1_ST_POS)) 
#define MXC_F_PWRSEQ_LPWKEN1_EN_POS                    0 
#define MXC_F_PWRSEQ_LPWKEN1_EN                        ((uint32_t)(0x7FFUL << MXC_F_PWRSEQ_LPWKEN1_EN_POS)) 
#define MXC_F_PWRSEQ_LPPWKST_BBMOD_POS                 16 
#define MXC_F_PWRSEQ_LPPWKST_BBMOD                     ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_BBMOD_POS)) 
#define MXC_F_PWRSEQ_LPPWKST_RST_POS                   17 
#define MXC_F_PWRSEQ_LPPWKST_RST                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_RST_POS)) 
#define MXC_F_PWRSEQ_LPPWKST_SDMA1_POS                 18 
#define MXC_F_PWRSEQ_LPPWKST_SDMA1                     ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_SDMA1_POS)) 
#define MXC_F_PWRSEQ_LPMEMSD_RAM0_POS                  0 
#define MXC_F_PWRSEQ_LPMEMSD_RAM0                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM0_POS)) 
#define MXC_F_PWRSEQ_LPMEMSD_RAM1_POS                  1 
#define MXC_F_PWRSEQ_LPMEMSD_RAM1                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM1_POS)) 
#define MXC_F_PWRSEQ_LPMEMSD_RAM2_POS                  2 
#define MXC_F_PWRSEQ_LPMEMSD_RAM2                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM2_POS)) 
#define MXC_F_PWRSEQ_LPMEMSD_RAM3_POS                  3 
#define MXC_F_PWRSEQ_LPMEMSD_RAM3                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM3_POS)) 
#define MXC_F_PWRSEQ_LPMEMSD_RAM4_POS                  4 
#define MXC_F_PWRSEQ_LPMEMSD_RAM4                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM4_POS)) 
#define MXC_F_PWRSEQ_LPMEMSD_ICACHE_POS                7 
#define MXC_F_PWRSEQ_LPMEMSD_ICACHE                    ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICACHE_POS)) 
#define MXC_F_PWRSEQ_LPMEMSD_ICACHEXIP_POS             8 
#define MXC_F_PWRSEQ_LPMEMSD_ICACHEXIP                 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICACHEXIP_POS)) 
#define MXC_F_PWRSEQ_LPMEMSD_ROM_POS                   12 
#define MXC_F_PWRSEQ_LPMEMSD_ROM                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ROM_POS)) 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_PWRSEQ_REGS_H_