MAX32520 Peripheral Driver API
Peripheral Driver API for the MAX32520
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tmr_regs.h
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1
8/******************************************************************************
9 *
10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
11 * Analog Devices, Inc.),
12 * Copyright (C) 2023-2024 Analog Devices, Inc.
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 * http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *
26 ******************************************************************************/
27
28#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_TMR_REGS_H_
29#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_TMR_REGS_H_
30
31/* **** Includes **** */
32#include <stdint.h>
33
34#ifdef __cplusplus
35extern "C" {
36#endif
37
38#if defined (__ICCARM__)
39 #pragma system_include
40#endif
41
42#if defined (__CC_ARM)
43 #pragma anon_unions
44#endif
46/*
47 If types are not defined elsewhere (CMSIS) define them here
48*/
49#ifndef __IO
50#define __IO volatile
51#endif
52#ifndef __I
53#define __I volatile const
54#endif
55#ifndef __O
56#define __O volatile
57#endif
58#ifndef __R
59#define __R volatile const
60#endif
62
63/* **** Definitions **** */
64
76typedef struct {
77 __IO uint32_t cnt;
78 __IO uint32_t cmp;
79 __IO uint32_t pwm;
80 __IO uint32_t intr;
81 __IO uint32_t cn;
82} mxc_tmr_regs_t;
83
84/* Register offsets for module TMR */
91#define MXC_R_TMR_CNT ((uint32_t)0x00000000UL)
92#define MXC_R_TMR_CMP ((uint32_t)0x00000004UL)
93#define MXC_R_TMR_PWM ((uint32_t)0x00000008UL)
94#define MXC_R_TMR_INTR ((uint32_t)0x0000000CUL)
95#define MXC_R_TMR_CN ((uint32_t)0x00000010UL)
105#define MXC_F_TMR_INTR_IRQ_CLR_POS 0
106#define MXC_F_TMR_INTR_IRQ_CLR ((uint32_t)(0x1UL << MXC_F_TMR_INTR_IRQ_CLR_POS))
116#define MXC_F_TMR_CN_TMODE_POS 0
117#define MXC_F_TMR_CN_TMODE ((uint32_t)(0x7UL << MXC_F_TMR_CN_TMODE_POS))
118#define MXC_V_TMR_CN_TMODE_ONESHOT ((uint32_t)0x0UL)
119#define MXC_S_TMR_CN_TMODE_ONESHOT (MXC_V_TMR_CN_TMODE_ONESHOT << MXC_F_TMR_CN_TMODE_POS)
120#define MXC_V_TMR_CN_TMODE_CONTINUOUS ((uint32_t)0x1UL)
121#define MXC_S_TMR_CN_TMODE_CONTINUOUS (MXC_V_TMR_CN_TMODE_CONTINUOUS << MXC_F_TMR_CN_TMODE_POS)
122#define MXC_V_TMR_CN_TMODE_COUNTER ((uint32_t)0x2UL)
123#define MXC_S_TMR_CN_TMODE_COUNTER (MXC_V_TMR_CN_TMODE_COUNTER << MXC_F_TMR_CN_TMODE_POS)
124#define MXC_V_TMR_CN_TMODE_PWM ((uint32_t)0x3UL)
125#define MXC_S_TMR_CN_TMODE_PWM (MXC_V_TMR_CN_TMODE_PWM << MXC_F_TMR_CN_TMODE_POS)
126#define MXC_V_TMR_CN_TMODE_CAPTURE ((uint32_t)0x4UL)
127#define MXC_S_TMR_CN_TMODE_CAPTURE (MXC_V_TMR_CN_TMODE_CAPTURE << MXC_F_TMR_CN_TMODE_POS)
128#define MXC_V_TMR_CN_TMODE_COMPARE ((uint32_t)0x5UL)
129#define MXC_S_TMR_CN_TMODE_COMPARE (MXC_V_TMR_CN_TMODE_COMPARE << MXC_F_TMR_CN_TMODE_POS)
130#define MXC_V_TMR_CN_TMODE_GATED ((uint32_t)0x6UL)
131#define MXC_S_TMR_CN_TMODE_GATED (MXC_V_TMR_CN_TMODE_GATED << MXC_F_TMR_CN_TMODE_POS)
132#define MXC_V_TMR_CN_TMODE_CAPTURECOMPARE ((uint32_t)0x7UL)
133#define MXC_S_TMR_CN_TMODE_CAPTURECOMPARE (MXC_V_TMR_CN_TMODE_CAPTURECOMPARE << MXC_F_TMR_CN_TMODE_POS)
135#define MXC_F_TMR_CN_PRES_POS 3
136#define MXC_F_TMR_CN_PRES ((uint32_t)(0x7UL << MXC_F_TMR_CN_PRES_POS))
137#define MXC_V_TMR_CN_PRES_DIV1 ((uint32_t)0x0UL)
138#define MXC_S_TMR_CN_PRES_DIV1 (MXC_V_TMR_CN_PRES_DIV1 << MXC_F_TMR_CN_PRES_POS)
139#define MXC_V_TMR_CN_PRES_DIV2 ((uint32_t)0x1UL)
140#define MXC_S_TMR_CN_PRES_DIV2 (MXC_V_TMR_CN_PRES_DIV2 << MXC_F_TMR_CN_PRES_POS)
141#define MXC_V_TMR_CN_PRES_DIV4 ((uint32_t)0x2UL)
142#define MXC_S_TMR_CN_PRES_DIV4 (MXC_V_TMR_CN_PRES_DIV4 << MXC_F_TMR_CN_PRES_POS)
143#define MXC_V_TMR_CN_PRES_DIV8 ((uint32_t)0x3UL)
144#define MXC_S_TMR_CN_PRES_DIV8 (MXC_V_TMR_CN_PRES_DIV8 << MXC_F_TMR_CN_PRES_POS)
145#define MXC_V_TMR_CN_PRES_DIV16 ((uint32_t)0x4UL)
146#define MXC_S_TMR_CN_PRES_DIV16 (MXC_V_TMR_CN_PRES_DIV16 << MXC_F_TMR_CN_PRES_POS)
147#define MXC_V_TMR_CN_PRES_DIV32 ((uint32_t)0x5UL)
148#define MXC_S_TMR_CN_PRES_DIV32 (MXC_V_TMR_CN_PRES_DIV32 << MXC_F_TMR_CN_PRES_POS)
149#define MXC_V_TMR_CN_PRES_DIV64 ((uint32_t)0x6UL)
150#define MXC_S_TMR_CN_PRES_DIV64 (MXC_V_TMR_CN_PRES_DIV64 << MXC_F_TMR_CN_PRES_POS)
151#define MXC_V_TMR_CN_PRES_DIV128 ((uint32_t)0x7UL)
152#define MXC_S_TMR_CN_PRES_DIV128 (MXC_V_TMR_CN_PRES_DIV128 << MXC_F_TMR_CN_PRES_POS)
154#define MXC_F_TMR_CN_TPOL_POS 6
155#define MXC_F_TMR_CN_TPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_TPOL_POS))
157#define MXC_F_TMR_CN_TEN_POS 7
158#define MXC_F_TMR_CN_TEN ((uint32_t)(0x1UL << MXC_F_TMR_CN_TEN_POS))
160#define MXC_F_TMR_CN_PRES3_POS 8
161#define MXC_F_TMR_CN_PRES3 ((uint32_t)(0x1UL << MXC_F_TMR_CN_PRES3_POS))
163#define MXC_F_TMR_CN_PWMSYNC_POS 9
164#define MXC_F_TMR_CN_PWMSYNC ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMSYNC_POS))
166#define MXC_F_TMR_CN_NOLHPOL_POS 10
167#define MXC_F_TMR_CN_NOLHPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLHPOL_POS))
169#define MXC_F_TMR_CN_NOLLPOL_POS 11
170#define MXC_F_TMR_CN_NOLLPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLLPOL_POS))
172#define MXC_F_TMR_CN_PWMCKBD_POS 12
173#define MXC_F_TMR_CN_PWMCKBD ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMCKBD_POS))
177#ifdef __cplusplus
178}
179#endif
180
181#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_TMR_REGS_H_
mxc_tmr_regs_t::cn
__IO uint32_t cn
Definition: tmr_regs.h:81
mxc_tmr_regs_t::pwm
__IO uint32_t pwm
Definition: tmr_regs.h:79
mxc_tmr_regs_t::cnt
__IO uint32_t cnt
Definition: tmr_regs.h:77
mxc_tmr_regs_t::cmp
__IO uint32_t cmp
Definition: tmr_regs.h:78
mxc_tmr_regs_t::intr
__IO uint32_t intr
Definition: tmr_regs.h:80
mxc_tmr_regs_t
Definition: tmr_regs.h:76