MAX32650 Peripheral Driver API
Peripheral Driver API for the MAX32650
max32650.h
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/******************************************************************************
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*
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* Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
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* Analog Devices, Inc.),
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* Copyright (C) 2023-2024 Analog Devices, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************/
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#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_MAX32650_H_
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#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_MAX32650_H_
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#ifndef TARGET_NUM
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#define TARGET_NUM 32650
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#endif
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#include <stdint.h>
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#ifndef FALSE
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#define FALSE (0)
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#endif
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#ifndef TRUE
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#define TRUE (1)
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#endif
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#if !defined(__GNUC__)
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#define CMSIS_VECTAB_VIRTUAL
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#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "nvic_table.h"
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#endif
/* !__GNUC__ */
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/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
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#if defined(__GNUC__)
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#ifndef __weak
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#define __weak __attribute__((weak))
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#endif
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#elif defined(__CC_ARM)
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#define inline __inline
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#pragma anon_unions
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#endif
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typedef
enum
{
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NonMaskableInt_IRQn = -14,
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HardFault_IRQn = -13,
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MemoryManagement_IRQn = -12,
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BusFault_IRQn = -11,
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UsageFault_IRQn = -10,
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SVCall_IRQn = -5,
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DebugMonitor_IRQn = -4,
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PendSV_IRQn = -2,
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SysTick_IRQn = -1,
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/* Device-specific interrupt sources (external to ARM core) */
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/* table entry number */
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/* |||| */
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/* |||| table offset address */
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/* vvvv vvvvvv */
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PF_IRQn = 0,
/* 0x10 0x0040 16: Power Fail */
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WDT0_IRQn,
/* 0x11 0x0044 17: Watchdog 0 */
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USB_IRQn,
/* 0x12 0x0048 18: USB */
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RTC_IRQn,
/* 0x13 0x004C 19: RTC */
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TRNG_IRQn,
/* 0x14 0x0050 20: True Random Number Generator */
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TMR0_IRQn,
/* 0x15 0x0054 21: Timer 0 */
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TMR1_IRQn,
/* 0x16 0x0058 22: Timer 1 */
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TMR2_IRQn,
/* 0x17 0x005C 23: Timer 2 */
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TMR3_IRQn,
/* 0x18 0x0060 24: Timer 3*/
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TMR4_IRQn,
/* 0x19 0x0064 25: Timer 4*/
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TMR5_IRQn,
/* 0x1A 0x0068 26: Timer 5 */
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RSV11_IRQn,
/* 0x1B 0x006C 27: Reserved */
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LCD_IRQn,
/* 0x1C 0x0070 28: LCD Controller*/
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I2C0_IRQn,
/* 0x1D 0x0074 29: I2C0 */
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UART0_IRQn,
/* 0x1E 0x0078 30: UART 0 */
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UART1_IRQn,
/* 0x1F 0x007C 31: UART 1 */
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SPI0_IRQn,
/* 0x20 0x0080 32: SPI0 */
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SPI1_IRQn,
/* 0x21 0x0084 33: SPI1 */
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SPI2_IRQn,
/* 0x22 0x0088 34: SPI2 */
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RSV19_IRQn,
/* 0x23 0x008C 35: Reserved */
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ADC_IRQn,
/* 0x24 0x0090 36: ADC */
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RSV21_IRQn,
/* 0x25 0x0094 37: Reserved */
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RSV22_IRQn,
/* 0x26 0x0098 38: Reserved */
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FLC_IRQn,
/* 0x27 0x009C 39: Flash Controller */
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GPIO0_IRQn,
/* 0x28 0x00A0 40: GPIO0 */
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GPIO1_IRQn,
/* 0x29 0x00A4 41: GPIO2 */
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GPIO2_IRQn,
/* 0x2A 0x00A8 42: GPIO3 */
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TPU_IRQn,
/* 0x2B 0x00AC 43: TPU */
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DMA0_IRQn,
/* 0x2C 0x00B0 44: DMA0 */
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DMA1_IRQn,
/* 0x2D 0x00B4 45: DMA1 */
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DMA2_IRQn,
/* 0x2E 0x00B8 46: DMA2 */
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DMA3_IRQn,
/* 0x2F 0x00BC 47: DMA3 */
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RSV32_IRQn,
/* 0x30 0x00C0 48: Reserved */
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RSV33_IRQn,
/* 0x31 0x00C4 49: Reserved */
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UART2_IRQn,
/* 0x32 0x00C8 50: UART 2 */
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RSV35_IRQn,
/* 0x33 0x00CC 51: Reserved */
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I2C1_IRQn,
/* 0x34 0x00D0 52: I2C1 */
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RSV37_IRQn,
/* 0x35 0x00D4 53: Reserved */
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SPIXFC_IRQn,
/* 0x36 0x00D8 54: SPI execute in place */
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RSV39_IRQn,
/* 0x37 0x00DC 55: Reserved */
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RSV40_IRQn,
/* 0x38 0x00E0 56: Reserved */
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RSV41_IRQn,
/* 0x39 0x00E4 57: Reserved */
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RSV42_IRQn,
/* 0x3A 0x00E8 58: Reserved */
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RSV43_IRQn,
/* 0x3B 0x00EC 59: Reserved */
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RSV44_IRQn,
/* 0x3C 0x00F0 60: Reserved */
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RSV45_IRQn,
/* 0x3D 0x00F4 61: Reserved */
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RSV46_IRQn,
/* 0x3E 0x00F8 62: Reserved */
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RSV47_IRQn,
/* 0x3F 0x00FC 63: Reserved */
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RSV48_IRQn,
/* 0x40 0x0100 64: Reserved */
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RSV49_IRQn,
/* 0x41 0x0104 65: Reserved */
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RSV50_IRQn,
/* 0x42 0x0108 66: Reserved */
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RSV51_IRQn,
/* 0x43 0x010C 67: Reserved */
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RSV52_IRQn,
/* 0x44 0x0110 68: Reserved */
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RSV53_IRQn,
/* 0x45 0x0114 69: Reserved */
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GPIOWAKE_IRQn,
/* 0x46 0x0118 70: GPIO Wakeup */
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RSV55_IRQn,
/* 0x47 0x011C 71: Reserved */
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SPI3_IRQn,
/* 0x48 0x0120 72: SPI3 */
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WDT1_IRQn,
/* 0x49 0x0124 73: Watchdog 1 */
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GPIO3_IRQn,
/* 0x4A 0x0128 74: GPIO3 */
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PT_IRQn,
/* 0x4B 0x012C 75: Pulse train */
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SDMA_IRQn,
/* 0x4C 0x0130 76: Smart DMA */
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HBMC_IRQn,
/* 0x4D 0x0134 77: HyperBus */
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RSV62_IRQn,
/* 0x4E 0x0138 78: Reserved */
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RSV63_IRQn,
/* 0x4F 0x013C 79: Reserved */
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RSV64_IRQn,
/* 0x50 0x0140 80: Reserved */
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RSV65_IRQn,
/* 0x51 0x0144 81: Reserved */
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SDHC_IRQn,
/* 0x52 0x0148 82: SDIO/SDHC */
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OWM_IRQn,
/* 0x53 0x014C 83: One Wire Master */
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DMA4_IRQn,
/* 0x54 0x0150 84: DMA4 */
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DMA5_IRQn,
/* 0x55 0x0154 85: DMA5 */
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DMA6_IRQn,
/* 0x56 0x0158 86: DMA6 */
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DMA7_IRQn,
/* 0x57 0x015C 87: DMA7 */
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DMA8_IRQn,
/* 0x58 0x0160 88: DMA8 */
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DMA9_IRQn,
/* 0x59 0x0164 89: DMA9 */
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DMA10_IRQn,
/* 0x5A 0x0168 90: DMA10 */
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DMA11_IRQn,
/* 0x5B 0x016C 91: DMA11 */
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DMA12_IRQn,
/* 0x5C 0x0170 92: DMA12 */
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DMA13_IRQn,
/* 0x5D 0x0174 93: DMA13 */
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DMA14_IRQn,
/* 0x5E 0x0178 94: DMA14 */
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DMA15_IRQn,
/* 0x5F 0x017C 95: DMA15 */
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USBDMA_IRQn,
/* 0x60 0x0180 96: USB DMA */
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MXC_IRQ_EXT_COUNT,
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} IRQn_Type;
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#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
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/* ================================================================================ */
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/* ================ Processor and Core Peripheral Section ================ */
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/* ================================================================================ */
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/* ------------------------ Configuration of the Cortex-M Processor and Core Peripherals ------------------------ */
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#define __CM4_REV 0x0100
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#define __MPU_PRESENT 1
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#define __NVIC_PRIO_BITS 3
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#define __Vendor_SysTickConfig 0
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#define __FPU_PRESENT 1
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#include <core_cm4.h>
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#include "system_max32650.h"
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/* ================================================================================ */
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/* ================== Device Specific Memory Section ================== */
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/* ================================================================================ */
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#define MXC_ROM_MEM_BASE 0x00000000UL
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#define MXC_ROM_MEM_SIZE 0x00020000UL
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#define MXC_XIP_MEM_BASE 0x08000000UL
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#define MXC_XIP_MEM_SIZE 0x08000000UL
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#define MXC_FLASH_MEM_BASE 0x10000000UL
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#define MXC_FLASH_PAGE_SIZE 0x00004000UL
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#define MXC_FLASH_MEM_SIZE 0x00300000UL
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#define MXC_INFO_MEM_BASE 0x10800000UL
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#define MXC_INFO_MEM_SIZE 0x00004000UL
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#define MXC_SRAM_MEM_BASE 0x20000000UL
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#define MXC_SRAM_MEM_SIZE 0x00100000UL
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#define MXC_HBMC_MEM_BASE 0x60000000UL
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#define MXC_HBMC_MEM_SIZE 0x20000000UL
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#define MXC_XIP_DATA_MEM_BASE 0x80000000UL
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#define MXC_XIP_DATA_MEM_SIZE 0x20000000UL
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/* ================================================================================ */
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/* ================ Device Specific Peripheral Section ================ */
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/* ================================================================================ */
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/*
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Base addresses and configuration settings for all MAX32650 peripheral modules.
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*/
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/* ************************************************************************** */
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/* Global control */
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#define MXC_BASE_GCR ((uint32_t)0x40000000UL)
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#define MXC_GCR ((mxc_gcr_regs_t *)MXC_BASE_GCR)
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/* ************************************************************************** */
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/* Non-battery backed SI Registers */
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#define MXC_BASE_SIR ((uint32_t)0x40000400UL)
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#define MXC_SIR ((mxc_sir_regs_t *)MXC_BASE_SIR)
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/* ************************************************************************** */
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/* Non-battery backed Function Control */
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#define MXC_BASE_NBBFC ((uint32_t)0x40000800UL)
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#define MXC_NBBFC ((mxc_nbbfc_regs_t *)MXC_BASE_NBBFC)
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/* ************************************************************************** */
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/* TPU */
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#define MXC_BASE_TPU ((uint32_t)0x40001000UL)
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#define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU)
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/* ************************************************************************** */
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/* Watchdog */
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#define MXC_BASE_WDT0 ((uint32_t)0x40003000UL)
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#define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
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#define MXC_BASE_WDT1 ((uint32_t)0x40003400UL)
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#define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1)
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/* ************************************************************************** */
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/* Security Monitor */
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#define MXC_BASE_SMON ((uint32_t)0x40004000UL)
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#define MXC_SMON ((mxc_smon_regs_t *)MXC_BASE_SMON)
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/* ************************************************************************** */
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/* AES Keys */
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#define MXC_BASE_AESKEYS ((uint32_t)0x40005000UL)
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#define MXC_AESKEYS ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS)
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/* ************************************************************************** */
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/* Trim System Initialization Registers */
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#define MXC_BASE_TRIMSIR ((uint32_t)0x40005400UL)
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#define MXC_TRIMSIR ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR)
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/* ************************************************************************** */
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/* BBFC */
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#define MXC_BASE_BBFC ((uint32_t)0x40005800UL)
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#define MXC_BBFC ((mxc_bbfc_regs_t *)MXC_BASE_BBFC)
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/* ************************************************************************** */
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/* Real Time Clock */
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#define MXC_BASE_RTC ((uint32_t)0x40006000UL)
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#define MXC_RTC ((mxc_rtc_regs_t *)MXC_BASE_RTC)
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/* ************************************************************************** */
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/* Power Sequencer */
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#define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL)
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#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
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/* ************************************************************************** */
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/* GPIO */
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#define MXC_CFG_GPIO_INSTANCES (4)
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#define MXC_CFG_GPIO_PINS_PORT (32)
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#define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL)
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#define MXC_GPIO0 ((mxc_gpio_regs_t *)MXC_BASE_GPIO0)
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#define MXC_BASE_GPIO1 ((uint32_t)0x40009000UL)
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#define MXC_GPIO1 ((mxc_gpio_regs_t *)MXC_BASE_GPIO1)
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#define MXC_BASE_GPIO2 ((uint32_t)0x4000A000UL)
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#define MXC_GPIO2 ((mxc_gpio_regs_t *)MXC_BASE_GPIO2)
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#define MXC_BASE_GPIO3 ((uint32_t)0x4000B000UL)
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#define MXC_GPIO3 ((mxc_gpio_regs_t *)MXC_BASE_GPIO3)
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#define MXC_GPIO_GET_IDX(p) \
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((p) == MXC_GPIO0 ? 0 : (p) == MXC_GPIO1 ? 1 : (p) == MXC_GPIO2 ? 2 : (p) == MXC_GPIO3 ? 3 : -1)
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#define MXC_GPIO_GET_GPIO(i) \
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((i) == 0 ? MXC_GPIO0 : (i) == 1 ? MXC_GPIO1 : (i) == 2 ? MXC_GPIO2 : (i) == 3 ? MXC_GPIO3 : 0)
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#define MXC_GPIO_GET_IRQ(i) \
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((i) == 0 ? GPIO0_IRQn : \
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(i) == 1 ? GPIO1_IRQn : \
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(i) == 2 ? GPIO2_IRQn : \
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(i) == 3 ? GPIO3_IRQn : \
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0)
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/* ************************************************************************** */
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/* Timer */
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#define SEC(s) (((uint32_t)s) * 1000000UL)
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#define MSEC(ms) (ms * 1000UL)
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#define USEC(us) (us)
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#define MXC_CFG_TMR_INSTANCES (6)
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#define MXC_BASE_TMR0 ((uint32_t)0x40010000UL)
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#define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0)
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#define MXC_BASE_TMR1 ((uint32_t)0x40011000UL)
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#define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1)
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#define MXC_BASE_TMR2 ((uint32_t)0x40012000UL)
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#define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2)
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#define MXC_BASE_TMR3 ((uint32_t)0x40013000UL)
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#define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3)
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#define MXC_BASE_TMR4 ((uint32_t)0x40014000UL)
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#define MXC_TMR4 ((mxc_tmr_regs_t *)MXC_BASE_TMR4)
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#define MXC_BASE_TMR5 ((uint32_t)0x40015000UL)
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#define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5)
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#define MXC_TMR_GET_IRQ(i) \
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(IRQn_Type)((i) == 0 ? TMR0_IRQn : \
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(i) == 1 ? TMR1_IRQn : \
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(i) == 2 ? TMR2_IRQn : \
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(i) == 3 ? TMR3_IRQn : \
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(i) == 4 ? TMR4_IRQn : \
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(i) == 5 ? TMR5_IRQn : \
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0)
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#define MXC_TMR_GET_BASE(i) \
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((i) == 0 ? MXC_BASE_TMR0 : \
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(i) == 1 ? MXC_BASE_TMR1 : \
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(i) == 2 ? MXC_BASE_TMR2 : \
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(i) == 3 ? MXC_BASE_TMR3 : \
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(i) == 4 ? MXC_BASE_TMR4 : \
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(i) == 5 ? MXC_BASE_TMR5 : \
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0)
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#define MXC_TMR_GET_TMR(i) \
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((i) == 0 ? MXC_TMR0 : \
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(i) == 1 ? MXC_TMR1 : \
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(i) == 2 ? MXC_TMR2 : \
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(i) == 3 ? MXC_TMR3 : \
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(i) == 4 ? MXC_TMR4 : \
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(i) == 5 ? MXC_TMR5 : \
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0)
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#define MXC_TMR_GET_IDX(p) \
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((p) == MXC_TMR0 ? 0 : \
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(p) == MXC_TMR1 ? 1 : \
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(p) == MXC_TMR2 ? 2 : \
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(p) == MXC_TMR3 ? 3 : \
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(p) == MXC_TMR4 ? 4 : \
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(p) == MXC_TMR5 ? 5 : \
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-1)
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/* ************************************************************************** */
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/* SPIMSS */
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#define MXC_SPIMSS_INSTANCES (1)
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#define MXC_SPIMSS_FIFO_DEPTH (8)
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#define MXC_BASE_SPIMSS ((uint32_t)0x40018000UL)
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#define MXC_SPIMSS ((mxc_spimss_regs_t *)MXC_BASE_SPIMSS)
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#define MXC_SPIMSS_GET_IDX(p) ((p) == MXC_SPIMSS ? 0 : -1)
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#define MXC_SPIMSS_GET_SPI(i) ((i) == 0 ? MXC_SPIMSS : 0)
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/* ************************************************************************** */
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/* I2C */
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#define MXC_I2C_INSTANCES (2)
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#define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL)
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#define MXC_I2C0 ((mxc_i2c_regs_t *)MXC_BASE_I2C0)
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#define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL)
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#define MXC_I2C1 ((mxc_i2c_regs_t *)MXC_BASE_I2C1)
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#define MXC_I2C_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2C0_IRQn : (i) == 1 ? I2C1_IRQn : 0)
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#define MXC_I2C_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2C0 : (i) == 1 ? MXC_BASE_I2C1 : 0)
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#define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : (i) == 1 ? MXC_I2C1 : 0)
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#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : (p) == MXC_I2C1 ? 1 : -1)
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#define MXC_I2C_FIFO_DEPTH (8)
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/* ************************************************************************** */
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/* SPI Execute in Place */
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#define MXC_BASE_SPIXF ((uint32_t)0x40026000UL)
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#define MXC_SPIXF ((mxc_spixf_regs_t *)MXC_BASE_SPIXF)
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/* ************************************************************************** */
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/* SPI Execute in Place Master Controller */
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#define MXC_CFG_SPIXFC_FIFO_DEPTH (16)
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#define MXC_BASE_SPIXFC ((uint32_t)0x40027000UL)
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#define MXC_SPIXFC ((mxc_spixfc_regs_t *)MXC_BASE_SPIXFC)
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#define MXC_BASE_SPIXFC_FIFO ((uint32_t)0x400BC000UL)
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#define MXC_SPIXFC_FIFO ((mxc_spixfc_fifo_regs_t *)MXC_BASE_SPIXFC_FIFO)
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/* ************************************************************************** */
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/* DMA */
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#define MXC_DMA_CHANNELS (16)
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#define MXC_DMA_INSTANCES (1)
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#define MXC_BASE_DMA ((uint32_t)0x40028000UL)
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#define MXC_DMA ((mxc_dma_regs_t *)MXC_BASE_DMA)
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#define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA ? 0 : -1)
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#define MXC_DMA_CH_GET_IRQ(i) \
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((IRQn_Type)(((i) == 0) ? DMA0_IRQn : \
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((i) == 1) ? DMA1_IRQn : \
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((i) == 2) ? DMA2_IRQn : \
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((i) == 3) ? DMA3_IRQn : \
400
((i) == 4) ? DMA4_IRQn : \
401
((i) == 5) ? DMA5_IRQn : \
402
((i) == 6) ? DMA6_IRQn : \
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((i) == 7) ? DMA7_IRQn : \
404
((i) == 8) ? DMA8_IRQn : \
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((i) == 9) ? DMA9_IRQn : \
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((i) == 10) ? DMA10_IRQn : \
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((i) == 11) ? DMA11_IRQn : \
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((i) == 12) ? DMA12_IRQn : \
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((i) == 13) ? DMA13_IRQn : \
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((i) == 14) ? DMA14_IRQn : \
411
((i) == 15) ? DMA15_IRQn : \
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0))
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/* ************************************************************************** */
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/* FLC */
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#define MXC_FLC_INSTANCES (1)
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#define MXC_BASE_FLC ((uint32_t)0x40029000UL)
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#define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC)
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#define MXC_FLC0 MXC_FLC
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#define MXC_FLC_GET_IRQ(i) (IRQn_Type)((i) == 0 ? FLC_IRQn : 0)
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#define MXC_FLC_GET_BASE(i) ((i) == 0 ? MXC_BASE_FLC : 0)
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#define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC : 0)
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#define MXC_FLC_GET_IDX(p) ((p) == MXC_FLC ? 0 : -1)
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/* ************************************************************************** */
430
/* Instruction Cache */
431
#define MXC_BASE_ICC0 ((uint32_t)0x4002A000UL)
432
#define MXC_ICC0 ((mxc_icc_regs_t *)MXC_BASE_ICC0)
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#define MXC_ICC MXC_ICC0
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436
/* ************************************************************************** */
437
/* Instruction Cache XIP */
438
#define MXC_BASE_ICC1 ((uint32_t)0x4002F000UL)
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#define MXC_ICC1 ((mxc_icc_regs_t *)MXC_BASE_ICC1)
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#define MXC_ICX MXC_ICC1
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443
/* ************************************************************************** */
444
/* CLCD */
445
#define MXC_BASE_CLCD ((uint32_t)0x40031000UL)
446
#define MXC_CLCD ((mxc_clcd_regs_t *)MXC_BASE_CLCD)
447
448
/* ************************************************************************** */
449
/* Data Cache */
450
#define MXC_BASE_EMCC ((uint32_t)0x40033000UL)
451
#define MXC_EMCC ((mxc_emcc_regs_t *)MXC_BASE_EMCC)
452
453
/* ************************************************************************** */
454
/* ADC */
455
#define MXC_BASE_ADC ((uint32_t)0x40034000UL)
456
#define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC)
457
#define MXC_ADC_MAX_CLOCK 8000000
// Maximum ADC clock in Hz
458
459
/* ************************************************************************** */
460
/* XXX Actually reserved! */
461
#define MXC_BASE_RESERVED ((uint32_t)0x40035000UL)
462
463
/* ************************************************************************** */
464
/* Smart DMA */
465
#define MXC_BASE_SDMA ((uint32_t)0x40036000UL)
466
#define MXC_SDMA ((mxc_sdma_regs_t *)MXC_BASE_SDMA)
467
468
/* ************************************************************************** */
469
/* HyperBus */
470
#define MXC_BASE_HPB ((uint32_t)0x40039000UL)
471
#define MXC_HPB ((mxc_hpb_regs_t *)MXC_BASE_HPB)
472
473
/* ************************************************************************** */
474
/* SPI XIP Data */
475
#define MXC_BASE_SPIXR ((uint32_t)0x4003A000UL)
476
#define MXC_SPIXR ((mxc_spixr_regs_t *)MXC_BASE_SPIXR)
477
478
/* ************************************************************************** */
479
/* MIPI DSI */
480
#define MXC_BASE_MIPI ((uint32_t)0x4003B000UL)
481
#define MXC_MIPI ((mxc_mipi_regs_t *)MXC_BASE_MIPI)
482
483
/*******************************************************************************/
484
/* Pulse Train Generation */
485
#define MXC_CFG_PT_INSTANCES (16)
486
487
#define MXC_BASE_PTG ((uint32_t)0x4003C000UL)
488
#define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG)
489
#define MXC_BASE_PT0 ((uint32_t)0x4003C020UL)
490
#define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0)
491
#define MXC_BASE_PT1 ((uint32_t)0x4003C040UL)
492
#define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1)
493
#define MXC_BASE_PT2 ((uint32_t)0x4003C060UL)
494
#define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2)
495
#define MXC_BASE_PT3 ((uint32_t)0x4003C080UL)
496
#define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3)
497
#define MXC_BASE_PT4 ((uint32_t)0x4003C0A0UL)
498
#define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4)
499
#define MXC_BASE_PT5 ((uint32_t)0x4003C0C0UL)
500
#define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5)
501
#define MXC_BASE_PT6 ((uint32_t)0x4003C0E0UL)
502
#define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6)
503
#define MXC_BASE_PT7 ((uint32_t)0x4003C100UL)
504
#define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7)
505
#define MXC_BASE_PT8 ((uint32_t)0x4003C120UL)
506
#define MXC_PT8 ((mxc_pt_regs_t *)MXC_BASE_PT8)
507
#define MXC_BASE_PT9 ((uint32_t)0x4003C140UL)
508
#define MXC_PT9 ((mxc_pt_regs_t *)MXC_BASE_PT9)
509
#define MXC_BASE_PT10 ((uint32_t)0x4003C160UL)
510
#define MXC_PT10 ((mxc_pt_regs_t *)MXC_BASE_PT10)
511
#define MXC_BASE_PT11 ((uint32_t)0x4003C180UL)
512
#define MXC_PT11 ((mxc_pt_regs_t *)MXC_BASE_PT11)
513
#define MXC_BASE_PT12 ((uint32_t)0x4003C1A0UL)
514
#define MXC_PT12 ((mxc_pt_regs_t *)MXC_BASE_PT12)
515
#define MXC_BASE_PT13 ((uint32_t)0x4003C1C0UL)
516
#define MXC_PT13 ((mxc_pt_regs_t *)MXC_BASE_PT13)
517
#define MXC_BASE_PT14 ((uint32_t)0x4003C1E0UL)
518
#define MXC_PT14 ((mxc_pt_regs_t *)MXC_BASE_PT14)
519
#define MXC_BASE_PT15 ((uint32_t)0x4003C200UL)
520
#define MXC_PT15 ((mxc_pt_regs_t *)MXC_BASE_PT15)
521
522
#define MXC_PT_GET_BASE(i) \
523
((i) == 0 ? MXC_BASE_PT0 : \
524
(i) == 1 ? MXC_BASE_PT1 : \
525
(i) == 2 ? MXC_BASE_PT2 : \
526
(i) == 3 ? MXC_BASE_PT3 : \
527
(i) == 4 ? MXC_BASE_PT4 : \
528
(i) == 5 ? MXC_BASE_PT5 : \
529
(i) == 6 ? MXC_BASE_PT6 : \
530
(i) == 7 ? MXC_BASE_PT7 : \
531
(i) == 8 ? MXC_BASE_PT8 : \
532
(i) == 9 ? MXC_BASE_PT9 : \
533
(i) == 10 ? MXC_BASE_PT10 : \
534
(i) == 11 ? MXC_BASE_PT11 : \
535
(i) == 12 ? MXC_BASE_PT12 : \
536
(i) == 13 ? MXC_BASE_PT13 : \
537
(i) == 14 ? MXC_BASE_PT14 : \
538
(i) == 15 ? MXC_BASE_PT15 : \
539
0)
540
541
#define MXC_PT_GET_PT(i) \
542
((i) == 0 ? MXC_PT0 : \
543
(i) == 1 ? MXC_PT1 : \
544
(i) == 2 ? MXC_PT2 : \
545
(i) == 3 ? MXC_PT3 : \
546
(i) == 4 ? MXC_PT4 : \
547
(i) == 5 ? MXC_PT5 : \
548
(i) == 6 ? MXC_PT6 : \
549
(i) == 7 ? MXC_PT7 : \
550
(i) == 8 ? MXC_PT8 : \
551
(i) == 9 ? MXC_PT9 : \
552
(i) == 10 ? MXC_PT10 : \
553
(i) == 11 ? MXC_PT11 : \
554
(i) == 12 ? MXC_PT12 : \
555
(i) == 13 ? MXC_PT13 : \
556
(i) == 14 ? MXC_PT14 : \
557
(i) == 15 ? MXC_PT15 : \
558
0)
559
560
#define MXC_PT_GET_IDX(p) \
561
((p) == MXC_PT0 ? 0 : \
562
(p) == MXC_PT1 ? 1 : \
563
(p) == MXC_PT2 ? 2 : \
564
(p) == MXC_PT3 ? 3 : \
565
(p) == MXC_PT4 ? 4 : \
566
(p) == MXC_PT5 ? 5 : \
567
(p) == MXC_PT6 ? 6 : \
568
(p) == MXC_PT7 ? 7 : \
569
(p) == MXC_PT8 ? 8 : \
570
(p) == MXC_PT9 ? 9 : \
571
(p) == MXC_PT10 ? 10 : \
572
(p) == MXC_PT11 ? 11 : \
573
(p) == MXC_PT12 ? 12 : \
574
(p) == MXC_PT13 ? 13 : \
575
(p) == MXC_PT14 ? 14 : \
576
(p) == MXC_PT15 ? 15 : \
577
-1)
578
579
/* ************************************************************************** */
580
/* One Wire Master */
581
#define MXC_BASE_OWM ((uint32_t)0x4003D000UL)
582
#define MXC_OWM ((mxc_owm_regs_t *)MXC_BASE_OWM)
583
584
/* ************************************************************************** */
585
/* Semaphore */
586
#define MXC_CFG_SEMA_INSTANCES (8)
587
588
#define MXC_BASE_SEMA ((uint32_t)0x4003E000UL)
589
#define MXC_SEMA ((mxc_sema_regs_t *)MXC_BASE_SEMA)
590
591
/* ************************************************************************** */
592
/* UART / Serial Port Interface */
593
#define MXC_UART_INSTANCES (3)
594
#define MXC_UART_FIFO_DEPTH (32)
595
596
#define MXC_BASE_UART0 ((uint32_t)0x40042000UL)
597
#define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0)
598
#define MXC_BASE_UART1 ((uint32_t)0x40043000UL)
599
#define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1)
600
#define MXC_BASE_UART2 ((uint32_t)0x40044000UL)
601
#define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2)
602
603
#define MXC_UART_GET_IRQ(i) \
604
(IRQn_Type)((i) == 0 ? UART0_IRQn : (i) == 1 ? UART1_IRQn : (i) == 2 ? UART2_IRQn : 0)
605
606
#define MXC_UART_GET_BASE(i) \
607
((i) == 0 ? MXC_BASE_UART0 : (i) == 1 ? MXC_BASE_UART1 : (i) == 2 ? MXC_BASE_UART2 : 0)
608
609
#define MXC_UART_GET_UART(i) \
610
((i) == 0 ? MXC_UART0 : (i) == 1 ? MXC_UART1 : (i) == 2 ? MXC_UART2 : 0)
611
612
#define MXC_UART_GET_IDX(p) \
613
((p) == MXC_UART0 ? 0 : (p) == MXC_UART1 ? 1 : (p) == MXC_UART2 ? 2 : -1)
614
615
/* ************************************************************************** */
616
/* SPI */
617
#define MXC_SPI_INSTANCES (4)
618
#define MXC_SPI_SS_INSTANCES (4)
619
#define MXC_SPI_FIFO_DEPTH (32)
620
621
#define MXC_BASE_SPI0 ((uint32_t)0x40046000UL)
622
#define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0)
623
#define MXC_BASE_SPI1 ((uint32_t)0x40047000UL)
624
#define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1)
625
#define MXC_BASE_SPI2 ((uint32_t)0x40048000UL)
626
#define MXC_SPI2 ((mxc_spi_regs_t *)MXC_BASE_SPI2)
627
#define MXC_BASE_SPI3 ((uint32_t)0x400BE000UL)
628
#define MXC_SPI3 ((mxc_spi_regs_t *)MXC_BASE_SPI3)
629
630
#define MXC_SPI_GET_IDX(p) \
631
((p) == MXC_SPI0 ? 0 : (p) == MXC_SPI1 ? 1 : (p) == MXC_SPI2 ? 2 : (p) == MXC_SPI3 ? 3 : -1)
632
633
#define MXC_SPI_GET_BASE(i) \
634
((i) == 0 ? MXC_BASE_SPI0 : \
635
(i) == 1 ? MXC_BASE_SPI1 : \
636
(i) == 2 ? MXC_BASE_SPI2 : \
637
(i) == 3 ? MXC_BASE_SPI3 : \
638
0)
639
640
#define MXC_SPI_GET_SPI(i) \
641
((i) == 0 ? MXC_SPI0 : (i) == 1 ? MXC_SPI1 : (i) == 2 ? MXC_SPI2 : (i) == 3 ? MXC_SPI3 : 0)
642
643
#define MXC_SPI_GET_IRQ(i) \
644
(IRQn_Type)((i) == 0 ? SPI0_IRQn : \
645
(i) == 1 ? SPI1_IRQn : \
646
(i) == 2 ? SPI2_IRQn : \
647
(i) == 3 ? SPI3_IRQn : \
648
0)
649
650
/* ************************************************************************** */
651
/* USB */
652
#define MXC_BASE_USBHS ((uint32_t)0x400B1000UL)
653
#define MXC_USBHS ((mxc_usbhs_regs_t *)MXC_BASE_USBHS)
654
#define MXC_USBHS_NUM_EP 12
/* HW must have at least EP 0 CONTROL + 11 IN/OUT */
655
#define MXC_USBHS_NUM_DMA 8
/* HW must have at least this many DMA channels */
656
#define MXC_USBHS_MAX_PACKET 512
657
658
/* ************************************************************************** */
659
/* TRNG */
660
#define MXC_BASE_TRNG ((uint32_t)0x400B5000UL)
661
#define MXC_TRNG ((mxc_trng_regs_t *)MXC_BASE_TRNG)
662
663
/* ************************************************************************** */
664
/* SDHC */
665
#define MXC_BASE_SDHC ((uint32_t)0x400B6000UL)
666
#define MXC_SDHC ((mxc_sdhc_regs_t *)MXC_BASE_SDHC)
667
668
/* ************************************************************************** */
669
/* Bit Shifting */
670
671
#define MXC_F_BIT_0 (1 << 0)
672
#define MXC_F_BIT_1 (1 << 1)
673
#define MXC_F_BIT_2 (1 << 2)
674
#define MXC_F_BIT_3 (1 << 3)
675
#define MXC_F_BIT_4 (1 << 4)
676
#define MXC_F_BIT_5 (1 << 5)
677
#define MXC_F_BIT_6 (1 << 6)
678
#define MXC_F_BIT_7 (1 << 7)
679
#define MXC_F_BIT_8 (1 << 8)
680
#define MXC_F_BIT_9 (1 << 9)
681
#define MXC_F_BIT_10 (1 << 10)
682
#define MXC_F_BIT_11 (1 << 11)
683
#define MXC_F_BIT_12 (1 << 12)
684
#define MXC_F_BIT_13 (1 << 13)
685
#define MXC_F_BIT_14 (1 << 14)
686
#define MXC_F_BIT_15 (1 << 15)
687
#define MXC_F_BIT_16 (1 << 16)
688
#define MXC_F_BIT_17 (1 << 17)
689
#define MXC_F_BIT_18 (1 << 18)
690
#define MXC_F_BIT_19 (1 << 19)
691
#define MXC_F_BIT_20 (1 << 20)
692
#define MXC_F_BIT_21 (1 << 21)
693
#define MXC_F_BIT_22 (1 << 22)
694
#define MXC_F_BIT_23 (1 << 23)
695
#define MXC_F_BIT_24 (1 << 24)
696
#define MXC_F_BIT_25 (1 << 25)
697
#define MXC_F_BIT_26 (1 << 26)
698
#define MXC_F_BIT_27 (1 << 27)
699
#define MXC_F_BIT_28 (1 << 28)
700
#define MXC_F_BIT_29 (1 << 29)
701
#define MXC_F_BIT_30 (1 << 30)
702
#define MXC_F_BIT_31 (1 << 31)
703
704
/* ************************************************************************** */
705
/* Bit Banding */
706
707
#define BITBAND(reg, bit) \
708
((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg)&0x0fffffff) << 5) + \
709
((bit) << 2))
710
711
#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
712
#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
713
#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
714
715
#define MXC_SETFIELD(reg, mask, setting) ((reg) = ((reg) & ~(mask)) | ((setting) & (mask)))
716
717
/* ************************************************************************** */
718
/* SCB CPACR */
719
720
/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
721
#define SCB_CPACR_CP10_Pos 20
722
#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos)
723
#define SCB_CPACR_CP11_Pos 22
724
#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos)
726
#endif
// LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_MAX32650_H_
CMSIS
Device
Maxim
MAX32650
Include
max32650.h
Generated on Fri Oct 25 2024 14:39:09 for MAX32650 Peripheral Driver API by
1.9.4
1.9.4