tmr_regs.h

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/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_TMR_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_TMR_REGS_H_
 
/* **** Includes **** */
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined (__ICCARM__)
  #pragma system_include
#endif
 
#if defined (__CC_ARM)
  #pragma anon_unions
#endif
/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif
#ifndef __R
#define __R  volatile const
#endif
 
/* **** Definitions **** */
 
typedef struct {
    __IO uint32_t cnt;                  
    __IO uint32_t cmp;                  
    __IO uint32_t pwm;                  
    __IO uint32_t intr;                 
    __IO uint32_t cn;                   
    __IO uint32_t nolcmp;               
} mxc_tmr_regs_t;
 
/* Register offsets for module TMR */
#define MXC_R_TMR_CNT                      ((uint32_t)0x00000000UL) 
#define MXC_R_TMR_CMP                      ((uint32_t)0x00000004UL) 
#define MXC_R_TMR_PWM                      ((uint32_t)0x00000008UL) 
#define MXC_R_TMR_INTR                     ((uint32_t)0x0000000CUL) 
#define MXC_R_TMR_CN                       ((uint32_t)0x00000010UL) 
#define MXC_R_TMR_NOLCMP                   ((uint32_t)0x00000014UL) 
#define MXC_F_TMR_CNT_COUNT_POS                        0 
#define MXC_F_TMR_CNT_COUNT                            ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CNT_COUNT_POS)) 
#define MXC_F_TMR_CMP_COMPARE_POS                      0 
#define MXC_F_TMR_CMP_COMPARE                          ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CMP_COMPARE_POS)) 
#define MXC_F_TMR_PWM_PWM_POS                          0 
#define MXC_F_TMR_PWM_PWM                              ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_PWM_PWM_POS)) 
#define MXC_F_TMR_INTR_IRQ_POS                         0 
#define MXC_F_TMR_INTR_IRQ                             ((uint32_t)(0x1UL << MXC_F_TMR_INTR_IRQ_POS)) 
#define MXC_F_TMR_CN_TMODE_POS                         0 
#define MXC_F_TMR_CN_TMODE                             ((uint32_t)(0x7UL << MXC_F_TMR_CN_TMODE_POS)) 
#define MXC_V_TMR_CN_TMODE_ONESHOT                     ((uint32_t)0x0UL) 
#define MXC_S_TMR_CN_TMODE_ONESHOT                     (MXC_V_TMR_CN_TMODE_ONESHOT << MXC_F_TMR_CN_TMODE_POS) 
#define MXC_V_TMR_CN_TMODE_CONTINUOUS                  ((uint32_t)0x1UL) 
#define MXC_S_TMR_CN_TMODE_CONTINUOUS                  (MXC_V_TMR_CN_TMODE_CONTINUOUS << MXC_F_TMR_CN_TMODE_POS) 
#define MXC_V_TMR_CN_TMODE_COUNTER                     ((uint32_t)0x2UL) 
#define MXC_S_TMR_CN_TMODE_COUNTER                     (MXC_V_TMR_CN_TMODE_COUNTER << MXC_F_TMR_CN_TMODE_POS) 
#define MXC_V_TMR_CN_TMODE_PWM                         ((uint32_t)0x3UL) 
#define MXC_S_TMR_CN_TMODE_PWM                         (MXC_V_TMR_CN_TMODE_PWM << MXC_F_TMR_CN_TMODE_POS) 
#define MXC_V_TMR_CN_TMODE_CAPTURE                     ((uint32_t)0x4UL) 
#define MXC_S_TMR_CN_TMODE_CAPTURE                     (MXC_V_TMR_CN_TMODE_CAPTURE << MXC_F_TMR_CN_TMODE_POS) 
#define MXC_V_TMR_CN_TMODE_COMPARE                     ((uint32_t)0x5UL) 
#define MXC_S_TMR_CN_TMODE_COMPARE                     (MXC_V_TMR_CN_TMODE_COMPARE << MXC_F_TMR_CN_TMODE_POS) 
#define MXC_V_TMR_CN_TMODE_GATED                       ((uint32_t)0x6UL) 
#define MXC_S_TMR_CN_TMODE_GATED                       (MXC_V_TMR_CN_TMODE_GATED << MXC_F_TMR_CN_TMODE_POS) 
#define MXC_V_TMR_CN_TMODE_CAPTURECOMPARE              ((uint32_t)0x7UL) 
#define MXC_S_TMR_CN_TMODE_CAPTURECOMPARE              (MXC_V_TMR_CN_TMODE_CAPTURECOMPARE << MXC_F_TMR_CN_TMODE_POS) 
#define MXC_F_TMR_CN_PRES_POS                          3 
#define MXC_F_TMR_CN_PRES                              ((uint32_t)(0x7UL << MXC_F_TMR_CN_PRES_POS)) 
#define MXC_V_TMR_CN_PRES_DIV1                         ((uint32_t)0x0UL) 
#define MXC_S_TMR_CN_PRES_DIV1                         (MXC_V_TMR_CN_PRES_DIV1 << MXC_F_TMR_CN_PRES_POS) 
#define MXC_V_TMR_CN_PRES_DIV2                         ((uint32_t)0x1UL) 
#define MXC_S_TMR_CN_PRES_DIV2                         (MXC_V_TMR_CN_PRES_DIV2 << MXC_F_TMR_CN_PRES_POS) 
#define MXC_V_TMR_CN_PRES_DIV4                         ((uint32_t)0x2UL) 
#define MXC_S_TMR_CN_PRES_DIV4                         (MXC_V_TMR_CN_PRES_DIV4 << MXC_F_TMR_CN_PRES_POS) 
#define MXC_V_TMR_CN_PRES_DIV8                         ((uint32_t)0x3UL) 
#define MXC_S_TMR_CN_PRES_DIV8                         (MXC_V_TMR_CN_PRES_DIV8 << MXC_F_TMR_CN_PRES_POS) 
#define MXC_V_TMR_CN_PRES_DIV16                        ((uint32_t)0x4UL) 
#define MXC_S_TMR_CN_PRES_DIV16                        (MXC_V_TMR_CN_PRES_DIV16 << MXC_F_TMR_CN_PRES_POS) 
#define MXC_V_TMR_CN_PRES_DIV32                        ((uint32_t)0x5UL) 
#define MXC_S_TMR_CN_PRES_DIV32                        (MXC_V_TMR_CN_PRES_DIV32 << MXC_F_TMR_CN_PRES_POS) 
#define MXC_V_TMR_CN_PRES_DIV64                        ((uint32_t)0x6UL) 
#define MXC_S_TMR_CN_PRES_DIV64                        (MXC_V_TMR_CN_PRES_DIV64 << MXC_F_TMR_CN_PRES_POS) 
#define MXC_V_TMR_CN_PRES_DIV128                       ((uint32_t)0x7UL) 
#define MXC_S_TMR_CN_PRES_DIV128                       (MXC_V_TMR_CN_PRES_DIV128 << MXC_F_TMR_CN_PRES_POS) 
#define MXC_V_TMR_CN_PRES_DIV256                       ((uint32_t)0x0UL) 
#define MXC_S_TMR_CN_PRES_DIV256                       (MXC_V_TMR_CN_PRES_DIV256 << MXC_F_TMR_CN_PRES_POS) 
#define MXC_V_TMR_CN_PRES_DIV512                       ((uint32_t)0x2UL) 
#define MXC_S_TMR_CN_PRES_DIV512                       (MXC_V_TMR_CN_PRES_DIV512 << MXC_F_TMR_CN_PRES_POS) 
#define MXC_V_TMR_CN_PRES_DIV1024                      ((uint32_t)0x3UL) 
#define MXC_S_TMR_CN_PRES_DIV1024                      (MXC_V_TMR_CN_PRES_DIV1024 << MXC_F_TMR_CN_PRES_POS) 
#define MXC_V_TMR_CN_PRES_DIV2048                      ((uint32_t)0x4UL) 
#define MXC_S_TMR_CN_PRES_DIV2048                      (MXC_V_TMR_CN_PRES_DIV2048 << MXC_F_TMR_CN_PRES_POS) 
#define MXC_V_TMR_CN_PRES_DIV4096                      ((uint32_t)0x5UL) 
#define MXC_S_TMR_CN_PRES_DIV4096                      (MXC_V_TMR_CN_PRES_DIV4096 << MXC_F_TMR_CN_PRES_POS) 
#define MXC_F_TMR_CN_TPOL_POS                          6 
#define MXC_F_TMR_CN_TPOL                              ((uint32_t)(0x1UL << MXC_F_TMR_CN_TPOL_POS)) 
#define MXC_V_TMR_CN_TPOL_ACTIVEHI                     ((uint32_t)0x0UL) 
#define MXC_S_TMR_CN_TPOL_ACTIVEHI                     (MXC_V_TMR_CN_TPOL_ACTIVEHI << MXC_F_TMR_CN_TPOL_POS) 
#define MXC_V_TMR_CN_TPOL_ACTIVELO                     ((uint32_t)0x1UL) 
#define MXC_S_TMR_CN_TPOL_ACTIVELO                     (MXC_V_TMR_CN_TPOL_ACTIVELO << MXC_F_TMR_CN_TPOL_POS) 
#define MXC_F_TMR_CN_TEN_POS                           7 
#define MXC_F_TMR_CN_TEN                               ((uint32_t)(0x1UL << MXC_F_TMR_CN_TEN_POS)) 
#define MXC_V_TMR_CN_TEN_DIS                           ((uint32_t)0x0UL) 
#define MXC_S_TMR_CN_TEN_DIS                           (MXC_V_TMR_CN_TEN_DIS << MXC_F_TMR_CN_TEN_POS) 
#define MXC_V_TMR_CN_TEN_EN                            ((uint32_t)0x1UL) 
#define MXC_S_TMR_CN_TEN_EN                            (MXC_V_TMR_CN_TEN_EN << MXC_F_TMR_CN_TEN_POS) 
#define MXC_F_TMR_CN_PRES3_POS                         8 
#define MXC_F_TMR_CN_PRES3                             ((uint32_t)(0x1UL << MXC_F_TMR_CN_PRES3_POS)) 
#define MXC_V_TMR_CN_PRES3_DIV1                        ((uint32_t)0x0UL) 
#define MXC_S_TMR_CN_PRES3_DIV1                        (MXC_V_TMR_CN_PRES3_DIV1 << MXC_F_TMR_CN_PRES3_POS) 
#define MXC_V_TMR_CN_PRES3_DIV2                        ((uint32_t)0x0UL) 
#define MXC_S_TMR_CN_PRES3_DIV2                        (MXC_V_TMR_CN_PRES3_DIV2 << MXC_F_TMR_CN_PRES3_POS) 
#define MXC_V_TMR_CN_PRES3_DIV4                        ((uint32_t)0x0UL) 
#define MXC_S_TMR_CN_PRES3_DIV4                        (MXC_V_TMR_CN_PRES3_DIV4 << MXC_F_TMR_CN_PRES3_POS) 
#define MXC_V_TMR_CN_PRES3_DIV8                        ((uint32_t)0x0UL) 
#define MXC_S_TMR_CN_PRES3_DIV8                        (MXC_V_TMR_CN_PRES3_DIV8 << MXC_F_TMR_CN_PRES3_POS) 
#define MXC_V_TMR_CN_PRES3_DIV16                       ((uint32_t)0x0UL) 
#define MXC_S_TMR_CN_PRES3_DIV16                       (MXC_V_TMR_CN_PRES3_DIV16 << MXC_F_TMR_CN_PRES3_POS) 
#define MXC_V_TMR_CN_PRES3_DIV32                       ((uint32_t)0x0UL) 
#define MXC_S_TMR_CN_PRES3_DIV32                       (MXC_V_TMR_CN_PRES3_DIV32 << MXC_F_TMR_CN_PRES3_POS) 
#define MXC_V_TMR_CN_PRES3_DIV64                       ((uint32_t)0x0UL) 
#define MXC_S_TMR_CN_PRES3_DIV64                       (MXC_V_TMR_CN_PRES3_DIV64 << MXC_F_TMR_CN_PRES3_POS) 
#define MXC_V_TMR_CN_PRES3_DIV128                      ((uint32_t)0x0UL) 
#define MXC_S_TMR_CN_PRES3_DIV128                      (MXC_V_TMR_CN_PRES3_DIV128 << MXC_F_TMR_CN_PRES3_POS) 
#define MXC_V_TMR_CN_PRES3_DIV256                      ((uint32_t)0x1UL) 
#define MXC_S_TMR_CN_PRES3_DIV256                      (MXC_V_TMR_CN_PRES3_DIV256 << MXC_F_TMR_CN_PRES3_POS) 
#define MXC_V_TMR_CN_PRES3_DIV512                      ((uint32_t)0x1UL) 
#define MXC_S_TMR_CN_PRES3_DIV512                      (MXC_V_TMR_CN_PRES3_DIV512 << MXC_F_TMR_CN_PRES3_POS) 
#define MXC_V_TMR_CN_PRES3_DIV1024                     ((uint32_t)0x1UL) 
#define MXC_S_TMR_CN_PRES3_DIV1024                     (MXC_V_TMR_CN_PRES3_DIV1024 << MXC_F_TMR_CN_PRES3_POS) 
#define MXC_V_TMR_CN_PRES3_DIV2048                     ((uint32_t)0x1UL) 
#define MXC_S_TMR_CN_PRES3_DIV2048                     (MXC_V_TMR_CN_PRES3_DIV2048 << MXC_F_TMR_CN_PRES3_POS) 
#define MXC_V_TMR_CN_PRES3_DIV4096                     ((uint32_t)0x1UL) 
#define MXC_S_TMR_CN_PRES3_DIV4096                     (MXC_V_TMR_CN_PRES3_DIV4096 << MXC_F_TMR_CN_PRES3_POS) 
#define MXC_F_TMR_CN_PWMSYNC_POS                       9 
#define MXC_F_TMR_CN_PWMSYNC                           ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMSYNC_POS)) 
#define MXC_V_TMR_CN_PWMSYNC_DIS                       ((uint32_t)0x0UL) 
#define MXC_S_TMR_CN_PWMSYNC_DIS                       (MXC_V_TMR_CN_PWMSYNC_DIS << MXC_F_TMR_CN_PWMSYNC_POS) 
#define MXC_V_TMR_CN_PWMSYNC_EN                        ((uint32_t)0x1UL) 
#define MXC_S_TMR_CN_PWMSYNC_EN                        (MXC_V_TMR_CN_PWMSYNC_EN << MXC_F_TMR_CN_PWMSYNC_POS) 
#define MXC_F_TMR_CN_NOLHPOL_POS                       10 
#define MXC_F_TMR_CN_NOLHPOL                           ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLHPOL_POS)) 
#define MXC_V_TMR_CN_NOLHPOL_NORMAL                    ((uint32_t)0x0UL) 
#define MXC_S_TMR_CN_NOLHPOL_NORMAL                    (MXC_V_TMR_CN_NOLHPOL_NORMAL << MXC_F_TMR_CN_NOLHPOL_POS) 
#define MXC_V_TMR_CN_NOLHPOL_INVERT                    ((uint32_t)0x1UL) 
#define MXC_S_TMR_CN_NOLHPOL_INVERT                    (MXC_V_TMR_CN_NOLHPOL_INVERT << MXC_F_TMR_CN_NOLHPOL_POS) 
#define MXC_F_TMR_CN_NOLLPOL_POS                       11 
#define MXC_F_TMR_CN_NOLLPOL                           ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLLPOL_POS)) 
#define MXC_V_TMR_CN_NOLLPOL_NORMAL                    ((uint32_t)0x0UL) 
#define MXC_S_TMR_CN_NOLLPOL_NORMAL                    (MXC_V_TMR_CN_NOLLPOL_NORMAL << MXC_F_TMR_CN_NOLLPOL_POS) 
#define MXC_V_TMR_CN_NOLLPOL_INVERT                    ((uint32_t)0x1UL) 
#define MXC_S_TMR_CN_NOLLPOL_INVERT                    (MXC_V_TMR_CN_NOLLPOL_INVERT << MXC_F_TMR_CN_NOLLPOL_POS) 
#define MXC_F_TMR_CN_PWMCKBD_POS                       12 
#define MXC_F_TMR_CN_PWMCKBD                           ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMCKBD_POS)) 
#define MXC_V_TMR_CN_PWMCKBD_DIS                       ((uint32_t)0x1UL) 
#define MXC_S_TMR_CN_PWMCKBD_DIS                       (MXC_V_TMR_CN_PWMCKBD_DIS << MXC_F_TMR_CN_PWMCKBD_POS) 
#define MXC_V_TMR_CN_PWMCKBD_EN                        ((uint32_t)0x0UL) 
#define MXC_S_TMR_CN_PWMCKBD_EN                        (MXC_V_TMR_CN_PWMCKBD_EN << MXC_F_TMR_CN_PWMCKBD_POS) 
#define MXC_F_TMR_NOLCMP_NOLLCMP_POS                   0 
#define MXC_F_TMR_NOLCMP_NOLLCMP                       ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_NOLLCMP_POS)) 
#define MXC_F_TMR_NOLCMP_NOLHCMP_POS                   8 
#define MXC_F_TMR_NOLCMP_NOLHCMP                       ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_NOLHCMP_POS)) 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_TMR_REGS_H_