fcr_regs.h

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/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_FCR_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_FCR_REGS_H_
 
/* **** Includes **** */
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined (__ICCARM__)
  #pragma system_include
#endif
 
#if defined (__CC_ARM)
  #pragma anon_unions
#endif
/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif
#ifndef __R
#define __R  volatile const
#endif
 
/* **** Definitions **** */
 
typedef struct {
    __IO uint32_t fctrl0;               
    __IO uint32_t autocal0;             
    __IO uint32_t autocal1;             
    __IO uint32_t autocal2;             
    __IO uint32_t urvbootaddr;          
    __IO uint32_t urvctrl;              
    __IO uint32_t erfoks;               
    __IO uint32_t erfo_intfl;           
    __IO uint32_t erfo_inten;           
} mxc_fcr_regs_t;
 
/* Register offsets for module FCR */
#define MXC_R_FCR_FCTRL0                   ((uint32_t)0x00000000UL) 
#define MXC_R_FCR_AUTOCAL0                 ((uint32_t)0x00000004UL) 
#define MXC_R_FCR_AUTOCAL1                 ((uint32_t)0x00000008UL) 
#define MXC_R_FCR_AUTOCAL2                 ((uint32_t)0x0000000CUL) 
#define MXC_R_FCR_URVBOOTADDR              ((uint32_t)0x00000010UL) 
#define MXC_R_FCR_URVCTRL                  ((uint32_t)0x00000014UL) 
#define MXC_R_FCR_ERFOKS                   ((uint32_t)0x00000018UL) 
#define MXC_R_FCR_ERFO_INTFL               ((uint32_t)0x0000001CUL) 
#define MXC_R_FCR_ERFO_INTEN               ((uint32_t)0x00000020UL) 
#define MXC_F_FCR_FCTRL0_I2C0DGEN0_POS                 20 
#define MXC_F_FCR_FCTRL0_I2C0DGEN0                     ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN0_POS)) 
#define MXC_F_FCR_FCTRL0_I2C0DGEN1_POS                 21 
#define MXC_F_FCR_FCTRL0_I2C0DGEN1                     ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN1_POS)) 
#define MXC_F_FCR_FCTRL0_I2C1DGEN0_POS                 22 
#define MXC_F_FCR_FCTRL0_I2C1DGEN0                     ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1DGEN0_POS)) 
#define MXC_F_FCR_FCTRL0_I2C1DGEN1_POS                 23 
#define MXC_F_FCR_FCTRL0_I2C1DGEN1                     ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1DGEN1_POS)) 
#define MXC_F_FCR_FCTRL0_I2C2DGEN0_POS                 24 
#define MXC_F_FCR_FCTRL0_I2C2DGEN0                     ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2DGEN0_POS)) 
#define MXC_F_FCR_FCTRL0_I2C2DGEN1_POS                 25 
#define MXC_F_FCR_FCTRL0_I2C2DGEN1                     ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2DGEN1_POS)) 
#define MXC_F_FCR_AUTOCAL0_ACEN_POS                    0 
#define MXC_F_FCR_AUTOCAL0_ACEN                        ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ACEN_POS)) 
#define MXC_F_FCR_AUTOCAL0_ACRUN_POS                   1 
#define MXC_F_FCR_AUTOCAL0_ACRUN                       ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ACRUN_POS)) 
#define MXC_F_FCR_AUTOCAL0_LDTRM_POS                   2 
#define MXC_F_FCR_AUTOCAL0_LDTRM                       ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_LDTRM_POS)) 
#define MXC_F_FCR_AUTOCAL0_GAININV_POS                 3 
#define MXC_F_FCR_AUTOCAL0_GAININV                     ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_GAININV_POS)) 
#define MXC_F_FCR_AUTOCAL0_ATOMIC_POS                  4 
#define MXC_F_FCR_AUTOCAL0_ATOMIC                      ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ATOMIC_POS)) 
#define MXC_F_FCR_AUTOCAL0_MU_POS                      8 
#define MXC_F_FCR_AUTOCAL0_MU                          ((uint32_t)(0xFFFUL << MXC_F_FCR_AUTOCAL0_MU_POS)) 
#define MXC_F_FCR_AUTOCAL0_HIRC96MACTMROUT_POS         23 
#define MXC_F_FCR_AUTOCAL0_HIRC96MACTMROUT             ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL0_HIRC96MACTMROUT_POS)) 
#define MXC_F_FCR_AUTOCAL1_INITTRM_POS                 0 
#define MXC_F_FCR_AUTOCAL1_INITTRM                     ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL1_INITTRM_POS)) 
#define MXC_F_FCR_AUTOCAL2_DONECNT_POS                 0 
#define MXC_F_FCR_AUTOCAL2_DONECNT                     ((uint32_t)(0xFFUL << MXC_F_FCR_AUTOCAL2_DONECNT_POS)) 
#define MXC_F_FCR_AUTOCAL2_ACDIV_POS                   8 
#define MXC_F_FCR_AUTOCAL2_ACDIV                       ((uint32_t)(0x1FFFUL << MXC_F_FCR_AUTOCAL2_ACDIV_POS)) 
#define MXC_F_FCR_URVCTRL_MEMSEL_POS                   0 
#define MXC_F_FCR_URVCTRL_MEMSEL                       ((uint32_t)(0x1UL << MXC_F_FCR_URVCTRL_MEMSEL_POS)) 
#define MXC_F_FCR_URVCTRL_IFLUSHEN_POS                 1 
#define MXC_F_FCR_URVCTRL_IFLUSHEN                     ((uint32_t)(0x1UL << MXC_F_FCR_URVCTRL_IFLUSHEN_POS)) 
#define MXC_F_FCR_ERFOKS_KSERFO_CNT_POS                0 
#define MXC_F_FCR_ERFOKS_KSERFO_CNT                    ((uint32_t)(0x7FUL << MXC_F_FCR_ERFOKS_KSERFO_CNT_POS)) 
#define MXC_F_FCR_ERFOKS_KSERFO_EN_POS                 7 
#define MXC_F_FCR_ERFOKS_KSERFO_EN                     ((uint32_t)(0x1UL << MXC_F_FCR_ERFOKS_KSERFO_EN_POS)) 
#define MXC_F_FCR_ERFOKS_KSERFODRIVER_POS              8 
#define MXC_F_FCR_ERFOKS_KSERFODRIVER                  ((uint32_t)(0x7UL << MXC_F_FCR_ERFOKS_KSERFODRIVER_POS)) 
#define MXC_F_FCR_ERFOKS_KSERFO2X_POS                  11 
#define MXC_F_FCR_ERFOKS_KSERFO2X                      ((uint32_t)(0x1UL << MXC_F_FCR_ERFOKS_KSERFO2X_POS)) 
#define MXC_F_FCR_ERFOKS_KSCLKSEL_POS                  12 
#define MXC_F_FCR_ERFOKS_KSCLKSEL                      ((uint32_t)(0x3UL << MXC_F_FCR_ERFOKS_KSCLKSEL_POS)) 
#define MXC_V_FCR_ERFOKS_KSCLKSEL_ISO                  ((uint32_t)0x2UL) 
#define MXC_S_FCR_ERFOKS_KSCLKSEL_ISO                  (MXC_V_FCR_ERFOKS_KSCLKSEL_ISO << MXC_F_FCR_ERFOKS_KSCLKSEL_POS) 
#define MXC_V_FCR_ERFOKS_KSCLKSEL_IPO                  ((uint32_t)0x3UL) 
#define MXC_S_FCR_ERFOKS_KSCLKSEL_IPO                  (MXC_V_FCR_ERFOKS_KSCLKSEL_IPO << MXC_F_FCR_ERFOKS_KSCLKSEL_POS) 
#define MXC_F_FCR_ERFO_INTFL_RDY_POS                   0 
#define MXC_F_FCR_ERFO_INTFL_RDY                       ((uint32_t)(0x1UL << MXC_F_FCR_ERFO_INTFL_RDY_POS)) 
#define MXC_F_FCR_ERFO_INTEN_RDY_POS                   0 
#define MXC_F_FCR_ERFO_INTEN_RDY                       ((uint32_t)(0x1UL << MXC_F_FCR_ERFO_INTEN_RDY_POS)) 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_FCR_REGS_H_