MAX32655 Peripheral Driver API
Peripheral Driver API for the MAX32655
ptg_regs.h
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1
8/******************************************************************************
9 *
10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
11 * Analog Devices, Inc.),
12 * Copyright (C) 2023-2024 Analog Devices, Inc.
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 * http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *
26 ******************************************************************************/
27
28#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_PTG_REGS_H_
29#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_PTG_REGS_H_
30
31/* **** Includes **** */
32#include <stdint.h>
33
34#ifdef __cplusplus
35extern "C" {
36#endif
37
38#if defined (__ICCARM__)
39 #pragma system_include
40#endif
41
42#if defined (__CC_ARM)
43 #pragma anon_unions
44#endif
46/*
47 If types are not defined elsewhere (CMSIS) define them here
48*/
49#ifndef __IO
50#define __IO volatile
51#endif
52#ifndef __I
53#define __I volatile const
54#endif
55#ifndef __O
56#define __O volatile
57#endif
58#ifndef __R
59#define __R volatile const
60#endif
62
63/* **** Definitions **** */
64
76typedef struct {
77 __IO uint32_t enable;
78 __IO uint32_t resync;
79 __IO uint32_t stop_intfl;
80 __IO uint32_t stop_inten;
81 __O uint32_t safe_en;
82 __O uint32_t safe_dis;
83 __IO uint32_t ready_intfl;
84 __IO uint32_t ready_inten;
85} mxc_ptg_regs_t;
86
87/* Register offsets for module PTG */
94#define MXC_R_PTG_ENABLE ((uint32_t)0x00000000UL)
95#define MXC_R_PTG_RESYNC ((uint32_t)0x00000004UL)
96#define MXC_R_PTG_STOP_INTFL ((uint32_t)0x00000008UL)
97#define MXC_R_PTG_STOP_INTEN ((uint32_t)0x0000000CUL)
98#define MXC_R_PTG_SAFE_EN ((uint32_t)0x00000010UL)
99#define MXC_R_PTG_SAFE_DIS ((uint32_t)0x00000014UL)
100#define MXC_R_PTG_READY_INTFL ((uint32_t)0x00000018UL)
101#define MXC_R_PTG_READY_INTEN ((uint32_t)0x0000001CUL)
110#define MXC_F_PTG_ENABLE_PT0_POS 0
111#define MXC_F_PTG_ENABLE_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT0_POS))
113#define MXC_F_PTG_ENABLE_PT1_POS 1
114#define MXC_F_PTG_ENABLE_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT1_POS))
116#define MXC_F_PTG_ENABLE_PT2_POS 2
117#define MXC_F_PTG_ENABLE_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT2_POS))
119#define MXC_F_PTG_ENABLE_PT3_POS 3
120#define MXC_F_PTG_ENABLE_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT3_POS))
130#define MXC_F_PTG_RESYNC_PT0_POS 0
131#define MXC_F_PTG_RESYNC_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT0_POS))
133#define MXC_F_PTG_RESYNC_PT1_POS 1
134#define MXC_F_PTG_RESYNC_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT1_POS))
136#define MXC_F_PTG_RESYNC_PT2_POS 2
137#define MXC_F_PTG_RESYNC_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT2_POS))
139#define MXC_F_PTG_RESYNC_PT3_POS 3
140#define MXC_F_PTG_RESYNC_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT3_POS))
150#define MXC_F_PTG_STOP_INTFL_PT0_POS 0
151#define MXC_F_PTG_STOP_INTFL_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT0_POS))
153#define MXC_F_PTG_STOP_INTFL_PT1_POS 1
154#define MXC_F_PTG_STOP_INTFL_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT1_POS))
156#define MXC_F_PTG_STOP_INTFL_PT2_POS 2
157#define MXC_F_PTG_STOP_INTFL_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT2_POS))
159#define MXC_F_PTG_STOP_INTFL_PT3_POS 3
160#define MXC_F_PTG_STOP_INTFL_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT3_POS))
170#define MXC_F_PTG_STOP_INTEN_PT0_POS 0
171#define MXC_F_PTG_STOP_INTEN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT0_POS))
173#define MXC_F_PTG_STOP_INTEN_PT1_POS 1
174#define MXC_F_PTG_STOP_INTEN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT1_POS))
176#define MXC_F_PTG_STOP_INTEN_PT2_POS 2
177#define MXC_F_PTG_STOP_INTEN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT2_POS))
179#define MXC_F_PTG_STOP_INTEN_PT3_POS 3
180#define MXC_F_PTG_STOP_INTEN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT3_POS))
190#define MXC_F_PTG_SAFE_EN_PT0_POS 0
191#define MXC_F_PTG_SAFE_EN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT0_POS))
193#define MXC_F_PTG_SAFE_EN_PT1_POS 1
194#define MXC_F_PTG_SAFE_EN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT1_POS))
196#define MXC_F_PTG_SAFE_EN_PT2_POS 2
197#define MXC_F_PTG_SAFE_EN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT2_POS))
199#define MXC_F_PTG_SAFE_EN_PT3_POS 3
200#define MXC_F_PTG_SAFE_EN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT3_POS))
210#define MXC_F_PTG_SAFE_DIS_PT0_POS 0
211#define MXC_F_PTG_SAFE_DIS_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT0_POS))
213#define MXC_F_PTG_SAFE_DIS_PT1_POS 1
214#define MXC_F_PTG_SAFE_DIS_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT1_POS))
216#define MXC_F_PTG_SAFE_DIS_PT2_POS 2
217#define MXC_F_PTG_SAFE_DIS_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT2_POS))
219#define MXC_F_PTG_SAFE_DIS_PT3_POS 3
220#define MXC_F_PTG_SAFE_DIS_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT3_POS))
230#define MXC_F_PTG_READY_INTFL_PT0_POS 0
231#define MXC_F_PTG_READY_INTFL_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT0_POS))
233#define MXC_F_PTG_READY_INTFL_PT1_POS 1
234#define MXC_F_PTG_READY_INTFL_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT1_POS))
236#define MXC_F_PTG_READY_INTFL_PT2_POS 2
237#define MXC_F_PTG_READY_INTFL_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT2_POS))
239#define MXC_F_PTG_READY_INTFL_PT3_POS 3
240#define MXC_F_PTG_READY_INTFL_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT3_POS))
250#define MXC_F_PTG_READY_INTEN_PT0_POS 0
251#define MXC_F_PTG_READY_INTEN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT0_POS))
253#define MXC_F_PTG_READY_INTEN_PT1_POS 1
254#define MXC_F_PTG_READY_INTEN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT1_POS))
256#define MXC_F_PTG_READY_INTEN_PT2_POS 2
257#define MXC_F_PTG_READY_INTEN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT2_POS))
259#define MXC_F_PTG_READY_INTEN_PT3_POS 3
260#define MXC_F_PTG_READY_INTEN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT3_POS))
264#ifdef __cplusplus
265}
266#endif
267
268#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_PTG_REGS_H_
mxc_ptg_regs_t::safe_dis
__O uint32_t safe_dis
Definition: ptg_regs.h:82
mxc_ptg_regs_t::ready_inten
__IO uint32_t ready_inten
Definition: ptg_regs.h:84
mxc_ptg_regs_t::resync
__IO uint32_t resync
Definition: ptg_regs.h:78
mxc_ptg_regs_t::safe_en
__O uint32_t safe_en
Definition: ptg_regs.h:81
mxc_ptg_regs_t::ready_intfl
__IO uint32_t ready_intfl
Definition: ptg_regs.h:83
mxc_ptg_regs_t::stop_intfl
__IO uint32_t stop_intfl
Definition: ptg_regs.h:79
mxc_ptg_regs_t::stop_inten
__IO uint32_t stop_inten
Definition: ptg_regs.h:80
mxc_ptg_regs_t::enable
__IO uint32_t enable
Definition: ptg_regs.h:77
mxc_ptg_regs_t
Definition: ptg_regs.h:76