Documentation/MAX32655/tmr__regs_8h_source.html

/******************************************************************************

 *

 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by

 * Analog Devices, Inc.),

 * Copyright (C) 2023-2024 Analog Devices, Inc.

 *

 * Licensed under the Apache License, Version 2.0 (the "License");

 * you may not use this file except in compliance with the License.

 * You may obtain a copy of the License at

 *

 *     http://www.apache.org/licenses/LICENSE-2.0

 *

 * Unless required by applicable law or agreed to in writing, software

 * distributed under the License is distributed on an "AS IS" BASIS,

 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

 * See the License for the specific language governing permissions and

 * limitations under the License.

 *

 ******************************************************************************/


#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_TMR_REGS_H_

#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_TMR_REGS_H_


/* **** Includes **** */

#include <stdint.h>


#ifdef __cplusplus

extern "C" {

#endif


#if defined (__ICCARM__)

  #pragma system_include

#endif


#if defined (__CC_ARM)

  #pragma anon_unions

#endif

/*

    If types are not defined elsewhere (CMSIS) define them here

*/

#ifndef __IO

#define __IO volatile

#endif

#ifndef __I

#define __I  volatile const

#endif

#ifndef __O

#define __O  volatile

#endif

#ifndef __R

#define __R  volatile const

#endif


/* **** Definitions **** */


typedef struct {

    __IO uint32_t cnt;

    __IO uint32_t cmp;

    __IO uint32_t pwm;

    __IO uint32_t intfl;

    __IO uint32_t ctrl0;

    __IO uint32_t nolcmp;

    __IO uint32_t ctrl1;

    __IO uint32_t wkfl;

} mxc_tmr_regs_t;


/* Register offsets for module TMR */

#define MXC_R_TMR_CNT                      ((uint32_t)0x00000000UL)

#define MXC_R_TMR_CMP                      ((uint32_t)0x00000004UL)

#define MXC_R_TMR_PWM                      ((uint32_t)0x00000008UL)

#define MXC_R_TMR_INTFL                    ((uint32_t)0x0000000CUL)

#define MXC_R_TMR_CTRL0                    ((uint32_t)0x00000010UL)

#define MXC_R_TMR_NOLCMP                   ((uint32_t)0x00000014UL)

#define MXC_R_TMR_CTRL1                    ((uint32_t)0x00000018UL)

#define MXC_R_TMR_WKFL                     ((uint32_t)0x0000001CUL)

#define MXC_F_TMR_CNT_COUNT_POS                        0

#define MXC_F_TMR_CNT_COUNT                            ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CNT_COUNT_POS))

#define MXC_F_TMR_CMP_COMPARE_POS                      0

#define MXC_F_TMR_CMP_COMPARE                          ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CMP_COMPARE_POS))

#define MXC_F_TMR_PWM_PWM_POS                          0

#define MXC_F_TMR_PWM_PWM                              ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_PWM_PWM_POS))

#define MXC_F_TMR_INTFL_IRQ_A_POS                      0

#define MXC_F_TMR_INTFL_IRQ_A                          ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_A_POS))

#define MXC_F_TMR_INTFL_WRDONE_A_POS                   8

#define MXC_F_TMR_INTFL_WRDONE_A                       ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WRDONE_A_POS))

#define MXC_F_TMR_INTFL_WR_DIS_A_POS                   9

#define MXC_F_TMR_INTFL_WR_DIS_A                       ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WR_DIS_A_POS))

#define MXC_F_TMR_INTFL_IRQ_B_POS                      16

#define MXC_F_TMR_INTFL_IRQ_B                          ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_B_POS))

#define MXC_F_TMR_INTFL_WRDONE_B_POS                   24

#define MXC_F_TMR_INTFL_WRDONE_B                       ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WRDONE_B_POS))

#define MXC_F_TMR_INTFL_WR_DIS_B_POS                   25

#define MXC_F_TMR_INTFL_WR_DIS_B                       ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WR_DIS_B_POS))

#define MXC_F_TMR_CTRL0_MODE_A_POS                     0

#define MXC_F_TMR_CTRL0_MODE_A                         ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_MODE_A_POS))

#define MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT                ((uint32_t)0x0UL)

#define MXC_S_TMR_CTRL0_MODE_A_ONE_SHOT                (MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT << MXC_F_TMR_CTRL0_MODE_A_POS)

#define MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS              ((uint32_t)0x1UL)

#define MXC_S_TMR_CTRL0_MODE_A_CONTINUOUS              (MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS << MXC_F_TMR_CTRL0_MODE_A_POS)

#define MXC_V_TMR_CTRL0_MODE_A_COUNTER                 ((uint32_t)0x2UL)

#define MXC_S_TMR_CTRL0_MODE_A_COUNTER                 (MXC_V_TMR_CTRL0_MODE_A_COUNTER << MXC_F_TMR_CTRL0_MODE_A_POS)

#define MXC_V_TMR_CTRL0_MODE_A_PWM                     ((uint32_t)0x3UL)

#define MXC_S_TMR_CTRL0_MODE_A_PWM                     (MXC_V_TMR_CTRL0_MODE_A_PWM << MXC_F_TMR_CTRL0_MODE_A_POS)

#define MXC_V_TMR_CTRL0_MODE_A_CAPTURE                 ((uint32_t)0x4UL)

#define MXC_S_TMR_CTRL0_MODE_A_CAPTURE                 (MXC_V_TMR_CTRL0_MODE_A_CAPTURE << MXC_F_TMR_CTRL0_MODE_A_POS)

#define MXC_V_TMR_CTRL0_MODE_A_COMPARE                 ((uint32_t)0x5UL)

#define MXC_S_TMR_CTRL0_MODE_A_COMPARE                 (MXC_V_TMR_CTRL0_MODE_A_COMPARE << MXC_F_TMR_CTRL0_MODE_A_POS)

#define MXC_V_TMR_CTRL0_MODE_A_GATED                   ((uint32_t)0x6UL)

#define MXC_S_TMR_CTRL0_MODE_A_GATED                   (MXC_V_TMR_CTRL0_MODE_A_GATED << MXC_F_TMR_CTRL0_MODE_A_POS)

#define MXC_V_TMR_CTRL0_MODE_A_CAPCOMP                 ((uint32_t)0x7UL)

#define MXC_S_TMR_CTRL0_MODE_A_CAPCOMP                 (MXC_V_TMR_CTRL0_MODE_A_CAPCOMP << MXC_F_TMR_CTRL0_MODE_A_POS)

#define MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE               ((uint32_t)0x8UL)

#define MXC_S_TMR_CTRL0_MODE_A_DUAL_EDGE               (MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE << MXC_F_TMR_CTRL0_MODE_A_POS)

#define MXC_V_TMR_CTRL0_MODE_A_IGATED                  ((uint32_t)0xEUL)

#define MXC_S_TMR_CTRL0_MODE_A_IGATED                  (MXC_V_TMR_CTRL0_MODE_A_IGATED << MXC_F_TMR_CTRL0_MODE_A_POS)

#define MXC_F_TMR_CTRL0_CLKDIV_A_POS                   4

#define MXC_F_TMR_CTRL0_CLKDIV_A                       ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_CLKDIV_A_POS))

#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1              ((uint32_t)0x0UL)

#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1              (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2              ((uint32_t)0x1UL)

#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2              (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4              ((uint32_t)0x2UL)

#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4              (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_8              ((uint32_t)0x3UL)

#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_8              (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_8 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_16             ((uint32_t)0x4UL)

#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_16             (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_16 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_32             ((uint32_t)0x5UL)

#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_32             (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_32 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_64             ((uint32_t)0x6UL)

#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_64             (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_64 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_128            ((uint32_t)0x7UL)

#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_128            (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_128 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_256            ((uint32_t)0x8UL)

#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_256            (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_256 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_512            ((uint32_t)0x9UL)

#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_512            (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_512 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1024           ((uint32_t)0xAUL)

#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1024           (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2048           ((uint32_t)0xBUL)

#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2048           (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4096           ((uint32_t)0xCUL)

#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4096           (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

#define MXC_F_TMR_CTRL0_POL_A_POS                      8

#define MXC_F_TMR_CTRL0_POL_A                          ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_POL_A_POS))

#define MXC_F_TMR_CTRL0_PWMSYNC_A_POS                  9

#define MXC_F_TMR_CTRL0_PWMSYNC_A                      ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMSYNC_A_POS))

#define MXC_F_TMR_CTRL0_NOLHPOL_A_POS                  10

#define MXC_F_TMR_CTRL0_NOLHPOL_A                      ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLHPOL_A_POS))

#define MXC_F_TMR_CTRL0_NOLLPOL_A_POS                  11

#define MXC_F_TMR_CTRL0_NOLLPOL_A                      ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLLPOL_A_POS))

#define MXC_F_TMR_CTRL0_PWMCKBD_A_POS                  12

#define MXC_F_TMR_CTRL0_PWMCKBD_A                      ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMCKBD_A_POS))

#define MXC_F_TMR_CTRL0_RST_A_POS                      13

#define MXC_F_TMR_CTRL0_RST_A                          ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_RST_A_POS))

#define MXC_F_TMR_CTRL0_CLKEN_A_POS                    14

#define MXC_F_TMR_CTRL0_CLKEN_A                        ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_CLKEN_A_POS))

#define MXC_F_TMR_CTRL0_EN_A_POS                       15

#define MXC_F_TMR_CTRL0_EN_A                           ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_EN_A_POS))

#define MXC_F_TMR_CTRL0_MODE_B_POS                     16

#define MXC_F_TMR_CTRL0_MODE_B                         ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_MODE_B_POS))

#define MXC_V_TMR_CTRL0_MODE_B_ONE_SHOT                ((uint32_t)0x0UL)

#define MXC_S_TMR_CTRL0_MODE_B_ONE_SHOT                (MXC_V_TMR_CTRL0_MODE_B_ONE_SHOT << MXC_F_TMR_CTRL0_MODE_B_POS)

#define MXC_V_TMR_CTRL0_MODE_B_CONTINUOUS              ((uint32_t)0x1UL)

#define MXC_S_TMR_CTRL0_MODE_B_CONTINUOUS              (MXC_V_TMR_CTRL0_MODE_B_CONTINUOUS << MXC_F_TMR_CTRL0_MODE_B_POS)

#define MXC_V_TMR_CTRL0_MODE_B_COUNTER                 ((uint32_t)0x2UL)

#define MXC_S_TMR_CTRL0_MODE_B_COUNTER                 (MXC_V_TMR_CTRL0_MODE_B_COUNTER << MXC_F_TMR_CTRL0_MODE_B_POS)

#define MXC_V_TMR_CTRL0_MODE_B_PWM                     ((uint32_t)0x3UL)

#define MXC_S_TMR_CTRL0_MODE_B_PWM                     (MXC_V_TMR_CTRL0_MODE_B_PWM << MXC_F_TMR_CTRL0_MODE_B_POS)

#define MXC_V_TMR_CTRL0_MODE_B_CAPTURE                 ((uint32_t)0x4UL)

#define MXC_S_TMR_CTRL0_MODE_B_CAPTURE                 (MXC_V_TMR_CTRL0_MODE_B_CAPTURE << MXC_F_TMR_CTRL0_MODE_B_POS)

#define MXC_V_TMR_CTRL0_MODE_B_COMPARE                 ((uint32_t)0x5UL)

#define MXC_S_TMR_CTRL0_MODE_B_COMPARE                 (MXC_V_TMR_CTRL0_MODE_B_COMPARE << MXC_F_TMR_CTRL0_MODE_B_POS)

#define MXC_V_TMR_CTRL0_MODE_B_GATED                   ((uint32_t)0x6UL)

#define MXC_S_TMR_CTRL0_MODE_B_GATED                   (MXC_V_TMR_CTRL0_MODE_B_GATED << MXC_F_TMR_CTRL0_MODE_B_POS)

#define MXC_V_TMR_CTRL0_MODE_B_CAPCOMP                 ((uint32_t)0x7UL)

#define MXC_S_TMR_CTRL0_MODE_B_CAPCOMP                 (MXC_V_TMR_CTRL0_MODE_B_CAPCOMP << MXC_F_TMR_CTRL0_MODE_B_POS)

#define MXC_V_TMR_CTRL0_MODE_B_DUAL_EDGE               ((uint32_t)0x8UL)

#define MXC_S_TMR_CTRL0_MODE_B_DUAL_EDGE               (MXC_V_TMR_CTRL0_MODE_B_DUAL_EDGE << MXC_F_TMR_CTRL0_MODE_B_POS)

#define MXC_V_TMR_CTRL0_MODE_B_IGATED                  ((uint32_t)0xEUL)

#define MXC_S_TMR_CTRL0_MODE_B_IGATED                  (MXC_V_TMR_CTRL0_MODE_B_IGATED << MXC_F_TMR_CTRL0_MODE_B_POS)

#define MXC_F_TMR_CTRL0_CLKDIV_B_POS                   20

#define MXC_F_TMR_CTRL0_CLKDIV_B                       ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_CLKDIV_B_POS))

#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1              ((uint32_t)0x0UL)

#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_1              (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2              ((uint32_t)0x1UL)

#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_2              (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4              ((uint32_t)0x2UL)

#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_4              (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_8              ((uint32_t)0x3UL)

#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_8              (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_8 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_16             ((uint32_t)0x4UL)

#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_16             (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_16 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_32             ((uint32_t)0x5UL)

#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_32             (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_32 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_64             ((uint32_t)0x6UL)

#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_64             (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_64 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_128            ((uint32_t)0x7UL)

#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_128            (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_128 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_256            ((uint32_t)0x8UL)

#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_256            (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_256 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_512            ((uint32_t)0x9UL)

#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_512            (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_512 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1024           ((uint32_t)0xAUL)

#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_1024           (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2048           ((uint32_t)0xBUL)

#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_2048           (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4096           ((uint32_t)0xCUL)

#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_4096           (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

#define MXC_F_TMR_CTRL0_POL_B_POS                      24

#define MXC_F_TMR_CTRL0_POL_B                          ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_POL_B_POS))

#define MXC_F_TMR_CTRL0_PWMSYNC_B_POS                  25

#define MXC_F_TMR_CTRL0_PWMSYNC_B                      ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMSYNC_B_POS))

#define MXC_F_TMR_CTRL0_NOLHPOL_B_POS                  26

#define MXC_F_TMR_CTRL0_NOLHPOL_B                      ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLHPOL_B_POS))

#define MXC_F_TMR_CTRL0_NOLLPOL_B_POS                  27

#define MXC_F_TMR_CTRL0_NOLLPOL_B                      ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLLPOL_B_POS))

#define MXC_F_TMR_CTRL0_PWMCKBD_B_POS                  28

#define MXC_F_TMR_CTRL0_PWMCKBD_B                      ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMCKBD_B_POS))

#define MXC_F_TMR_CTRL0_RST_B_POS                      29

#define MXC_F_TMR_CTRL0_RST_B                          ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_RST_B_POS))

#define MXC_F_TMR_CTRL0_CLKEN_B_POS                    30

#define MXC_F_TMR_CTRL0_CLKEN_B                        ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_CLKEN_B_POS))

#define MXC_F_TMR_CTRL0_EN_B_POS                       31

#define MXC_F_TMR_CTRL0_EN_B                           ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_EN_B_POS))

#define MXC_F_TMR_NOLCMP_LO_A_POS                      0

#define MXC_F_TMR_NOLCMP_LO_A                          ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_LO_A_POS))

#define MXC_F_TMR_NOLCMP_HI_A_POS                      8

#define MXC_F_TMR_NOLCMP_HI_A                          ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_HI_A_POS))

#define MXC_F_TMR_NOLCMP_LO_B_POS                      16

#define MXC_F_TMR_NOLCMP_LO_B                          ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_LO_B_POS))

#define MXC_F_TMR_NOLCMP_HI_B_POS                      24

#define MXC_F_TMR_NOLCMP_HI_B                          ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_HI_B_POS))

#define MXC_F_TMR_CTRL1_CLKSEL_A_POS                   0

#define MXC_F_TMR_CTRL1_CLKSEL_A                       ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_A_POS))

#define MXC_F_TMR_CTRL1_CLKEN_A_POS                    2

#define MXC_F_TMR_CTRL1_CLKEN_A                        ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKEN_A_POS))

#define MXC_F_TMR_CTRL1_CLKRDY_A_POS                   3

#define MXC_F_TMR_CTRL1_CLKRDY_A                       ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKRDY_A_POS))

#define MXC_F_TMR_CTRL1_EVENT_SEL_A_POS                4

#define MXC_F_TMR_CTRL1_EVENT_SEL_A                    ((uint32_t)(0x7UL << MXC_F_TMR_CTRL1_EVENT_SEL_A_POS))

#define MXC_F_TMR_CTRL1_NEGTRIG_A_POS                  7

#define MXC_F_TMR_CTRL1_NEGTRIG_A                      ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_NEGTRIG_A_POS))

#define MXC_F_TMR_CTRL1_IE_A_POS                       8

#define MXC_F_TMR_CTRL1_IE_A                           ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_IE_A_POS))

#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_A_POS             9

#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_A                 ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CAPEVENT_SEL_A_POS))

#define MXC_F_TMR_CTRL1_SW_CAPEVENT_A_POS              11

#define MXC_F_TMR_CTRL1_SW_CAPEVENT_A                  ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_SW_CAPEVENT_A_POS))

#define MXC_F_TMR_CTRL1_WE_A_POS                       12

#define MXC_F_TMR_CTRL1_WE_A                           ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_WE_A_POS))

#define MXC_F_TMR_CTRL1_OUTEN_A_POS                    13

#define MXC_F_TMR_CTRL1_OUTEN_A                        ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTEN_A_POS))

#define MXC_F_TMR_CTRL1_OUTBEN_A_POS                   14

#define MXC_F_TMR_CTRL1_OUTBEN_A                       ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS))

#define MXC_F_TMR_CTRL1_CLKSEL_B_POS                   16

#define MXC_F_TMR_CTRL1_CLKSEL_B                       ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS))

#define MXC_F_TMR_CTRL1_CLKEN_B_POS                    18

#define MXC_F_TMR_CTRL1_CLKEN_B                        ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKEN_B_POS))

#define MXC_F_TMR_CTRL1_CLKRDY_B_POS                   19

#define MXC_F_TMR_CTRL1_CLKRDY_B                       ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKRDY_B_POS))

#define MXC_F_TMR_CTRL1_EVENT_SEL_B_POS                20

#define MXC_F_TMR_CTRL1_EVENT_SEL_B                    ((uint32_t)(0x7UL << MXC_F_TMR_CTRL1_EVENT_SEL_B_POS))

#define MXC_F_TMR_CTRL1_NEGTRIG_B_POS                  23

#define MXC_F_TMR_CTRL1_NEGTRIG_B                      ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_NEGTRIG_B_POS))

#define MXC_F_TMR_CTRL1_IE_B_POS                       24

#define MXC_F_TMR_CTRL1_IE_B                           ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_IE_B_POS))

#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_B_POS             25

#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_B                 ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CAPEVENT_SEL_B_POS))

#define MXC_F_TMR_CTRL1_SW_CAPEVENT_B_POS              27

#define MXC_F_TMR_CTRL1_SW_CAPEVENT_B                  ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_SW_CAPEVENT_B_POS))

#define MXC_F_TMR_CTRL1_WE_B_POS                       28

#define MXC_F_TMR_CTRL1_WE_B                           ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_WE_B_POS))

#define MXC_F_TMR_CTRL1_CASCADE_POS                    31

#define MXC_F_TMR_CTRL1_CASCADE                        ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CASCADE_POS))

#define MXC_F_TMR_WKFL_A_POS                           0

#define MXC_F_TMR_WKFL_A                               ((uint32_t)(0x1UL << MXC_F_TMR_WKFL_A_POS))

#define MXC_F_TMR_WKFL_B_POS                           16

#define MXC_F_TMR_WKFL_B                               ((uint32_t)(0x1UL << MXC_F_TMR_WKFL_B_POS))

#ifdef __cplusplus

}

#endif


#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_TMR_REGS_H_

mxc_tmr_regs_t::ctrl0
__IO uint32_t ctrl0
Definition: tmr_regs.h:81

mxc_tmr_regs_t::pwm
__IO uint32_t pwm
Definition: tmr_regs.h:79

mxc_tmr_regs_t::intfl
__IO uint32_t intfl
Definition: tmr_regs.h:80

mxc_tmr_regs_t::wkfl
__IO uint32_t wkfl
Definition: tmr_regs.h:84

mxc_tmr_regs_t::nolcmp
__IO uint32_t nolcmp
Definition: tmr_regs.h:82

mxc_tmr_regs_t::cnt
__IO uint32_t cnt
Definition: tmr_regs.h:77

mxc_tmr_regs_t::cmp
__IO uint32_t cmp
Definition: tmr_regs.h:78

mxc_tmr_regs_t::ctrl1
__IO uint32_t ctrl1
Definition: tmr_regs.h:83

mxc_tmr_regs_t
Definition: tmr_regs.h:76