pwrseq_regs.h

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/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_PWRSEQ_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_PWRSEQ_REGS_H_
 
/* **** Includes **** */
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined (__ICCARM__)
  #pragma system_include
#endif
 
#if defined (__CC_ARM)
  #pragma anon_unions
#endif
/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif
#ifndef __R
#define __R  volatile const
#endif
 
/* **** Definitions **** */
 
typedef struct {
    __IO uint32_t lp_ctrl;              
    __IO uint32_t lp_wakefl;            
    __IO uint32_t lpwk_en;              
    __R  uint32_t rsv_0xc_0x3f[13];
    __IO uint32_t lpmemsd;              
} mxc_pwrseq_regs_t;
 
/* Register offsets for module PWRSEQ */
#define MXC_R_PWRSEQ_LP_CTRL               ((uint32_t)0x00000000UL) 
#define MXC_R_PWRSEQ_LP_WAKEFL             ((uint32_t)0x00000004UL) 
#define MXC_R_PWRSEQ_LPWK_EN               ((uint32_t)0x00000008UL) 
#define MXC_R_PWRSEQ_LPMEMSD               ((uint32_t)0x00000040UL) 
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS           0 
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0               ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS)) 
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS           1 
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1               ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS)) 
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS           2 
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2               ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS)) 
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS           3 
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3               ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS)) 
#define MXC_F_PWRSEQ_LP_CTRL_OVR_POS                   4 
#define MXC_F_PWRSEQ_LP_CTRL_OVR                       ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LP_CTRL_OVR_POS)) 
#define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V                  ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V                  (MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) 
#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V                  ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V                  (MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) 
#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V                  ((uint32_t)0x2UL) 
#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V                  (MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) 
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS      6 
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS          ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS)) 
#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS             8 
#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN                 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS)) 
#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS            10 
#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN                ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS)) 
#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS                11 
#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF                    ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS)) 
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS         12 
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS             ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS)) 
#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS               16 
#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS)) 
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS         20 
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS             ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS)) 
#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS         25 
#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS             ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS)) 
#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS              0 
#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST                  ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) 
#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS                0 
#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN                    ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS             0 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF                 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS)) 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS             1 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF                 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS)) 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS             2 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF                 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS)) 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS             3 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF                 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS)) 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_PWRSEQ_REGS_H_