MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
max32665.h
1/******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_MAX32665_H_
22#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_MAX32665_H_
23
24// clang-format off
25
26#ifndef TARGET_NUM
27#define TARGET_NUM 32665
28#endif
29
30#define MXC_NUMCORES 2
31
32#include <stdint.h>
33
34#ifndef FALSE
35#define FALSE (0)
36#endif
37
38#ifndef TRUE
39#define TRUE (1)
40#endif
41
42#if !defined(__GNUC__)
43#define CMSIS_VECTAB_VIRTUAL
44#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "nvic_table.h"
45#endif
46
47/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
48#if defined(__GNUC__)
49
50#ifndef __weak
51#define __weak __attribute__((weak))
52#endif
53
54#elif defined(__CC_ARM)
55
56#define inline __inline
57#pragma anon_unions
58
59#endif
60
61typedef enum {
62 NonMaskableInt_IRQn = -14,
63 HardFault_IRQn = -13,
64 MemoryManagement_IRQn = -12,
65 BusFault_IRQn = -11,
66 UsageFault_IRQn = -10,
67 SVCall_IRQn = -5,
68 DebugMonitor_IRQn = -4,
69 PendSV_IRQn = -2,
70 SysTick_IRQn = -1,
71
72 /* Device-specific interrupt sources (external to ARM core) */
73 /* table entry number */
74 /* |||| */
75 /* |||| table offset address */
76 /* vvvv vvvvvv */
77
78 PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */
79 WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */
80 USB_IRQn, /* 0x12 0x0048 18: USB */
81 RTC_IRQn, /* 0x13 0x004C 19: RTC */
82 TRNG_IRQn, /* 0x14 0x0050 20: True Random Number Generator */
83 TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */
84 TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */
85 TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */
86 TMR3_IRQn, /* 0x18 0x0060 24: Timer 3*/
87 TMR4_IRQn, /* 0x19 0x0064 25: Timer 4*/
88 TMR5_IRQn, /* 0x1A 0x0068 26: Timer 5 */
89 RSV11_IRQn, /* 0x1B 0x006C 27: Reserved */
90 RSV12_IRQn, /* 0x1C 0x0070 28: Reserved */
91 I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */
92 UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */
93 UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */
94 SPI1_IRQn, /* 0x20 0x0080 32: SPI1 */
95 SPI2_IRQn, /* 0x21 0x0084 33: SPI2 */
96 RSV18_IRQn, /* 0x22 0x0088 34: Reserved */
97 RSV19_IRQn, /* 0x23 0x008C 35: Reserved */
98 ADC_IRQn, /* 0x24 0x0090 36: ADC */
99 RSV21_IRQn, /* 0x25 0x0094 37: Reserved */
100 RSV22_IRQn, /* 0x26 0x0098 38: Reserved */
101 FLC0_IRQn, /* 0x27 0x009C 39: Flash Controller 0 */
102 GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */
103 GPIO1_IRQn, /* 0x29 0x00A4 41: GPIO1 */
104 RSV26_IRQn, /* 0x2A 0x00A8 42: Reserved */
105 TPU_IRQn, /* 0x2B 0x00AC 43: Crypto */
106 DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */
107 DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */
108 DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */
109 DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */
110 RSV32_IRQn, /* 0x30 0x00C0 48: Reserved */
111 RSV33_IRQn, /* 0x31 0x00C4 49: Reserved */
112 UART2_IRQn, /* 0x32 0x00C8 50: UART 2 */
113 RSV35_IRQn, /* 0x33 0x00CC 51: Reserved */
114 I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */
115 RSV36_IRQn, /* 0x35 0x00D4 53: Reserved */
116 SPIXFC_IRQn, /* 0x36 0x00D8 54: SPI execute in place */
117 BTLE_TX_DONE_IRQn, /* 0x37 0x00DC 55: BTLE TX Done */
118 BTLE_RX_RCVD_IRQn, /* 0x38 0x00E0 56: BTLE RX Received */
119 BTLE_RX_ENG_DET_IRQn, /* 0x39 0x00E4 57: BTLE RX Energy Detected */
120 BTLE_SFD_DET_IRQn, /* 0x3A 0x00E8 58: BTLE SFD Detected */
121 BTLE_SFD_TO_IRQn, /* 0x3B 0x00EC 59: BTLE SFD Timeout*/
122 BTLE_GP_EVENT_IRQn, /* 0x3C 0x00F0 60: BTLE Timestamp*/
123 BTLE_CFO_IRQn, /* 0x3D 0x00F4 61: BTLE CFO Done */
124 BTLE_SIG_DET_IRQn, /* 0x3E 0x00F8 62: BTLE Signal Detected */
125 BTLE_AGC_EVENT_IRQn, /* 0x3F 0x00FC 63: BTLE AGC Event */
126 BTLE_RFFE_SPIM_IRQn, /* 0x40 0x0100 64: BTLE RFFE SPIM Done */
127 BTLE_TX_AES_IRQn, /* 0x41 0x0104 65: BTLE TX AES Done */
128 BTLE_RX_AES_IRQn, /* 0x42 0x0108 66: BTLE RX AES Done */
129 BTLE_INV_APB_ADDR_IRQn, /* 0x43 0x010C 67: BTLE Invalid APB Address*/
130 BTLE_IQ_DATA_VALID_IRQn, /* 0x44 0x0110 68: BTLE IQ Data Valid */
131 WUT_IRQn, /* 0x45 0x0114 69: WUT Wakeup */
132 GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIO Wakeup */
133 RSV55_IRQn, /* 0x47 0x011C 71: Reserved */
134 SPI0_IRQn, /* 0x48 0x0120 72: SPI0 AHB*/
135 WDT1_IRQn, /* 0x49 0x0124 73: Watchdog 1 */
136 RSV58_IRQn, /* 0x4A 0x0128 74: Reserved */
137 PT_IRQn, /* 0x4B 0x012C 75: Pulse train */
138 SDMA_IRQn, /* 0x4C 0x0130 76: Smart DMA 0 */
139 RSV61_IRQn, /* 0x4D 0x0134 77: Reserved */
140 I2C2_IRQn, /* 0x4E 0x0138 78: I2C 2 */
141 RSV63_IRQn, /* 0x4F 0x013C 79: Reserved */
142 RSV64_IRQn, /* 0x50 0x0140 80: Reserved */
143 RSV65_IRQn, /* 0x51 0x0144 81: Reserved */
144 SDHC_IRQn, /* 0x52 0x0148 82: SDIO/SDHC */
145 OWM_IRQn, /* 0x53 0x014C 83: One Wire Master */
146 DMA4_IRQn, /* 0x54 0x0150 84: DMA4 */
147 DMA5_IRQn, /* 0x55 0x0154 85: DMA5 */
148 DMA6_IRQn, /* 0x56 0x0158 86: DMA6 */
149 DMA7_IRQn, /* 0x57 0x015C 87: DMA7 */
150 DMA8_IRQn, /* 0x58 0x0160 88: DMA8 */
151 DMA9_IRQn, /* 0x59 0x0164 89: DMA9 */
152 DMA10_IRQn, /* 0x5A 0x0168 90: DMA10 */
153 DMA11_IRQn, /* 0x5B 0x016C 91: DMA11 */
154 DMA12_IRQn, /* 0x5C 0x0170 92: DMA12 */
155 DMA13_IRQn, /* 0x5D 0x0174 93: DMA13 */
156 DMA14_IRQn, /* 0x5E 0x0178 94: DMA14 */
157 DMA15_IRQn, /* 0x5F 0x017C 95: DMA15 */
158 USBDMA_IRQn, /* 0x60 0x0180 96: USB DMA */
159 WDT2_IRQn, /* 0x61 0x0184 97: Watchdog Timer 2 */
160 ECC_IRQn, /* 0x62 0x0188 98: Error Correction */
161 DVS_IRQn, /* 0x63 0x018C 99: DVS Controller */
162 SIMO_IRQn, /* 0x64 0x0190 100: SIMO Controller */
163 SCA_IRQn, /* 0x65 0x0194 101: SCA */
164 AUDIO_IRQn, /* 0x66 0x0198 102: Audio subsystem */
165 FLC1_IRQn, /* 0x67 0x019C 103: Flash Control 1 */
166 UART3_IRQn, /* 0x68 0x01A0 104: UART 3 */
167 UART4_IRQn, /* 0x69 0x01A4 105: UART 4 */
168 UART5_IRQn, /* 0x6A 0x01A8 106: UART 5 */
169 CameraIF_IRQn, /* 0x6B 0x01AC 107: Camera IF */
170 I3C_IRQn, /* 0x6C 0x01B0 108: I3C */
171 HTMR0_IRQn, /* 0x6D 0x01B4 109: HTimer0 */
172 HTMR1_IRQn, /* 0x6E 0x01B8 110: HTimer1 */
173 MXC_IRQ_EXT_COUNT
174} IRQn_Type;
175
176#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
177
178/* ================================================================================ */
179/* ================ Processor and Core Peripheral Section ================ */
180/* ================================================================================ */
181
182/* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */
183#define __CM4_REV 0x0100
184#define __MPU_PRESENT 1
185#define __NVIC_PRIO_BITS 3
186#define __Vendor_SysTickConfig 0
187#define __FPU_PRESENT 1
189#include <core_cm4.h>
191#include "system_max32665.h"
192#include "system_core1_max32665.h"
194/* ================================================================================ */
195/* ================== Device Specific Memory Section ================== */
196/* ================================================================================ */
197
198#define MXC_ROM_MEM_BASE 0x00000000UL
199#define MXC_ROM_MEM_SIZE 0x00020000UL
200#define MXC_XIP_MEM_BASE 0x08000000UL
201#define MXC_XIP_MEM_SIZE 0x08000000UL
202#define MXC_FLASH0_MEM_BASE 0x10000000UL
203#define MXC_FLASH1_MEM_BASE 0x10080000UL
204#define MXC_FLASH_MEM_BASE MXC_FLASH0_MEM_BASE
205#define MXC_FLASH_PAGE_SIZE 0x00002000UL
206#define MXC_FLASH_MEM_SIZE 0x00080000UL
207#define MXC_INFO0_MEM_BASE 0x10800000UL
208#define MXC_INFO1_MEM_BASE 0x10804000UL
209#define MXC_INFO_MEM_BASE MXC_INFO0_MEM_BASE
210#define MXC_INFO_MEM_SIZE 0x00004000UL
211#define MXC_SRAM_MEM_BASE 0x20000000UL
212#define MXC_SRAM_MEM_SIZE 0x0008C000UL
213#define MXC_XIP_DATA_MEM_BASE 0x80000000UL
214#define MXC_XIP_DATA_MEM_SIZE 0x20000000UL
215
216/* ================================================================================ */
217/* ================ Device Specific Peripheral Section ================ */
218/* ================================================================================ */
219
220/*
221 Base addresses and configuration settings for all MAX32665 peripheral modules.
222*/
223
224/******************************************************************************/
225/* Global control */
226#define MXC_BASE_GCR ((uint32_t)0x40000000UL)
227#define MXC_GCR ((mxc_gcr_regs_t *)MXC_BASE_GCR)
228
229/******************************************************************************/
230/* Non-battery backed SI Registers */
231#define MXC_BASE_SIR ((uint32_t)0x40000400UL)
232#define MXC_SIR ((mxc_sir_regs_t *)MXC_BASE_SIR)
233
234/******************************************************************************/
235/* Non-battery backed Function Control */
236#define MXC_BASE_FCR ((uint32_t)0x40000800UL)
237#define MXC_FCR ((mxc_fcr_regs_t *)MXC_BASE_FCR)
238
239/******************************************************************************/
240/* Trust Protection Unit */
241#define MXC_BASE_TPU ((uint32_t)0x40001000UL)
242#define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU)
243
244/******************************************************************************/
245/* RPU */
246#define MXC_BASE_RPU ((uint32_t)0x40002000UL)
247#define MXC_RPU ((mxc_rpu_regs_t *)MXC_BASE_RPU)
248#define MXC_RPU_NUM_BUS_MASTERS 9
249
250/******************************************************************************/
251/* Watchdog */
252#define MXC_BASE_WDT0 ((uint32_t)0x40003000UL)
253#define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
254#define MXC_BASE_WDT1 ((uint32_t)0x40003400UL)
255#define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1)
256#define MXC_BASE_WDT2 ((uint32_t)0x40003800UL)
257#define MXC_WDT2 ((mxc_wdt_regs_t *)MXC_BASE_WDT2)
258
259/******************************************************************************/
260/* Security Monitor */
261#define MXC_BASE_SMON ((uint32_t)0x40004000UL)
262#define MXC_SMON ((mxc_smon_regs_t *)MXC_BASE_SMON)
263
264/******************************************************************************/
265/* SIMO */
266#define MXC_BASE_SIMO ((uint32_t)0x40004400UL)
267#define MXC_SIMO ((mxc_simo_regs_t *)MXC_BASE_SIMO)
268
269/******************************************************************************/
270/* DVS */
271#define MXC_BASE_DVS ((uint32_t)0x40004800UL)
272#define MXC_DVS ((mxc_dvs_regs_t *)MXC_BASE_DVS)
273
274/******************************************************************************/
275/* AES Keys */
276#define MXC_BASE_AESKEYS ((uint32_t)0x40005000UL)
277#define MXC_AESKEYS ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS)
278
279// DEPRECATED(1-10-2023): Scheduled for removal.
280#define MXC_BASE_AESKEY MXC_BASE_AESKEYS
281#define MXC_AESKEY ((mxc_aes_key_regs_t *)MXC_BASE_AESKEY)
282
283/******************************************************************************/
284/* Trim System Initalization Register */
285#define MXC_BASE_TRIMSIR ((uint32_t)0x40005400UL)
286#define MXC_TRIMSIR ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR)
287
288/******************************************************************************/
289/* Real Time Clock */
290#define MXC_BASE_RTC ((uint32_t)0x40006000UL)
291#define MXC_RTC ((mxc_rtc_regs_t *)MXC_BASE_RTC)
292
293/******************************************************************************/
294/* Wakeup Timer */
295#define MXC_BASE_WUT ((uint32_t)0x40006400UL)
296#define MXC_WUT ((mxc_wut_regs_t *)MXC_BASE_WUT)
297
298/******************************************************************************/
299/* Power Sequencer */
300#define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL)
301#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
302/******************************************************************************/
303/* Power Sequencer */
304#define MXC_BASE_MCR ((uint32_t)0x40006C00UL)
305#define MXC_MCR ((mxc_mcr_regs_t *)MXC_BASE_MCR)
306
307/******************************************************************************/
308/* GPIO */
309#define MXC_CFG_GPIO_INSTANCES (2)
310#define MXC_CFG_GPIO_PINS_PORT (32)
311
312#define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL)
313#define MXC_GPIO0 ((mxc_gpio_regs_t *)MXC_BASE_GPIO0)
314#define MXC_BASE_GPIO1 ((uint32_t)0x40009000UL)
315#define MXC_GPIO1 ((mxc_gpio_regs_t *)MXC_BASE_GPIO1)
316
317#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : (p) == MXC_GPIO1 ? 1 : -1)
318
319#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : (i) == 1 ? MXC_GPIO1 : 0)
320
321#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : (i) == 1 ? GPIO1_IRQn : (IRQn_Type)0)
322
323/******************************************************************************/
324/* Timer */
325#define MXC_CFG_TMR_INSTANCES (6)
326
327#define MXC_BASE_TMR0 ((uint32_t)0x40010000UL)
328#define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0)
329#define MXC_BASE_TMR1 ((uint32_t)0x40011000UL)
330#define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1)
331#define MXC_BASE_TMR2 ((uint32_t)0x40012000UL)
332#define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2)
333#define MXC_BASE_TMR3 ((uint32_t)0x40013000UL)
334#define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3)
335#define MXC_BASE_TMR4 ((uint32_t)0x40014000UL)
336#define MXC_TMR4 ((mxc_tmr_regs_t *)MXC_BASE_TMR4)
337#define MXC_BASE_TMR5 ((uint32_t)0x40015000UL)
338#define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5)
339
340#define MXC_TMR_GET_IRQ(i) \
341 (IRQn_Type)((i) == 0 ? TMR0_IRQn : \
342 (i) == 1 ? TMR1_IRQn : \
343 (i) == 2 ? TMR2_IRQn : \
344 (i) == 3 ? TMR3_IRQn : \
345 (i) == 4 ? TMR4_IRQn : \
346 (i) == 5 ? TMR5_IRQn : \
347 0)
348
349#define MXC_TMR_GET_BASE(i) \
350 ((i) == 0 ? MXC_BASE_TMR0 : \
351 (i) == 1 ? MXC_BASE_TMR1 : \
352 (i) == 2 ? MXC_BASE_TMR2 : \
353 (i) == 3 ? MXC_BASE_TMR3 : \
354 (i) == 4 ? MXC_BASE_TMR4 : \
355 (i) == 5 ? MXC_BASE_TMR5 : \
356 0)
357
358#define MXC_TMR_GET_TMR(i) \
359 ((i) == 0 ? MXC_TMR0 : \
360 (i) == 1 ? MXC_TMR1 : \
361 (i) == 2 ? MXC_TMR2 : \
362 (i) == 3 ? MXC_TMR3 : \
363 (i) == 4 ? MXC_TMR4 : \
364 (i) == 5 ? MXC_TMR5 : \
365 0)
366
367#define MXC_TMR_GET_IDX(p) \
368 ((p) == MXC_TMR0 ? 0 : \
369 (p) == MXC_TMR1 ? 1 : \
370 (p) == MXC_TMR2 ? 2 : \
371 (p) == MXC_TMR3 ? 3 : \
372 (p) == MXC_TMR4 ? 4 : \
373 (p) == MXC_TMR5 ? 5 : \
374 -1)
375
376/******************************************************************************/
377/* High Speed Timer */
378#define MXC_BASE_HTMR0 ((uint32_t)0x4001B000UL)
379#define MXC_HTMR0 ((mxc_htmr_regs_t *)MXC_BASE_HTMR0)
380#define MXC_BASE_HTMR1 ((uint32_t)0x4001C000UL)
381#define MXC_HTMR1 ((mxc_htmr_regs_t *)MXC_BASE_HTMR1)
382
383/******************************************************************************/
384/* I2C */
385#define MXC_I2C_INSTANCES (3)
386
387#define MXC_BASE_I2C0_BUS0 ((uint32_t)0x4001D000UL)
388#define MXC_I2C0_BUS0 ((mxc_i2c_regs_t *)MXC_BASE_I2C0_BUS0)
389#define MXC_BASE_I2C1_BUS0 ((uint32_t)0x4001E000UL)
390#define MXC_I2C1_BUS0 ((mxc_i2c_regs_t *)MXC_BASE_I2C1_BUS0)
391#define MXC_BASE_I2C2_BUS0 ((uint32_t)0x4001F000UL)
392#define MXC_I2C2_BUS0 ((mxc_i2c_regs_t *)MXC_BASE_I2C2_BUS0)
393
394#define MXC_BASE_I2C0_BUS1 ((uint32_t)0x4011D000UL)
395#define MXC_I2C0_BUS1 ((mxc_i2c_regs_t *)MXC_BASE_I2C0_BUS1)
396#define MXC_BASE_I2C1_BUS1 ((uint32_t)0x4011E000UL)
397#define MXC_I2C1_BUS1 ((mxc_i2c_regs_t *)MXC_BASE_I2C1_BUS1)
398#define MXC_BASE_I2C2_BUS1 ((uint32_t)0x4011F000UL)
399#define MXC_I2C2_BUS1 ((mxc_i2c_regs_t *)MXC_BASE_I2C2_BUS1)
400
401#define MXC_I2C_GET_IRQ(i) \
402 (IRQn_Type)((i) == 0x0 ? I2C0_IRQn : \
403 (i) == 0x1 ? I2C1_IRQn : \
404 (i) == 0x2 ? I2C2_IRQn : \
405 (i) == 0x8000 ? I2C0_IRQn : \
406 (i) == 0x8001 ? I2C1_IRQn : \
407 (i) == 0x8002 ? I2C2_IRQn : \
408 0)
409
410#define MXC_I2C_GET_BASE(i) \
411 ((i) == 0x0 ? MXC_BASE_I2C0_BUS0 : \
412 (i) == 0x1 ? MXC_BASE_I2C1_BUS0 : \
413 (i) == 0x2 ? MXC_BASE_I2C2_BUS0 : \
414 (i) == 0x8000 ? MXC_BASE_I2C0_BUS1 : \
415 (i) == 0x8001 ? MXC_BASE_I2C1_BUS1 : \
416 (i) == 0x8002 ? MXC_BASE_I2C2_BUS1 : \
417 0)
418
419#define MXC_I2C_GET_IDX(p) \
420 ((p) == MXC_I2C0_BUS0 ? 0x0 : \
421 (p) == MXC_I2C1_BUS0 ? 0x1 : \
422 (p) == MXC_I2C2_BUS0 ? 0x2 : \
423 (p) == MXC_I2C0_BUS1 ? 0x8000 : \
424 (p) == MXC_I2C1_BUS1 ? 0x8001 : \
425 (p) == MXC_I2C2_BUS1 ? 0x8002 : \
426 -1)
427
428#define MXC_I2C_GET_I2C(p) \
429 ((p) == 0x0 ? MXC_I2C0_BUS0 : \
430 (p) == 0x1 ? MXC_I2C1_BUS0 : \
431 (p) == 0x2 ? MXC_I2C2_BUS0 : \
432 (p) == 0x8000 ? MXC_I2C0_BUS1 : \
433 (p) == 0x8001 ? MXC_I2C1_BUS1 : \
434 (p) == 0x8002 ? MXC_I2C2_BUS1 : \
435 0)
436#define MXC_I2C_FIFO_DEPTH (8)
437
438/******************************************************************************/
439/* SPI Execute in Place */
440#define MXC_BASE_SPIXFM ((uint32_t)0x40026000UL)
441#define MXC_SPIXFM ((mxc_spixfm_regs_t *)MXC_BASE_SPIXFM)
442
443#define MXC_BASE_SPIXFC_FIFO ((uint32_t)0x400BC000UL)
444#define MXC_SPIXFC_FIFO ((mxc_spixfc_fifo_regs_t *)MXC_BASE_SPIXFC_FIFO)
445/******************************************************************************/
446/* SPI Execute in Place Master */
447
448#define MXC_CFG_SPIXFC_FIFO_DEPTH (16)
449
450#define MXC_BASE_SPIXFC ((uint32_t)0x40027000UL)
451#define MXC_SPIXFC ((mxc_spixfc_regs_t *)MXC_BASE_SPIXFC)
452
453/******************************************************************************/
454/* DMA */
455#define MXC_DMA_CHANNELS (16)
456#define MXC_DMA_INSTANCES (2)
457#define MXC_DMA_CH_OFFSET (8)
458
459#define MXC_BASE_DMA0 ((uint32_t)0x40028000UL)
460#define MXC_DMA0 ((mxc_dma_regs_t *)MXC_BASE_DMA0)
461#define MXC_BASE_DMA1 ((uint32_t)0x40035000UL)
462#define MXC_DMA1 ((mxc_dma_regs_t *)MXC_BASE_DMA1)
463
464#define MXC_DMA_GET_BASE(i) ((i) == 0 ? MXC_BASE_DMA0 : (i) == 1 ? MXC_BASE_DMA1 : 0)
465
466#define MXC_DMA_GET_DMA(i) ((i) == 0 ? MXC_DMA0 : (i) == 1 ? MXC_DMA1 : 0)
467
468#define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA0 ? 0 : (p) == MXC_DMA1 ? 1 : -1)
469
470#define MXC_DMA0_CH_GET_IRQ(i) \
471 ((IRQn_Type)(((i) == 0) ? DMA0_IRQn : \
472 ((i) == 1) ? DMA1_IRQn : \
473 ((i) == 2) ? DMA2_IRQn : \
474 ((i) == 3) ? DMA3_IRQn : \
475 ((i) == 4) ? DMA4_IRQn : \
476 ((i) == 5) ? DMA5_IRQn : \
477 ((i) == 6) ? DMA6_IRQn : \
478 ((i) == 7) ? DMA7_IRQn : \
479 0))
480
481#define MXC_DMA1_CH_GET_IRQ(i) \
482 ((IRQn_Type)(((i) == 0) ? DMA8_IRQn : \
483 ((i) == 1) ? DMA9_IRQn : \
484 ((i) == 2) ? DMA10_IRQn : \
485 ((i) == 3) ? DMA11_IRQn : \
486 ((i) == 4) ? DMA12_IRQn : \
487 ((i) == 5) ? DMA13_IRQn : \
488 ((i) == 6) ? DMA14_IRQn : \
489 ((i) == 7) ? DMA15_IRQn : \
490 0))
491
492#define MXC_DMA_CH_GET_IRQ(i) \
493 (((i) > (MXC_DMA_CH_OFFSET - 1)) ? MXC_DMA1_CH_GET_IRQ(i % MXC_DMA_CH_OFFSET) : \
494 MXC_DMA0_CH_GET_IRQ(i))
495
496/* Create alias for MXC_DMA0 for backwards compatibility with code that was
497 written for parts that only had one DMA instance. */
498#define MXC_DMA MXC_DMA0
499
500/******************************************************************************/
501/* FLC */
502#define MXC_FLC_INSTANCES (2)
503
504#define MXC_BASE_FLC0 ((uint32_t)0x40029000UL)
505#define MXC_FLC0 ((mxc_flc_regs_t *)MXC_BASE_FLC0)
506#define MXC_BASE_FLC1 ((uint32_t)0x40029400UL)
507#define MXC_FLC1 ((mxc_flc_regs_t *)MXC_BASE_FLC1)
508
509#define MXC_FLC_GET_IRQ(i) (IRQn_Type)((i) == 0 ? FLC0_IRQn : (i) == 1 ? FLC1_IRQn : 0)
510
511#define MXC_FLC_GET_BASE(i) ((i) == 0 ? MXC_BASE_FLC0 : (i) == 1 ? MXC_BASE_FLC1 : 0)
512
513#define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC0 : (i) == 1 ? MXC_FLC1 : 0)
514
515#define MXC_FLC_GET_IDX(p) ((p) == MXC_FLC0 ? 0 : (p) == MXC_FLC1 ? 1 : -1)
516
517/******************************************************************************/
518/* Instruction Cache */
519#define MXC_ICC_INSTANCES (2)
520
521#define MXC_BASE_ICC0 ((uint32_t)0x4002A000UL)
522#define MXC_ICC0 ((mxc_icc_regs_t *)MXC_BASE_ICC0)
523#define MXC_BASE_ICC1 ((uint32_t)0x4002A800UL)
524#define MXC_ICC1 ((mxc_icc_regs_t *)MXC_BASE_ICC1)
525
526#define MXC_ICC MXC_ICC0
527
528#define MXC_ICC_GET_BASE(i) ((i) == 0 ? MXC_BASE_ICC0 : (i) == 1 ? MXC_BASE_ICC1 : 0)
529
530#define MXC_ICC_GET_ICC(i) ((i) == 0 ? MXC_ICC0 : (i) == 1 ? MXC_ICC1 : 0)
531
532#define MXC_ICC_GET_IDX(p) ((p) == MXC_ICC0 ? 0 : (p) == MXC_ICC1 ? 1 : -1)
533
534/******************************************************************************/
535/* Instruction Cache XIP */
536#define MXC_BASE_SFCC ((uint32_t)0x4002F000UL)
537#define MXC_SFCC ((mxc_icc_regs_t *)MXC_BASE_SFCC)
538
539/******************************************************************************/
540/* Data Cache */
541#define MXC_BASE_SRCC ((uint32_t)0x40033000UL)
542#define MXC_SRCC ((mxc_srcc_regs_t *)MXC_BASE_SRCC)
543
544/******************************************************************************/
545/* ADC */
546#define MXC_BASE_ADC ((uint32_t)0x40034000UL)
547#define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC)
548#define MXC_ADC_MAX_CLOCK 8000000 // Maximum ADC clock in Hz
549
550/******************************************************************************/
551/* Smart DMA */
552#define MXC_BASE_SDMA ((uint32_t)0x40036000UL)
553#define MXC_SDMA ((mxc_sdma_regs_t *)MXC_BASE_SDMA)
554
555/******************************************************************************/
556/* SPI XIP Data */
557#define MXC_BASE_SPIXR ((uint32_t)0x4003A000UL)
558#define MXC_SPIXR ((mxc_spixr_regs_t *)MXC_BASE_SPIXR)
559
560/*******************************************************************************/
561/* Pulse Train Generation */
562#define MXC_CFG_PT_INSTANCES (16)
563
564#define MXC_BASE_PTG_BUS0 ((uint32_t)0x4003C000UL)
565#define MXC_PTG_BUS0 ((mxc_ptg_regs_t *)MXC_BASE_PTG_BUS0)
566#define MXC_BASE_PT0_BUS0 ((uint32_t)0x4003C020UL)
567#define MXC_PT0_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT0_BUS0)
568#define MXC_BASE_PT1_BUS0 ((uint32_t)0x4003C040UL)
569#define MXC_PT1_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT1_BUS0)
570#define MXC_BASE_PT2_BUS0 ((uint32_t)0x4003C060UL)
571#define MXC_PT2_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT2_BUS0)
572#define MXC_BASE_PT3_BUS0 ((uint32_t)0x4003C080UL)
573#define MXC_PT3_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT3_BUS0)
574#define MXC_BASE_PT4_BUS0 ((uint32_t)0x4003C0A0UL)
575#define MXC_PT4_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT4_BUS0)
576#define MXC_BASE_PT5_BUS0 ((uint32_t)0x4003C0C0UL)
577#define MXC_PT5_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT5_BUS0)
578#define MXC_BASE_PT6_BUS0 ((uint32_t)0x4003C0E0UL)
579#define MXC_PT6_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT6_BUS0)
580#define MXC_BASE_PT7_BUS0 ((uint32_t)0x4003C100UL)
581#define MXC_PT7_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT7_BUS0)
582#define MXC_BASE_PT8_BUS0 ((uint32_t)0x4003C120UL)
583#define MXC_PT8_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT8_BUS0)
584#define MXC_BASE_PT9_BUS0 ((uint32_t)0x4003C140UL)
585#define MXC_PT9_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT9_BUS0)
586#define MXC_BASE_PT10_BUS0 ((uint32_t)0x4003C160UL)
587#define MXC_PT10_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT10_BUS0)
588#define MXC_BASE_PT11_BUS0 ((uint32_t)0x4003C180UL)
589#define MXC_PT11_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT11_BUS0)
590#define MXC_BASE_PT12_BUS0 ((uint32_t)0x4003C1A0UL)
591#define MXC_PT12_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT12_BUS0)
592#define MXC_BASE_PT13_BUS0 ((uint32_t)0x4003C1C0UL)
593#define MXC_PT13_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT13_BUS0)
594#define MXC_BASE_PT14_BUS0 ((uint32_t)0x4003C1E0UL)
595#define MXC_PT14_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT14_BUS0)
596#define MXC_BASE_PT15_BUS0 ((uint32_t)0x4003C200UL)
597#define MXC_PT15_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT15_BUS0)
598
599#define MXC_BASE_PTG_BUS1 ((uint32_t)0x4013C000UL)
600#define MXC_PTG_BUS1 ((mxc_ptg_regs_t *)MXC_BASE_PTG_BUS1)
601#define MXC_BASE_PT0_BUS1 ((uint32_t)0x4013C020UL)
602#define MXC_PT0_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT0_BUS1)
603#define MXC_BASE_PT1_BUS1 ((uint32_t)0x4013C040UL)
604#define MXC_PT1_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT1_BUS1)
605#define MXC_BASE_PT2_BUS1 ((uint32_t)0x4013C060UL)
606#define MXC_PT2_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT2_BUS1)
607#define MXC_BASE_PT3_BUS1 ((uint32_t)0x4013C080UL)
608#define MXC_PT3_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT3_BUS1)
609#define MXC_BASE_PT4_BUS1 ((uint32_t)0x4013C0A0UL)
610#define MXC_PT4_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT4_BUS1)
611#define MXC_BASE_PT5_BUS1 ((uint32_t)0x4013C0C0UL)
612#define MXC_PT5_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT5_BUS1)
613#define MXC_BASE_PT6_BUS1 ((uint32_t)0x4013C0E0UL)
614#define MXC_PT6_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT6_BUS1)
615#define MXC_BASE_PT7_BUS1 ((uint32_t)0x4013C100UL)
616#define MXC_PT7_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT7_BUS1)
617#define MXC_BASE_PT8_BUS1 ((uint32_t)0x4013C120UL)
618#define MXC_PT8_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT8_BUS1)
619#define MXC_BASE_PT9_BUS1 ((uint32_t)0x4013C140UL)
620#define MXC_PT9_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT9_BUS1)
621#define MXC_BASE_PT10_BUS1 ((uint32_t)0x4013C160UL)
622#define MXC_PT10_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT10_BUS1)
623#define MXC_BASE_PT11_BUS1 ((uint32_t)0x4013C180UL)
624#define MXC_PT11_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT11_BUS1)
625#define MXC_BASE_PT12_BUS1 ((uint32_t)0x4013C1A0UL)
626#define MXC_PT12_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT12_BUS1)
627#define MXC_BASE_PT13_BUS1 ((uint32_t)0x4013C1C0UL)
628#define MXC_PT13_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT13_BUS1)
629#define MXC_BASE_PT14_BUS1 ((uint32_t)0x4013C1E0UL)
630#define MXC_PT14_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT14_BUS1)
631#define MXC_BASE_PT15_BUS1 ((uint32_t)0x4013C200UL)
632#define MXC_PT15_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT15_BUS1)
633
634#define MXC_PT_GET_BASE(i) \
635 ((i) == 0x0 ? MXC_BASE_PT0_BUS0 : \
636 (i) == 0x1 ? MXC_BASE_PT1_BUS0 : \
637 (i) == 0x2 ? MXC_BASE_PT2_BUS0 : \
638 (i) == 0x3 ? MXC_BASE_PT3_BUS0 : \
639 (i) == 0x4 ? MXC_BASE_PT4_BUS0 : \
640 (i) == 0x5 ? MXC_BASE_PT5_BUS0 : \
641 (i) == 0x6 ? MXC_BASE_PT6_BUS0 : \
642 (i) == 0x7 ? MXC_BASE_PT7_BUS0 : \
643 (i) == 0x8 ? MXC_BASE_PT8_BUS0 : \
644 (i) == 0x9 ? MXC_BASE_PT9_BUS0 : \
645 (i) == 0xA ? MXC_BASE_PT10_BUS0 : \
646 (i) == 0xB ? MXC_BASE_PT11_BUS0 : \
647 (i) == 0xC ? MXC_BASE_PT12_BUS0 : \
648 (i) == 0xD ? MXC_BASE_PT13_BUS0 : \
649 (i) == 0xE ? MXC_BASE_PT14_BUS0 : \
650 (i) == 0xF ? MXC_BASE_PT15_BUS0 : \
651 (i) == 0x8000 ? MXC_BASE_PT0_BUS1 : \
652 (i) == 0x8001 ? MXC_BASE_PT1_BUS1 : \
653 (i) == 0x8002 ? MXC_BASE_PT2_BUS1 : \
654 (i) == 0x8003 ? MXC_BASE_PT3_BUS1 : \
655 (i) == 0x8004 ? MXC_BASE_PT4_BUS1 : \
656 (i) == 0x8005 ? MXC_BASE_PT5_BUS1 : \
657 (i) == 0x8006 ? MXC_BASE_PT6_BUS1 : \
658 (i) == 0x8007 ? MXC_BASE_PT7_BUS1 : \
659 (i) == 0x8008 ? MXC_BASE_PT8_BUS1 : \
660 (i) == 0x8009 ? MXC_BASE_PT9_BUS1 : \
661 (i) == 0x800A ? MXC_BASE_PT10_BUS1 : \
662 (i) == 0x800B ? MXC_BASE_PT11_BUS1 : \
663 (i) == 0x800C ? MXC_BASE_PT12_BUS1 : \
664 (i) == 0x800D ? MXC_BASE_PT13_BUS1 : \
665 (i) == 0x800E ? MXC_BASE_PT14_BUS1 : \
666 (i) == 0x800F ? MXC_BASE_PT15_BUS1 : \
667 0)
668
669#define MXC_PT_GET_PT(i) \
670 ((i) == 0x0 ? MXC_PT0_BUS0 : \
671 (i) == 0x1 ? MXC_PT1_BUS0 : \
672 (i) == 0x2 ? MXC_PT2_BUS0 : \
673 (i) == 0x3 ? MXC_PT3_BUS0 : \
674 (i) == 0x4 ? MXC_PT4_BUS0 : \
675 (i) == 0x5 ? MXC_PT5_BUS0 : \
676 (i) == 0x6 ? MXC_PT6_BUS0 : \
677 (i) == 0x7 ? MXC_PT7_BUS0 : \
678 (i) == 0x8 ? MXC_PT8_BUS0 : \
679 (i) == 0x9 ? MXC_PT9_BUS0 : \
680 (i) == 0xA ? MXC_PT10_BUS0 : \
681 (i) == 0xB ? MXC_PT11_BUS0 : \
682 (i) == 0xC ? MXC_PT12_BUS0 : \
683 (i) == 0xD ? MXC_PT13_BUS0 : \
684 (i) == 0xE ? MXC_PT14_BUS0 : \
685 (i) == 0xF ? MXC_PT15_BUS0 : \
686 (i) == 0x8000 ? MXC_PT0_BUS1 : \
687 (i) == 0x8001 ? MXC_PT1_BUS1 : \
688 (i) == 0x8002 ? MXC_PT2_BUS1 : \
689 (i) == 0x8003 ? MXC_PT3_BUS1 : \
690 (i) == 0x8004 ? MXC_PT4_BUS1 : \
691 (i) == 0x8005 ? MXC_PT5_BUS1 : \
692 (i) == 0x8006 ? MXC_PT6_BUS1 : \
693 (i) == 0x8007 ? MXC_PT7_BUS1 : \
694 (i) == 0x8008 ? MXC_PT8_BUS1 : \
695 (i) == 0x8009 ? MXC_PT9_BUS1 : \
696 (i) == 0x800A ? MXC_PT10_BUS1 : \
697 (i) == 0x800B ? MXC_PT11_BUS1 : \
698 (i) == 0x800C ? MXC_PT12_BUS1 : \
699 (i) == 0x800D ? MXC_PT13_BUS1 : \
700 (i) == 0x800E ? MXC_PT14_BUS1 : \
701 (i) == 0x800F ? MXC_PT15_BUS1 : \
702 0)
703
704#define MXC_PT_GET_IDX(p) \
705 ((p) == MXC_PT0_BUS0 ? 0x0 : \
706 (p) == MXC_PT1_BUS0 ? 0x1 : \
707 (p) == MXC_PT2_BUS0 ? 0x2 : \
708 (p) == MXC_PT3_BUS0 ? 0x3 : \
709 (p) == MXC_PT4_BUS0 ? 0x4 : \
710 (p) == MXC_PT5_BUS0 ? 0x5 : \
711 (p) == MXC_PT6_BUS0 ? 0x6 : \
712 (p) == MXC_PT7_BUS0 ? 0x7 : \
713 (p) == MXC_PT8_BUS0 ? 0x8 : \
714 (p) == MXC_PT9_BUS0 ? 0x9 : \
715 (p) == MXC_PT10_BUS0 ? 0xA : \
716 (p) == MXC_PT11_BUS0 ? 0xB : \
717 (p) == MXC_PT12_BUS0 ? 0xC : \
718 (p) == MXC_PT13_BUS0 ? 0xD : \
719 (p) == MXC_PT14_BUS0 ? 0xE : \
720 (p) == MXC_PT15_BUS0 ? 0xF : \
721 (p) == MXC_PT0_BUS1 ? 0x8000 : \
722 (p) == MXC_PT1_BUS1 ? 0x8001 : \
723 (p) == MXC_PT2_BUS1 ? 0x8002 : \
724 (p) == MXC_PT3_BUS1 ? 0x8003 : \
725 (p) == MXC_PT4_BUS1 ? 0x8004 : \
726 (p) == MXC_PT5_BUS1 ? 0x8005 : \
727 (p) == MXC_PT6_BUS1 ? 0x8006 : \
728 (p) == MXC_PT7_BUS1 ? 0x8007 : \
729 (p) == MXC_PT8_BUS1 ? 0x8008 : \
730 (p) == MXC_PT9_BUS1 ? 0x8009 : \
731 (p) == MXC_PT10_BUS1 ? 0x800A : \
732 (p) == MXC_PT11_BUS1 ? 0x800B : \
733 (p) == MXC_PT12_BUS1 ? 0x800C : \
734 (p) == MXC_PT13_BUS1 ? 0x800D : \
735 (p) == MXC_PT14_BUS1 ? 0x800E : \
736 (p) == MXC_PT15_BUS1 ? 0x800F : \
737 -1)
738
739#define MXC_PT_GET_BUS(i) (((i)&0x00100000UL) >> 20)
740
741#define MXC_PTG_GET_PTG(i) \
742 (MXC_PT_GET_BUS((i)) == 0 ? MXC_PTG_BUS0 : MXC_PT_GET_BUS((i)) == 1 ? MXC_PTG_BUS1 : 0)
743
744/******************************************************************************/
745/* One Wire Master */
746#define MXC_BASE_OWM ((uint32_t)0x4003D000UL)
747#define MXC_OWM ((mxc_owm_regs_t *)MXC_BASE_OWM)
748
749/******************************************************************************/
750/* Semaphore */
751#define MXC_CFG_SEMA_INSTANCES (8)
752
753#define MXC_BASE_SEMA ((uint32_t)0x4003E000UL)
754#define MXC_SEMA ((mxc_sema_regs_t *)MXC_BASE_SEMA)
755
756/******************************************************************************/
757/* UART / Serial Port Interface */
758#define MXC_UART_INSTANCES (3)
759#define MXC_UART_FIFO_DEPTH (32)
760
761#define MXC_BASE_UART0 ((uint32_t)0x40042000UL)
762#define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0)
763#define MXC_BASE_UART1 ((uint32_t)0x40043000UL)
764#define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1)
765#define MXC_BASE_UART2 ((uint32_t)0x40044000UL)
766#define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2)
767
768#define MXC_UART_GET_IRQ(i) \
769 (IRQn_Type)((i) == 0 ? UART0_IRQn : \
770 (IRQn_Type)(i) == 1 ? UART1_IRQn : \
771 (IRQn_Type)(i) == 2 ? UART2_IRQn : \
772 0)
773
774#define MXC_UART_GET_BASE(i) \
775 ((i) == 0 ? MXC_BASE_UART0 : (i) == 1 ? MXC_BASE_UART1 : (i) == 2 ? MXC_BASE_UART2 : 0)
776
777#define MXC_UART_GET_UART(i) \
778 ((i) == 0 ? MXC_UART0 : (i) == 1 ? MXC_UART1 : (i) == 2 ? MXC_UART2 : 0)
779
780#define MXC_UART_GET_IDX(p) \
781 ((p) == MXC_UART0 ? 0 : (p) == MXC_UART1 ? 1 : (p) == MXC_UART2 ? 2 : -1)
782
783/******************************************************************************/
784/* SPI */
785#define MXC_SPI_INSTANCES (3)
786#define MXC_SPI_SS_INSTANCES (4)
787#define MXC_SPI_FIFO_DEPTH (32)
788
789#define MXC_BASE_SPI0 ((uint32_t)0x400BE000UL)
790#define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0)
791#define MXC_BASE_SPI1 ((uint32_t)0x40046000UL)
792#define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1)
793#define MXC_BASE_SPI2 ((uint32_t)0x40047000UL)
794#define MXC_SPI2 ((mxc_spi_regs_t *)MXC_BASE_SPI2)
795
796#define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : (p) == MXC_SPI1 ? 1 : (p) == MXC_SPI2 ? 2 : -1)
797
798#define MXC_SPI_GET_BASE(i) \
799 ((i) == 0 ? MXC_BASE_SPI0 : (i) == 1 ? MXC_BASE_SPI1 : (i) == 2 ? MXC_BASE_SPI2 : 0)
800
801#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : (i) == 1 ? MXC_SPI1 : (i) == 2 ? MXC_SPI2 : 0)
802
803#define MXC_SPI_GET_IRQ(i) \
804 (IRQn_Type)((i) == 0 ? SPI0_IRQn : (i) == 1 ? SPI1_IRQn : (i) == 2 ? SPI2_IRQn : 0)
805
806/******************************************************************************/
807/* TRNG */
808#define MXC_BASE_TRNG ((uint32_t)0x4004D000UL)
809#define MXC_TRNG ((mxc_trng_regs_t *)MXC_BASE_TRNG)
810
811/******************************************************************************/
812/* Audio Subsystem */
813#define MXC_BASE_AUDIO ((uint32_t)0x4004C000UL)
814#define MXC_AUDIO ((mxc_audio_regs_t *)MXC_BASE_AUDIO)
815
816/******************************************************************************/
817/* Bluetooth Low Energy */
818#define MXC_BASE_BTLE (0x40050000UL)
819#define MXC_BTLE ((mxc_btle_regs_t *)MXC_BASE_BTLE)
820#define MXC_BASE_BTLE_DBB_CTRL (MXC_BASE_BTLE + 0x1000)
821#define MXC_BASE_BTLE_DBB_TX (MXC_BASE_BTLE + 0x2000)
822#define MXC_BASE_BTLE_DBB_RX (MXC_BASE_BTLE + 0x3000)
823#define MXC_BASE_BTLE_DBB_EXT_RFFE (MXC_BASE_BTLE + 0x8000)
824
825// Base address definitions needed for DBB register definitions in BTLE stack
826#define DBB_CTRL_BASE MXC_BASE_BTLE_DBB_CTRL
827#define DBB_TX_BASE MXC_BASE_BTLE_DBB_TX
828#define DBB_RX_BASE MXC_BASE_BTLE_DBB_RX
829#define DBB_EXT_RFFE_BASE MXC_BASE_BTLE_DBB_EXT_RFFE
830
831/******************************************************************************/
832/* USB */
833#define MXC_BASE_USBHS ((uint32_t)0x400B1000UL)
834#define MXC_USBHS ((mxc_usbhs_regs_t *)MXC_BASE_USBHS)
835#define MXC_USBHS_NUM_EP 12 /* HW must have at least EP 0 CONTROL + 11 IN/OUT */
836#define MXC_USBHS_NUM_DMA 8 /* HW must have at least this many DMA channels */
837#define MXC_USBHS_MAX_PACKET 512
838
839/******************************************************************************/
840/* SDHC */
841#define MXC_BASE_SDHC ((uint32_t)0x400B6000UL)
842#define MXC_SDHC ((mxc_sdhc_regs_t *)MXC_BASE_SDHC)
843
844/******************************************************************************/
845/* Bit Shifting */
846#define MXC_F_BIT_0 (1 << 0)
847#define MXC_F_BIT_1 (1 << 1)
848#define MXC_F_BIT_2 (1 << 2)
849#define MXC_F_BIT_3 (1 << 3)
850#define MXC_F_BIT_4 (1 << 4)
851#define MXC_F_BIT_5 (1 << 5)
852#define MXC_F_BIT_6 (1 << 6)
853#define MXC_F_BIT_7 (1 << 7)
854#define MXC_F_BIT_8 (1 << 8)
855#define MXC_F_BIT_9 (1 << 9)
856#define MXC_F_BIT_10 (1 << 10)
857#define MXC_F_BIT_11 (1 << 11)
858#define MXC_F_BIT_12 (1 << 12)
859#define MXC_F_BIT_13 (1 << 13)
860#define MXC_F_BIT_14 (1 << 14)
861#define MXC_F_BIT_15 (1 << 15)
862#define MXC_F_BIT_16 (1 << 16)
863#define MXC_F_BIT_17 (1 << 17)
864#define MXC_F_BIT_18 (1 << 18)
865#define MXC_F_BIT_19 (1 << 19)
866#define MXC_F_BIT_20 (1 << 20)
867#define MXC_F_BIT_21 (1 << 21)
868#define MXC_F_BIT_22 (1 << 22)
869#define MXC_F_BIT_23 (1 << 23)
870#define MXC_F_BIT_24 (1 << 24)
871#define MXC_F_BIT_25 (1 << 25)
872#define MXC_F_BIT_26 (1 << 26)
873#define MXC_F_BIT_27 (1 << 27)
874#define MXC_F_BIT_28 (1 << 28)
875#define MXC_F_BIT_29 (1 << 29)
876#define MXC_F_BIT_30 (1 << 30)
877#define MXC_F_BIT_31 (1 << 31)
878
879/******************************************************************************/
880/* Bit Banding */
881#define BITBAND(reg, bit) \
882 ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg)&0x0fffffff) << 5) + \
883 ((bit) << 2))
884
885#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
886#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
887#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
888
889#define MXC_SETFIELD(reg, mask, setting) (reg = ((reg) & ~(mask)) | ((setting) & (mask)))
890
891/******************************************************************************/
892/* SCB CPACR */
893
894/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
895#define SCB_CPACR_CP10_Pos 20
896#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos)
897#define SCB_CPACR_CP11_Pos 22
898#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos)
900#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_MAX32665_H_