pwrseq_regs.h

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/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_PWRSEQ_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_PWRSEQ_REGS_H_
 
/* **** Includes **** */
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined (__ICCARM__)
  #pragma system_include
#endif
 
#if defined (__CC_ARM)
  #pragma anon_unions
#endif
/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif
#ifndef __R
#define __R  volatile const
#endif
 
/* **** Definitions **** */
 
typedef struct {
    __IO uint32_t lpcn;                 
    __IO uint32_t lpwkst0;              
    __IO uint32_t lpwken0;              
    __IO uint32_t lpwkst1;              
    __IO uint32_t lpwken1;              
    __R  uint32_t rsv_0x14_0x2f[7];
    __IO uint32_t lppwst;               
    __IO uint32_t lppwen;               
    __R  uint32_t rsv_0x38_0x3f[2];
    __IO uint32_t lpmemsd;              
    __IO uint32_t lpvddpd;              
    __IO uint32_t buretvec;             
    __IO uint32_t buaod;                
} mxc_pwrseq_regs_t;
 
/* Register offsets for module PWRSEQ */
#define MXC_R_PWRSEQ_LPCN                  ((uint32_t)0x00000000UL) 
#define MXC_R_PWRSEQ_LPWKST0               ((uint32_t)0x00000004UL) 
#define MXC_R_PWRSEQ_LPWKEN0               ((uint32_t)0x00000008UL) 
#define MXC_R_PWRSEQ_LPWKST1               ((uint32_t)0x0000000CUL) 
#define MXC_R_PWRSEQ_LPWKEN1               ((uint32_t)0x00000010UL) 
#define MXC_R_PWRSEQ_LPPWST                ((uint32_t)0x00000030UL) 
#define MXC_R_PWRSEQ_LPPWEN                ((uint32_t)0x00000034UL) 
#define MXC_R_PWRSEQ_LPMEMSD               ((uint32_t)0x00000040UL) 
#define MXC_R_PWRSEQ_LPVDDPD               ((uint32_t)0x00000044UL) 
#define MXC_R_PWRSEQ_BURETVEC              ((uint32_t)0x00000048UL) 
#define MXC_R_PWRSEQ_BUAOD                 ((uint32_t)0x0000004CUL) 
#define MXC_F_PWRSEQ_LPCN_RAMRET_POS                   0 
#define MXC_F_PWRSEQ_LPCN_RAMRET                       ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCN_RAMRET_POS)) 
#define MXC_V_PWRSEQ_LPCN_RAMRET_DIS                   ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_LPCN_RAMRET_DIS                   (MXC_V_PWRSEQ_LPCN_RAMRET_DIS << MXC_F_PWRSEQ_LPCN_RAMRET_POS) 
#define MXC_V_PWRSEQ_LPCN_RAMRET_EN1                   ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_LPCN_RAMRET_EN1                   (MXC_V_PWRSEQ_LPCN_RAMRET_EN1 << MXC_F_PWRSEQ_LPCN_RAMRET_POS) 
#define MXC_V_PWRSEQ_LPCN_RAMRET_EN2                   ((uint32_t)0x2UL) 
#define MXC_S_PWRSEQ_LPCN_RAMRET_EN2                   (MXC_V_PWRSEQ_LPCN_RAMRET_EN2 << MXC_F_PWRSEQ_LPCN_RAMRET_POS) 
#define MXC_V_PWRSEQ_LPCN_RAMRET_EN3                   ((uint32_t)0x3UL) 
#define MXC_S_PWRSEQ_LPCN_RAMRET_EN3                   (MXC_V_PWRSEQ_LPCN_RAMRET_EN3 << MXC_F_PWRSEQ_LPCN_RAMRET_POS) 
#define MXC_F_PWRSEQ_LPCN_BCKGRND_POS                  9 
#define MXC_F_PWRSEQ_LPCN_BCKGRND                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BCKGRND_POS)) 
#define MXC_F_PWRSEQ_LPCN_FWKM_POS                     10 
#define MXC_F_PWRSEQ_LPCN_FWKM                         ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FWKM_POS)) 
#define MXC_F_PWRSEQ_LPCN_BGOFF_POS                    11 
#define MXC_F_PWRSEQ_LPCN_BGOFF                        ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BGOFF_POS)) 
#define MXC_F_PWRSEQ_LPCN_VCOREMD_POS                  20 
#define MXC_F_PWRSEQ_LPCN_VCOREMD                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREMD_POS)) 
#define MXC_F_PWRSEQ_LPCN_VREGIMD_POS                  21 
#define MXC_F_PWRSEQ_LPCN_VREGIMD                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VREGIMD_POS)) 
#define MXC_F_PWRSEQ_LPCN_VDDAMD_POS                   22 
#define MXC_F_PWRSEQ_LPCN_VDDAMD                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDAMD_POS)) 
#define MXC_F_PWRSEQ_LPCN_VDDIOMD_POS                  23 
#define MXC_F_PWRSEQ_LPCN_VDDIOMD                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDIOMD_POS)) 
#define MXC_F_PWRSEQ_LPCN_VDDIOHMD_POS                 24 
#define MXC_F_PWRSEQ_LPCN_VDDIOHMD                     ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDIOHMD_POS)) 
#define MXC_F_PWRSEQ_LPCN_PORVDDIOMD_POS               25 
#define MXC_F_PWRSEQ_LPCN_PORVDDIOMD                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDIOMD_POS)) 
#define MXC_F_PWRSEQ_LPCN_PORVDDIOHMD_POS              26 
#define MXC_F_PWRSEQ_LPCN_PORVDDIOHMD                  ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDIOHMD_POS)) 
#define MXC_F_PWRSEQ_LPCN_VDDBMD_POS                   27 
#define MXC_F_PWRSEQ_LPCN_VDDBMD                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDBMD_POS)) 
#define MXC_F_PWRSEQ_LPCN_VRXOUTMD_POS                 28 
#define MXC_F_PWRSEQ_LPCN_VRXOUTMD                     ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VRXOUTMD_POS)) 
#define MXC_F_PWRSEQ_LPCN_VTXOUTMD_POS                 29 
#define MXC_F_PWRSEQ_LPCN_VTXOUTMD                     ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VTXOUTMD_POS)) 
#define MXC_F_PWRSEQ_LPCN_PDOWNDSLEN_POS               30 
#define MXC_F_PWRSEQ_LPCN_PDOWNDSLEN                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PDOWNDSLEN_POS)) 
#define MXC_F_PWRSEQ_LPWKST0_WAKEST_POS                0 
#define MXC_F_PWRSEQ_LPWKST0_WAKEST                    ((uint32_t)(0xFFFFFFFFUL << MXC_F_PWRSEQ_LPWKST0_WAKEST_POS)) 
#define MXC_F_PWRSEQ_LPWKEN0_WAKEEN_POS                0 
#define MXC_F_PWRSEQ_LPWKEN0_WAKEEN                    ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKEN0_WAKEEN_POS)) 
#define MXC_F_PWRSEQ_LPWKST1_WAKEST_POS                0 
#define MXC_F_PWRSEQ_LPWKST1_WAKEST                    ((uint32_t)(0x3FFFFUL << MXC_F_PWRSEQ_LPWKST1_WAKEST_POS)) 
#define MXC_F_PWRSEQ_LPWKEN1_WAKEEN_POS                0 
#define MXC_F_PWRSEQ_LPWKEN1_WAKEEN                    ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKEN1_WAKEEN_POS)) 
#define MXC_F_PWRSEQ_LPPWST_USBLSWKST_POS              0 
#define MXC_F_PWRSEQ_LPPWST_USBLSWKST                  ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPPWST_USBLSWKST_POS)) 
#define MXC_F_PWRSEQ_LPPWST_USBVBUSWKST_POS            2 
#define MXC_F_PWRSEQ_LPPWST_USBVBUSWKST                ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_USBVBUSWKST_POS)) 
#define MXC_F_PWRSEQ_LPPWST_SDMAWKST_POS               3 
#define MXC_F_PWRSEQ_LPPWST_SDMAWKST                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_SDMAWKST_POS)) 
#define MXC_F_PWRSEQ_LPPWST_AINCOMP0WKST_POS           4 
#define MXC_F_PWRSEQ_LPPWST_AINCOMP0WKST               ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP0WKST_POS)) 
#define MXC_F_PWRSEQ_LPPWST_AINCOMP1WKST_POS           5 
#define MXC_F_PWRSEQ_LPPWST_AINCOMP1WKST               ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP1WKST_POS)) 
#define MXC_F_PWRSEQ_LPPWST_AINCOMP2WKST_POS           6 
#define MXC_F_PWRSEQ_LPPWST_AINCOMP2WKST               ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP2WKST_POS)) 
#define MXC_F_PWRSEQ_LPPWST_AINCOMP3WKST_POS           7 
#define MXC_F_PWRSEQ_LPPWST_AINCOMP3WKST               ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP3WKST_POS)) 
#define MXC_F_PWRSEQ_LPPWST_AINCOMP0ST_POS             8 
#define MXC_F_PWRSEQ_LPPWST_AINCOMP0ST                 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP0ST_POS)) 
#define MXC_F_PWRSEQ_LPPWST_AINCOMP1ST_POS             9 
#define MXC_F_PWRSEQ_LPPWST_AINCOMP1ST                 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP1ST_POS)) 
#define MXC_F_PWRSEQ_LPPWST_AINCOMP2ST_POS             10 
#define MXC_F_PWRSEQ_LPPWST_AINCOMP2ST                 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP2ST_POS)) 
#define MXC_F_PWRSEQ_LPPWST_AINCOMP3ST_POS             11 
#define MXC_F_PWRSEQ_LPPWST_AINCOMP3ST                 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP3ST_POS)) 
#define MXC_F_PWRSEQ_LPPWST_BBMODEST_POS               16 
#define MXC_F_PWRSEQ_LPPWST_BBMODEST                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_BBMODEST_POS)) 
#define MXC_F_PWRSEQ_LPPWST_RSTWKST_POS                17 
#define MXC_F_PWRSEQ_LPPWST_RSTWKST                    ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_RSTWKST_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_USBLSWKEN_POS              0 
#define MXC_F_PWRSEQ_LPPWEN_USBLSWKEN                  ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPPWEN_USBLSWKEN_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_USBVBUSWKEN_POS            2 
#define MXC_F_PWRSEQ_LPPWEN_USBVBUSWKEN                ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_USBVBUSWKEN_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_SDMAWKEN_POS               3 
#define MXC_F_PWRSEQ_LPPWEN_SDMAWKEN                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_SDMAWKEN_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_AINCOMP0WKEN_POS           4 
#define MXC_F_PWRSEQ_LPPWEN_AINCOMP0WKEN               ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_AINCOMP0WKEN_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_AINCOMP1WKEN_POS           5 
#define MXC_F_PWRSEQ_LPPWEN_AINCOMP1WKEN               ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_AINCOMP1WKEN_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_AINCOMP2WKEN_POS           6 
#define MXC_F_PWRSEQ_LPPWEN_AINCOMP2WKEN               ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_AINCOMP2WKEN_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_AINCOMP3WKEN_POS           7 
#define MXC_F_PWRSEQ_LPPWEN_AINCOMP3WKEN               ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_AINCOMP3WKEN_POS)) 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM0SD_POS               0 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM0SD                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM0SD_POS)) 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM1SD_POS               1 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM1SD                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM1SD_POS)) 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM2SD_POS               2 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM2SD                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM2SD_POS)) 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM3SD_POS               3 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM3SD                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM3SD_POS)) 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM4SD_POS               4 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM4SD                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM4SD_POS)) 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM5SD_POS               5 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM5SD                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM5SD_POS)) 
#define MXC_F_PWRSEQ_LPMEMSD_ICACHESD_POS              7 
#define MXC_F_PWRSEQ_LPMEMSD_ICACHESD                  ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICACHESD_POS)) 
#define MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD_POS           8 
#define MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD               ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD_POS)) 
#define MXC_F_PWRSEQ_LPMEMSD_SRCCSD_POS                9 
#define MXC_F_PWRSEQ_LPMEMSD_SRCCSD                    ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRCCSD_POS)) 
#define MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD_POS              10 
#define MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD                  ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD_POS)) 
#define MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD_POS             11 
#define MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD                 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD_POS)) 
#define MXC_F_PWRSEQ_LPMEMSD_ROMSD_POS                 12 
#define MXC_F_PWRSEQ_LPMEMSD_ROMSD                     ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ROMSD_POS)) 
#define MXC_F_PWRSEQ_LPMEMSD_ROM1SD_POS                13 
#define MXC_F_PWRSEQ_LPMEMSD_ROM1SD                    ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ROM1SD_POS)) 
#define MXC_F_PWRSEQ_LPMEMSD_IC1SD_POS                 14 
#define MXC_F_PWRSEQ_LPMEMSD_IC1SD                     ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_IC1SD_POS)) 
#define MXC_F_PWRSEQ_LPVDDPD_VREGOBPD_POS              0 
#define MXC_F_PWRSEQ_LPVDDPD_VREGOBPD                  ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPVDDPD_VREGOBPD_POS)) 
#define MXC_F_PWRSEQ_LPVDDPD_VREGODPD_POS              1 
#define MXC_F_PWRSEQ_LPVDDPD_VREGODPD                  ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPVDDPD_VREGODPD_POS)) 
#define MXC_F_PWRSEQ_LPVDDPD_VDD2PD_POS                8 
#define MXC_F_PWRSEQ_LPVDDPD_VDD2PD                    ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPVDDPD_VDD2PD_POS)) 
#define MXC_F_PWRSEQ_LPVDDPD_VDD3PD_POS                9 
#define MXC_F_PWRSEQ_LPVDDPD_VDD3PD                    ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPVDDPD_VDD3PD_POS)) 
#define MXC_F_PWRSEQ_LPVDDPD_VDD4PD_POS                10 
#define MXC_F_PWRSEQ_LPVDDPD_VDD4PD                    ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPVDDPD_VDD4PD_POS)) 
#define MXC_F_PWRSEQ_LPVDDPD_VDD5PD_POS                11 
#define MXC_F_PWRSEQ_LPVDDPD_VDD5PD                    ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPVDDPD_VDD5PD_POS)) 
#define MXC_F_PWRSEQ_BURETVEC_GPR0_POS                 0 
#define MXC_F_PWRSEQ_BURETVEC_GPR0                     ((uint32_t)(0xFFFFFFFFUL << MXC_F_PWRSEQ_BURETVEC_GPR0_POS)) 
#define MXC_F_PWRSEQ_BUAOD_GPR1_POS                    0 
#define MXC_F_PWRSEQ_BUAOD_GPR1                        ((uint32_t)(0xFFFFFFFFUL << MXC_F_PWRSEQ_BUAOD_GPR1_POS)) 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_PWRSEQ_REGS_H_