MAX32670 Peripheral Driver API
Peripheral Driver API for the MAX32670
max32670.h
1/******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_MAX32670_H_
22#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_MAX32670_H_
23
24#ifndef TARGET_NUM
25#define TARGET_NUM 32670
26#endif
27
28#define MXC_NUMCORES 1
29
30#include <stdint.h>
31
32#ifndef FALSE
33#define FALSE (0)
34#endif
35
36#ifndef TRUE
37#define TRUE (1)
38#endif
39
40/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
41#if defined(__GNUC__)
42#ifndef __weak
43#define __weak __attribute__((weak))
44#endif
45
46#elif defined(__CC_ARM)
47
48#define inline __inline
49#pragma anon_unions
50
51#endif
52
53typedef enum {
54 NonMaskableInt_IRQn = -14,
55 HardFault_IRQn = -13,
56 MemoryManagement_IRQn = -12,
57 BusFault_IRQn = -11,
58 UsageFault_IRQn = -10,
59 SVCall_IRQn = -5,
60 DebugMonitor_IRQn = -4,
61 PendSV_IRQn = -2,
62 SysTick_IRQn = -1,
63
64 /* Device-specific interrupt sources (external to ARM core) */
65 /* table entry number */
66 /* |||| */
67 /* |||| table offset address */
68 /* vvvv vvvvvv */
69
70 PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */
71 WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */
72 RSV02_IRQn, /* 0x12 0x0048 18: Reserved */
73 RTC_IRQn, /* 0x13 0x004C 19: RTC */
74 TRNG_IRQn, /* 0x14 0x0050 20: True Random Number Generator */
75 TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */
76 TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */
77 TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */
78 TMR3_IRQn, /* 0x18 0x0060 24: Timer 3 */
79 TMR4_IRQn, /* 0x19 0x0064 25: Timer 4 */
80 TMR5_IRQn, /* 0x1A 0x0068 26: Timer 5 */
81 RSV11_IRQn, /* 0x1B 0x006C 27: Reserved */
82 RSV12_IRQn, /* 0x1C 0x0070 28: Reserved */
83 I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */
84 UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */
85 UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */
86 SPI0_IRQn, /* 0x20 0x0080 32: SPI0 */
87 SPI1_IRQn, /* 0x21 0x0084 33: SPI1 */
88 SPI2_IRQn, /* 0x22 0x0088 34: SPI2 */
89 RSV19_IRQn, /* 0x23 0x008C 35: Reserved */
90 RSV20_IRQn, /* 0x24 0x0090 36: Reserved */
91 RSV21_IRQn, /* 0x25 0x0094 37: Reserved */
92 RSV22_IRQn, /* 0x26 0x0098 38: Magstripe DSP */
93 FLC0_IRQn, /* 0x27 0x009C 39: Flash Controller 0 */
94 GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */
95 GPIO1_IRQn, /* 0x29 0x00A4 41: GPIO2 */
96 RSV26_IRQn, /* 0x2A 0x00A8 42: Reserved */
97 RSV27_IRQn, /* 0x2B 0x00AC 43: Reserved */
98 DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */
99 DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */
100 DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */
101 DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */
102 RSV32_IRQn, /* 0x30 0x00C0 48: Reserved */
103 RSV33_IRQn, /* 0x31 0x00C4 49: Reserved */
104 UART2_IRQn, /* 0x32 0x00C8 50: UART 2 */
105 RSV35_IRQn, /* 0x33 0x00CC 51: Contactless Link Control */
106 I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */
107 RSV37_IRQn, /* 0x35 0x00D4 53: Smart Card 1 */
108 RSV38_IRQn, /* 0x36 0x00D8 54: Reserved */
109 RSV39_IRQn, /* 0x37 0x00DC 55: Reserved */
110 RSV40_IRQn, /* 0x38 0x00E0 56: Reserved */
111 RSV41_IRQn, /* 0x39 0x00E4 57: Reserved */
112 RSV42_IRQn, /* 0x3A 0x00E8 58: Reserved */
113 RSV43_IRQn, /* 0x3B 0x00EC 59: Reserved */
114 RSV44_IRQn, /* 0x3C 0x00F0 60: Reserved */
115 RSV45_IRQn, /* 0x3D 0x00F4 61: Reserved */
116 RSV46_IRQn, /* 0x3E 0x00F8 62: Reserved */
117 RSV47_IRQn, /* 0x3F 0x00FC 63: Reserved */
118 RSV48_IRQn, /* 0x40 0x0100 64: Reserved */
119 RSV49_IRQn, /* 0x41 0x0104 65: Reserved */
120 RSV50_IRQn, /* 0x42 0x0108 66: Reserved */
121 RSV51_IRQn, /* 0x43 0x010C 67: Reserved */
122 RSV52_IRQn, /* 0x44 0x0110 68: Reserved */
123 RSV53_IRQn, /* 0x45 0x0114 69: Reserved */
124 GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIOWAKE */
125 RSV55_IRQn, /* 0x47 0x011C 71: Reserved */
126 RSV56_IRQn, /* 0x48 0x0120 72: Reserved */
127 WDT1_IRQn, /* 0x49 0x0124 73: Watchdog 1 */
128 RSV57_IRQn, /* 0x4A 0x0128 74: Reserved */
129 RSV58_IRQn, /* 0x4B 0x012C 75: Reserved */
130 RSV59_IRQn, /* 0x4C 0x0130 76: Reserved */
131 RSV61_IRQn, /* 0x4D 0x0134 77: Reserved */
132 I2C2_IRQn, /* 0x4E 0x0138 78: I2C 2 */
133 RSV63_IRQn, /* 0x4F 0x013C 79: Reserved */
134 RSV64_IRQn, /* 0x50 0x0140 80: Reserved */
135 RSV65_IRQn, /* 0x51 0x0144 81: Reserved */
136 RSV66_IRQn, /* 0x52 0x0148 82: Reserved */
137 RSV67_IRQn, /* 0x53 0x014C 83: One Wire Master */
138 DMA4_IRQn, /* 0x54 0x0150 84: DMA4 */
139 DMA5_IRQn, /* 0x55 0x0154 85: DMA5 */
140 DMA6_IRQn, /* 0x56 0x0158 86: DMA6 */
141 DMA7_IRQn, /* 0x57 0x015C 87: DMA7 */
142 RSV72_IRQn, /* 0x58 0x0160 88: Reserved */
143 RSV73_IRQn, /* 0x59 0x0164 89: Reserved */
144 RSV74_IRQn, /* 0x5A 0x0168 90: Reserved */
145 RSV75_IRQn, /* 0x5B 0x016C 91: Reserved */
146 RSV76_IRQn, /* 0x5C 0x0170 92: Reserved */
147 RSV77_IRQn, /* 0x5D 0x0174 93: Reserved */
148 RSV78_IRQn, /* 0x5E 0x0178 94: Reserved */
149 RSV79_IRQn, /* 0x5F 0x017C 95: Reserved */
150 RSV80_IRQn, /* 0x60 0x0180 96: Reserved */
151 RSV81_IRQn, /* 0x61 0x0184 97: Reserved */
152 ECC_IRQn, /* 0x62 0x0188 98: Error Correction */
153 RSV83_IRQn, /* 0x63 0x018C 99: Reserved */
154 RSV84_IRQn, /* 0x64 0x0190 100: Reserved */
155 RSV85_IRQn, /* 0x65 0x0194 101: Reserved */
156 RSV86_IRQn, /* 0x66 0x0198 102: Reserved */
157 RSV87_IRQn, /* 0x67 0x019C 103: Reserved */
158 UART3_IRQn, /* 0x68 0x01A0 104: UART 3 */
159 RSV89_IRQn, /* 0x69 0x01A4 105: Reserved */
160 RSV90_IRQn, /* 0x6A 0x01A8 106: Reserved */
161 RSV91_IRQn, /* 0x6B 0x01AC 107: Reserved */
162 RSV92_IRQn, /* 0x6C 0x01B0 108: Reserved */
163 RSV93_IRQn, /* 0x6D 0x01B4 109: Reserved */
164 RSV94_IRQn, /* 0x6E 0x01B8 110: Reserved */
165 RSV95_IRQn, /* 0x6F 0x01BC 111: Reserved */
166 RSV96_IRQn, /* 0x70 0x01C0 112: Reserved */
167 AES_IRQn, /* 0x71 0x01C4 113: AES */
168 CRC_IRQn, /* 0x72 0x01C8 114: CRC */
169 I2S_IRQn, /* 0x73 0x01CC 115: I2S */
170 MXC_IRQ_EXT_COUNT,
171} IRQn_Type;
172
173#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
174
175/* ================================================================================ */
176/* ================ Processor and Core Peripheral Section ================ */
177/* ================================================================================ */
178
179/* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */
180#define __CM4_REV 0x0100
181#define __MPU_PRESENT 1
182#define __NVIC_PRIO_BITS 3
183#define __Vendor_SysTickConfig 0
184#define __FPU_PRESENT 1
186#include <core_cm4.h>
187#include "system_max32670.h"
189/* ================================================================================ */
190/* ================== Device Specific Memory Section ================== */
191/* ================================================================================ */
192
193#define MXC_ROM_MEM_BASE 0x00000000UL
194#define MXC_ROM_MEM_SIZE 0x00020000UL
195#define MXC_XIP_MEM_BASE 0x08000000UL
196#define MXC_XIP_MEM_SIZE 0x08000000UL
197#define MXC_FLASH0_MEM_BASE 0x10000000UL
198#define MXC_FLASH_MEM_BASE MXC_FLASH0_MEM_BASE
199#define MXC_FLASH_PAGE_SIZE 0x00002000UL
200#define MXC_FLASH_MEM_SIZE (0x00060000UL - MXC_FLASH_PAGE_SIZE)
201// ^ Last page of flash is used by the bootloader and cannot be used by app code.
202// Furthermore, it appears that using this page will brick the device...
203#define MXC_INFO0_MEM_BASE 0x10800000UL
204#define MXC_INFO_MEM_BASE MXC_INFO0_MEM_BASE
205#define MXC_INFO_MEM_SIZE 0x00004000UL
206#define MXC_SRAM_MEM_BASE 0x20000000UL
207#define MXC_SRAM_MEM_SIZE 0x00028000UL
208#define MXC_XIP_DATA_MEM_BASE 0x80000000UL
209#define MXC_XIP_DATA_MEM_SIZE 0x20000000UL
210
211/* ================================================================================ */
212/* ================ Device Specific Peripheral Section ================ */
213/* ================================================================================ */
214
215/*
216 Base addresses and configuration settings for all MAX32670 peripheral modules.
217*/
218
219/******************************************************************************/
220/* Global control */
221#define MXC_BASE_GCR ((uint32_t)0x40000000UL)
222#define MXC_GCR ((mxc_gcr_regs_t *)MXC_BASE_GCR)
223
224/******************************************************************************/
225/* Non-battery backed SI Registers */
226#define MXC_BASE_SIR ((uint32_t)0x40000400UL)
227#define MXC_SIR ((mxc_sir_regs_t *)MXC_BASE_SIR)
228
229/******************************************************************************/
230/* Non-battery backed Function Control */
231#define MXC_BASE_FCR ((uint32_t)0x40000800UL)
232#define MXC_FCR ((mxc_fcr_regs_t *)MXC_BASE_FCR)
233
234/******************************************************************************/
235/* AES Keys */
236#define MXC_BASE_AESKEYS ((uint32_t)0x40005000UL)
237#define MXC_AESKEYS ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS)
238
239// DEPRECATED(1-10-2023): Scheduled for removal.
240#define MXC_BASE_AESKEY MXC_BASE_AESKEYS
241#define MXC_AESKEY ((mxc_aes_key_regs_t *)MXC_BASE_AESKEY)
242
243/******************************************************************************/
244/* Error Correcting Code */
245/* ECC registers is a subset of TRIMSIR registers */
246#define MXC_BASE_ECC ((uint32_t)0x40105400UL)
247#define MXC_ECC ((mxc_ecc_regs_t *)MXC_BASE_ECC)
248
249/******************************************************************************/
250/* Trim System Initalization Register */
251#define MXC_BASE_TRIMSIR ((uint32_t)0x400105400UL)
252#define MXC_TRIMSIR ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR)
253
254/******************************************************************************/
255/* Watchdog */
256#define MXC_BASE_WDT0 ((uint32_t)0x40003000UL)
257#define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
258#define MXC_BASE_WDT1 ((uint32_t)0x40003400UL)
259#define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1)
260
261/******************************************************************************/
262/* Real Time Clock */
263#define MXC_BASE_RTC ((uint32_t)0x40106000UL)
264#define MXC_RTC ((mxc_rtc_regs_t *)MXC_BASE_RTC)
265
266/******************************************************************************/
267/* Power Sequencer */
268#define MXC_BASE_PWRSEQ ((uint32_t)0x40106800UL)
269#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
270
271/******************************************************************************/
272/* MISC Control */
273#define MXC_BASE_MCR ((uint32_t)0x40106C00UL)
274#define MXC_MCR ((mxc_mcr_regs_t *)MXC_BASE_MCR)
275
276/******************************************************************************/
277/* AES */
278#define MXC_BASE_AES ((uint32_t)0x40007400UL)
279#define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES)
280
281/******************************************************************************/
282/* GPIO */
283#define MXC_CFG_GPIO_INSTANCES (2)
284#define MXC_CFG_GPIO_PINS_PORT (32)
285
286#define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL)
287#define MXC_GPIO0 ((mxc_gpio_regs_t *)MXC_BASE_GPIO0)
288#define MXC_BASE_GPIO1 ((uint32_t)0x40009000UL)
289#define MXC_GPIO1 ((mxc_gpio_regs_t *)MXC_BASE_GPIO1)
290
291#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : (p) == MXC_GPIO1 ? 1 : -1)
292
293#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : (i) == 1 ? MXC_GPIO1 : 0)
294
295#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : (i) == 1 ? GPIO1_IRQn : 0)
296
297/******************************************************************************/
298/* CRC */
299#define MXC_BASE_CRC ((uint32_t)0x4000F000UL)
300#define MXC_CRC ((mxc_crc_regs_t *)MXC_BASE_CRC)
301
302/******************************************************************************/
303/* Timer */
304#define SEC(s) (((uint32_t)s) * 1000000UL)
305#define MSEC(ms) (ms * 1000UL)
306#define USEC(us) (us)
307
308#define MXC_CFG_TMR_INSTANCES (6)
309
310#define MXC_BASE_TMR0 ((uint32_t)0x40010000UL)
311#define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0)
312#define MXC_BASE_TMR1 ((uint32_t)0x40011000UL)
313#define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1)
314#define MXC_BASE_TMR2 ((uint32_t)0x40012000UL)
315#define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2)
316#define MXC_BASE_TMR3 ((uint32_t)0x40013000UL)
317#define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3)
318#define MXC_BASE_TMR4 ((uint32_t)0x40114000UL)
319#define MXC_TMR4 ((mxc_tmr_regs_t *)MXC_BASE_TMR4)
320#define MXC_BASE_TMR5 ((uint32_t)0x40115000UL)
321#define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5)
322
323#define MXC_TMR_GET_IRQ(i) \
324 (IRQn_Type)((i) == 0 ? TMR0_IRQn : \
325 (i) == 1 ? TMR1_IRQn : \
326 (i) == 2 ? TMR2_IRQn : \
327 (i) == 3 ? TMR3_IRQn : \
328 (i) == 4 ? TMR4_IRQn : \
329 (i) == 5 ? TMR5_IRQn : \
330 0)
331
332#define MXC_TMR_GET_BASE(i) \
333 ((i) == 0 ? MXC_BASE_TMR0 : \
334 (i) == 1 ? MXC_BASE_TMR1 : \
335 (i) == 2 ? MXC_BASE_TMR2 : \
336 (i) == 3 ? MXC_BASE_TMR3 : \
337 (i) == 4 ? MXC_BASE_TMR4 : \
338 (i) == 5 ? MXC_BASE_TMR5 : \
339 0)
340
341#define MXC_TMR_GET_TMR(i) \
342 ((i) == 0 ? MXC_TMR0 : \
343 (i) == 1 ? MXC_TMR1 : \
344 (i) == 2 ? MXC_TMR2 : \
345 (i) == 3 ? MXC_TMR3 : \
346 (i) == 4 ? MXC_TMR4 : \
347 (i) == 5 ? MXC_TMR5 : \
348 0)
349
350#define MXC_TMR_GET_IDX(p) \
351 ((p) == MXC_TMR0 ? 0 : \
352 (p) == MXC_TMR1 ? 1 : \
353 (p) == MXC_TMR2 ? 2 : \
354 (p) == MXC_TMR3 ? 3 : \
355 (p) == MXC_TMR4 ? 4 : \
356 (p) == MXC_TMR5 ? 5 : \
357 -1)
358
359/******************************************************************************/
360/* I2C */
361#define MXC_I2C_INSTANCES (3)
362#define MXC_I2C_FIFO_DEPTH (8)
363#define MXC_I2C_NUM_TARGET_ADDR (4)
364
365#define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL)
366#define MXC_I2C0 ((mxc_i2c_regs_t *)MXC_BASE_I2C0)
367#define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL)
368#define MXC_I2C1 ((mxc_i2c_regs_t *)MXC_BASE_I2C1)
369#define MXC_BASE_I2C2 ((uint32_t)0x4001F000UL)
370#define MXC_I2C2 ((mxc_i2c_regs_t *)MXC_BASE_I2C2)
371
372#define MXC_I2C_GET_IRQ(i) \
373 (IRQn_Type)((i) == 0 ? I2C0_IRQn : (i) == 1 ? I2C1_IRQn : (i) == 2 ? I2C2_IRQn : 0)
374
375#define MXC_I2C_GET_BASE(i) \
376 ((i) == 0 ? MXC_BASE_I2C0 : (i) == 1 ? MXC_BASE_I2C1 : (i) == 2 ? MXC_BASE_I2C2 : 0)
377
378#define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : (i) == 1 ? MXC_I2C1 : (i) == 2 ? MXC_I2C2 : 0)
379
380#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : (p) == MXC_I2C1 ? 1 : (p) == MXC_I2C2 ? 2 : -1)
381
382/******************************************************************************/
383/* DMA */
384#define MXC_DMA_CHANNELS (8)
385#define MXC_DMA_INSTANCES (1)
386
387#define MXC_BASE_DMA ((uint32_t)0x40028000UL)
388#define MXC_DMA ((mxc_dma_regs_t *)MXC_BASE_DMA)
389
390#define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA ? 0 : -1)
391
392#define MXC_DMA_CH_GET_IRQ(i) \
393 ((IRQn_Type)(((i) == 0) ? DMA0_IRQn : \
394 ((i) == 1) ? DMA1_IRQn : \
395 ((i) == 2) ? DMA2_IRQn : \
396 ((i) == 3) ? DMA3_IRQn : \
397 ((i) == 4) ? DMA4_IRQn : \
398 ((i) == 5) ? DMA5_IRQn : \
399 ((i) == 6) ? DMA6_IRQn : \
400 ((i) == 7) ? DMA7_IRQn : \
401 0))
402
403/******************************************************************************/
404/* FLC */
405#define MXC_FLC_INSTANCES (1)
406
407#define MXC_BASE_FLC0 ((uint32_t)0x40029000UL)
408#define MXC_FLC0 ((mxc_flc_regs_t *)MXC_BASE_FLC0)
409
410#define MXC_FLC_GET_IRQ(i) (IRQn_Type)((i) == 0 ? FLC0_IRQn : 0)
411
412#define MXC_FLC_GET_BASE(i) ((i) == 0 ? MXC_BASE_FLC0 : 0)
413
414#define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC0 : 0)
415
416#define MXC_FLC_GET_IDX(p) ((p) == MXC_FLC0 ? 0 : -1)
417
418/******************************************************************************/
419/* Instruction Cache */
420#define MXC_BASE_ICC ((uint32_t)0x4002A000UL)
421#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC)
422
423/******************************************************************************/
424/* Data Cache */
425#define MXC_BASE_EMCC ((uint32_t)0x40033000UL)
426#define MXC_EMCC ((mxc_emcc_regs_t *)MXC_BASE_EMCC)
427
428/******************************************************************************/
429/* XXX Actually reserved! */
430#define MXC_BASE_RESERVED ((uint32_t)0x40035000UL)
431
432/******************************************************************************/
433/* One Wire Master */
434#define MXC_BASE_OWM ((uint32_t)0x4003D000UL)
435#define MXC_OWM ((mxc_owm_regs_t *)MXC_BASE_OWM)
436
437/******************************************************************************/
438/* UART / Serial Port Interface */
439#define MXC_UART_INSTANCES (4)
440#define MXC_UART_FIFO_DEPTH (8)
441
442#define MXC_BASE_UART0 ((uint32_t)0x40042000UL)
443#define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0)
444#define MXC_BASE_UART1 ((uint32_t)0x40043000UL)
445#define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1)
446#define MXC_BASE_UART2 ((uint32_t)0x40044000UL)
447#define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2)
448#define MXC_BASE_UART3 ((uint32_t)0x40145000UL)
449#define MXC_UART3 ((mxc_uart_regs_t *)MXC_BASE_UART3)
450
451#define MXC_UART_GET_IRQ(i) \
452 (IRQn_Type)((i) == 0 ? UART0_IRQn : \
453 (i) == 1 ? UART1_IRQn : \
454 (i) == 2 ? UART2_IRQn : \
455 (i) == 3 ? UART3_IRQn : \
456 0)
457
458#define MXC_UART_GET_BASE(i) \
459 ((i) == 0 ? MXC_BASE_UART0 : \
460 (i) == 1 ? MXC_BASE_UART1 : \
461 (i) == 2 ? MXC_BASE_UART2 : \
462 (i) == 3 ? MXC_BASE_UART3 : \
463 0)
464
465#define MXC_UART_GET_UART(i) \
466 ((i) == 0 ? MXC_UART0 : (i) == 1 ? MXC_UART1 : (i) == 2 ? MXC_UART2 : (i) == 3 ? MXC_UART3 : 0)
467
468#define MXC_UART_GET_IDX(p) \
469 ((p) == MXC_UART0 ? 0 : (p) == MXC_UART1 ? 1 : (p) == MXC_UART2 ? 2 : (p) == MXC_UART3 ? 3 : -1)
470
471/******************************************************************************/
472/* SPI */
473#define MXC_SPI_INSTANCES (3)
474#define MXC_SPI_SS_INSTANCES (4)
475#define MXC_SPI_FIFO_DEPTH (32)
476
477#define MXC_BASE_SPI0 ((uint32_t)0x40046000UL)
478#define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0)
479#define MXC_BASE_SPI1 ((uint32_t)0x40047000UL)
480#define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1)
481#define MXC_BASE_SPI2 ((uint32_t)0x40048000UL)
482#define MXC_SPI2 ((mxc_spi_regs_t *)MXC_BASE_SPI2)
483
484#define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : (p) == MXC_SPI1 ? 1 : (p) == MXC_SPI2 ? 2 : -1)
485
486#define MXC_SPI_GET_BASE(i) \
487 ((i) == 0 ? MXC_BASE_SPI0 : (i) == 1 ? MXC_BASE_SPI1 : (i) == 2 ? MXC_BASE_SPI2 : 0)
488
489#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : (i) == 1 ? MXC_SPI1 : (i) == 2 ? MXC_SPI2 : 0)
490
491#define MXC_SPI_GET_IRQ(i) \
492 (IRQn_Type)((i) == 0 ? SPI0_IRQn : (i) == 1 ? SPI1_IRQn : (i) == 2 ? SPI2_IRQn : 0)
493
494/******************************************************************************/
495/* TRNG */
496#define MXC_BASE_TRNG ((uint32_t)0x4004D000UL)
497#define MXC_TRNG ((mxc_trng_regs_t *)MXC_BASE_TRNG)
498
499/******************************************************************************/
500#define MXC_BASE_I2S ((uint32_t)0x40060000UL)
501#define MXC_I2S ((mxc_i2s_regs_t *)MXC_BASE_I2S)
502
503/******************************************************************************/
504/* Bit Shifting */
505#define MXC_F_BIT_0 (1 << 0)
506#define MXC_F_BIT_1 (1 << 1)
507#define MXC_F_BIT_2 (1 << 2)
508#define MXC_F_BIT_3 (1 << 3)
509#define MXC_F_BIT_4 (1 << 4)
510#define MXC_F_BIT_5 (1 << 5)
511#define MXC_F_BIT_6 (1 << 6)
512#define MXC_F_BIT_7 (1 << 7)
513#define MXC_F_BIT_8 (1 << 8)
514#define MXC_F_BIT_9 (1 << 9)
515#define MXC_F_BIT_10 (1 << 10)
516#define MXC_F_BIT_11 (1 << 11)
517#define MXC_F_BIT_12 (1 << 12)
518#define MXC_F_BIT_13 (1 << 13)
519#define MXC_F_BIT_14 (1 << 14)
520#define MXC_F_BIT_15 (1 << 15)
521#define MXC_F_BIT_16 (1 << 16)
522#define MXC_F_BIT_17 (1 << 17)
523#define MXC_F_BIT_18 (1 << 18)
524#define MXC_F_BIT_19 (1 << 19)
525#define MXC_F_BIT_20 (1 << 20)
526#define MXC_F_BIT_21 (1 << 21)
527#define MXC_F_BIT_22 (1 << 22)
528#define MXC_F_BIT_23 (1 << 23)
529#define MXC_F_BIT_24 (1 << 24)
530#define MXC_F_BIT_25 (1 << 25)
531#define MXC_F_BIT_26 (1 << 26)
532#define MXC_F_BIT_27 (1 << 27)
533#define MXC_F_BIT_28 (1 << 28)
534#define MXC_F_BIT_29 (1 << 29)
535#define MXC_F_BIT_30 (1 << 30)
536#define MXC_F_BIT_31 (1 << 31)
537
538/******************************************************************************/
539/* Bit Banding */
540
541#define BITBAND(reg, bit) \
542 ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg)&0x0fffffff) << 5) + \
543 ((bit) << 2))
544
545#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
546#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
547#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
548
549#define MXC_SETFIELD(reg, mask, setting) (reg = ((reg) & ~(mask)) | ((setting) & (mask)))
550
551/******************************************************************************/
552/* SCB CPACR */
553
554/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
555#define SCB_CPACR_CP10_Pos 20
556#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos)
557#define SCB_CPACR_CP11_Pos 22
558#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos)
560#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_MAX32670_H_