MAX32672 Peripheral Driver API
Peripheral Driver API for the MAX32672
max32672.h
1/******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_MAX32672_H_
22#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_MAX32672_H_
23
24#ifndef TARGET_NUM
25#define TARGET_NUM 32672
26#endif
27
28#define MXC_NUMCORES 1
29
30#include <stdint.h>
31
32// TODO(ADI): Remove below after grace period. Temporarily added these includes to resolve errors
33// for grace period before eventually removing support for deprecated features. 10-24-2022
34//>>>
35#include "trimsir_regs.h"
36#include "aes_regs.h"
37//<<<
38
39#ifndef FALSE
40#define FALSE (0)
41#endif
42
43#ifndef TRUE
44#define TRUE (1)
45#endif
46
47/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
48#if defined(__GNUC__)
49#ifndef __weak
50#define __weak __attribute__((weak))
51#endif
52
53#elif defined(__CC_ARM)
54
55#define inline __inline
56#pragma anon_unions
57
58#endif
59
60typedef enum {
61 NonMaskableInt_IRQn = -14,
62 HardFault_IRQn = -13,
63 MemoryManagement_IRQn = -12,
64 BusFault_IRQn = -11,
65 UsageFault_IRQn = -10,
66 SVCall_IRQn = -5,
67 DebugMonitor_IRQn = -4,
68 PendSV_IRQn = -2,
69 SysTick_IRQn = -1,
70
71 /* Device-specific interrupt sources (external to ARM core) */
72 /* table entry number */
73 /* |||| */
74 /* |||| table offset address */
75 /* vvvv vvvvvv */
76
77 PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */
78 WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */
79 RSV02_IRQn, /* 0x12 0x0048 18: Reserved */
80 RTC_IRQn, /* 0x13 0x004C 19: RTC */
81 TRNG_IRQn, /* 0x14 0x0050 20: True Random Number Generator */
82 TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */
83 TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */
84 TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */
85 TMR3_IRQn, /* 0x18 0x0060 24: Timer 3 */
86 TMR4_IRQn, /* 0x19 0x0064 25: Timer 4 */
87 TMR5_IRQn, /* 0x1A 0x0068 26: Timer 5 */
88 RSV11_IRQn, /* 0x1B 0x006C 27: Reserved */
89 RSV12_IRQn, /* 0x1C 0x0070 28: Reserved */
90 I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */
91 UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */
92 UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */
93 SPI0_IRQn, /* 0x20 0x0080 32: SPI0 */
94 SPI1_IRQn, /* 0x21 0x0084 33: SPI1 */
95 SPI2_IRQn, /* 0x22 0x0088 34: SPI2 */
96 RSV19_IRQn, /* 0x23 0x008C 35: Reserved */
97 ADC_IRQn, /* 0x24 0x0090 36: ADC */
98 RSV21_IRQn, /* 0x25 0x0094 37: Reserved */
99 RSV22_IRQn, /* 0x26 0x0098 38: Magstripe DSP */
100 FLC0_IRQn, /* 0x27 0x009C 39: Flash Controller 0 */
101 GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */
102 GPIO1_IRQn, /* 0x29 0x00A4 41: GPIO1 */
103 RSV26_IRQn, /* 0x2A 0x00A8 42: Reserved */
104 CRYPTO_IRQn, /* 0x2B 0x00AC 43: Crypto */
105 DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */
106 DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */
107 DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */
108 DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */
109 RSV32_IRQn, /* 0x30 0x00C0 48: Reserved */
110 RSV33_IRQn, /* 0x31 0x00C4 49: Reserved */
111 UART2_IRQn, /* 0x32 0x00C8 50: UART 2 */
112 RSV35_IRQn, /* 0x33 0x00CC 51: Contactless Link Control */
113 I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */
114 RSV37_IRQn, /* 0x35 0x00D4 53: Smart Card 1 */
115 RSV38_IRQn, /* 0x36 0x00D8 54: Reserved */
116 RSV39_IRQn, /* 0x37 0x00DC 55: Reserved */
117 RSV40_IRQn, /* 0x38 0x00E0 56: Reserved */
118 RSV41_IRQn, /* 0x39 0x00E4 57: Reserved */
119 RSV42_IRQn, /* 0x3A 0x00E8 58: Reserved */
120 RSV43_IRQn, /* 0x3B 0x00EC 59: Reserved */
121 RSV44_IRQn, /* 0x3C 0x00F0 60: Reserved */
122 RSV45_IRQn, /* 0x3D 0x00F4 61: Reserved */
123 RSV46_IRQn, /* 0x3E 0x00F8 62: Reserved */
124 RSV47_IRQn, /* 0x3F 0x00FC 63: Reserved */
125 RSV48_IRQn, /* 0x40 0x0100 64: Reserved */
126 RSV49_IRQn, /* 0x41 0x0104 65: Reserved */
127 RSV50_IRQn, /* 0x42 0x0108 66: Reserved */
128 RSV51_IRQn, /* 0x43 0x010C 67: Reserved */
129 RSV52_IRQn, /* 0x44 0x0110 68: Reserved */
130 RSV53_IRQn, /* 0x45 0x0114 69: Reserved */
131 GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIO Wakeup */
132 RSV55_IRQn, /* 0x47 0x011C 71: Reserved */
133 RSV56_IRQn, /* 0x48 0x0120 72: Reserved */
134 WDT1_IRQn, /* 0x49 0x0124 73: Watchdog 1 */
135 RSV58_IRQn, /* 0x4A 0x0128 74: Reserved */
136 RSV59_IRQn, /* 0x4B 0x012C 75: Reserved */
137 RSV60_IRQn, /* 0x4C 0x0130 76: Reserved */
138 RSV61_IRQn, /* 0x4D 0x0134 77: Reserved */
139 I2C2_IRQn, /* 0x4E 0x0138 78: I2C 2 */
140 RSV63_IRQn, /* 0x4F 0x013C 79: Reserved */
141 RSV64_IRQn, /* 0x50 0x0140 80: Reserved */
142 RSV65_IRQn, /* 0x51 0x0144 81: Reserved */
143 RSV66_IRQn, /* 0x52 0x0148 82: Reserved */
144 RSV67_IRQn, /* 0x53 0x014C 83: One Wire Master */
145 DMA4_IRQn, /* 0x54 0x0150 84: DMA4 */
146 DMA5_IRQn, /* 0x55 0x0154 85: DMA5 */
147 DMA6_IRQn, /* 0x56 0x0158 86: DMA6 */
148 DMA7_IRQn, /* 0x57 0x015C 87: DMA7 */
149 DMA8_IRQn, /* 0x58 0x0160 88: DMA8 */
150 DMA9_IRQn, /* 0x59 0x0164 89: DMA9 */
151 DMA10_IRQn, /* 0x5A 0x0168 90: DMA10 */
152 DMA11_IRQn, /* 0x5B 0x016C 91: DMA11 */
153 RSV76_IRQn, /* 0x5C 0x0170 92: Reserved */
154 RSV77_IRQn, /* 0x5D 0x0174 93: Reserved */
155 RSV78_IRQn, /* 0x5E 0x0178 94: Reserved */
156 RSV79_IRQn, /* 0x5F 0x017C 95: Reserved */
157 RSV80_IRQn, /* 0x60 0x0180 96: Reserved */
158 RSV81_IRQn, /* 0x61 0x0184 97: Reserved */
159 ECC_IRQn, /* 0x62 0x0188 98: Error Correction */
160 RSV83_IRQn, /* 0x63 0x018C 99: Reserved */
161 RSV84_IRQn, /* 0x64 0x0190 100: Reserved */
162 SCA_IRQn, /* 0x65 0x0194 101: Crypto Accelerator */
163 RSV86_IRQn, /* 0x66 0x0198 102: Reserved */
164 FLC1_IRQn, /* 0x67 0x019C 103: Flash Controller 1 */
165 UART3_IRQn, /* 0x68 0x01A0 104: UART 3 */
166 RSV89_IRQn, /* 0x69 0x01A4 105: Reserved */
167 RSV90_IRQn, /* 0x6A 0x01A8 106: Reserved */
168 RSV91_IRQn, /* 0x6B 0x01AC 107: Reserved */
169 RSV92_IRQn, /* 0x6C 0x01B0 108: Reserved */
170 RSV93_IRQn, /* 0x6D 0x01B4 109: Reserved */
171 RSV94_IRQn, /* 0x6E 0x01B8 110: Reserved */
172 RSV95_IRQn, /* 0x6F 0x01BC 111: Reserved */
173 RSV96_IRQn, /* 0x70 0x01C0 112: Reserved */
174 AES_IRQn, /* 0x71 0x01C4 113: AES */
175 RSV98_IRQn, /* 0x72 0x01C8 114: Reserved */
176 I2S_IRQn, /* 0x73 0x01CC 115: Reserved */
177 RSV100_IRQn, /* 0x74 0x01D0 116: Reserved */
178 RSV101_IRQn, /* 0x75 0x01D4 117: Reserved */
179 RSV102_IRQn, /* 0x76 0x01D8 118: Reserved */
180 RSV103_IRQn, /* 0x77 0x01DC 119: Reserved */
181 RSV104_IRQn, /* 0x78 0x01E0 120: Reserved */
182 RSV105_IRQn, /* 0x79 0x01E4 121: Reserved */
183 QDEC_IRQn, /* 0x7A 0x01E8 122: Quadrature Decoder Interface */
184 RSV107_IRQn, /* 0x7B 0x01EC 123: Reserved */
185 MXC_IRQ_EXT_COUNT,
186} IRQn_Type;
187
188#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
189
190/* ================================================================================ */
191/* ================ Processor and Core Peripheral Section ================ */
192/* ================================================================================ */
193
194/* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */
195#define __CM4_REV 0x0100
196#define __MPU_PRESENT 1
197#define __NVIC_PRIO_BITS 3
198#define __Vendor_SysTickConfig 0
199#define __FPU_PRESENT 1
201#include <core_cm4.h>
202#include "system_max32672.h"
204/* ================================================================================ */
205/* ================== Device Specific Memory Section ================== */
206/* ================================================================================ */
207
208#define MXC_ROM_MEM_BASE 0x00000000UL
209#define MXC_ROM_MEM_SIZE 0x00020000UL
210#define MXC_XIP_MEM_BASE 0x08000000UL
211#define MXC_XIP_MEM_SIZE 0x08000000UL
212#define MXC_FLASH0_MEM_BASE 0x10000000UL
213#define MXC_FLASH1_MEM_BASE 0x10080000UL
214#define MXC_FLASH_MEM_BASE MXC_FLASH0_MEM_BASE
215#define MXC_FLASH_PAGE_SIZE 0x00002000UL
216#define MXC_FLASH_MEM_SIZE 0x00080000UL
217#define MXC_INFO0_MEM_BASE 0x10800000UL
218#define MXC_INFO1_MEM_BASE 0x10802000UL
219#define MXC_INFO_MEM_BASE MXC_INFO0_MEM_BASE
220#define MXC_INFO_MEM_SIZE 0x00002000UL
221#define MXC_SRAM_MEM_BASE 0x20000000UL
222#define MXC_SRAM_MEM_SIZE 0x00032000UL
223#define MXC_XIP_DATA_MEM_BASE 0x80000000UL
224#define MXC_XIP_DATA_MEM_SIZE 0x20000000UL
225
226/* ================================================================================ */
227/* ================ Device Specific Peripheral Section ================ */
228/* ================================================================================ */
229
230/*
231 Base addresses and configuration settings for all MAX32672 peripheral modules.
232*/
233
234/******************************************************************************/
235/* Global control */
236#define MXC_BASE_GCR ((uint32_t)0x40000000UL)
237#define MXC_GCR ((mxc_gcr_regs_t *)MXC_BASE_GCR)
238
239/******************************************************************************/
240/* Non-battery backed SI Registers */
241#define MXC_BASE_SIR ((uint32_t)0x40000400UL)
242#define MXC_SIR ((mxc_sir_regs_t *)MXC_BASE_SIR)
243
244/******************************************************************************/
245/* Non-battery backed Function Control */
246#define MXC_BASE_FCR ((uint32_t)0x40000800UL)
247#define MXC_FCR ((mxc_fcr_regs_t *)MXC_BASE_FCR)
248
249/******************************************************************************/
250/* Crypto Toolbox */
251#define MXC_BASE_CTB ((uint32_t)0x40001000UL)
252#define MXC_CTB ((mxc_ctb_regs_t *)MXC_BASE_CTB)
253
254/******************************************************************************/
255/* Trim System Initalization Register */
256#define MXC_BASE_TRIMSIR ((uint32_t)0x40105400UL)
257#define MXC_TRIMSIR ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR)
258
259// DEPRECATED(10-24-2022): Scheduled for removal.
260#define MXC_ECC ((mxc_ecc_regs_t *)MXC_BASE_TRIMSIR)
261
262/******************************************************************************/
263/* Watchdog */
264#define MXC_BASE_WDT0 ((uint32_t)0x40003000UL)
265#define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
266#define MXC_BASE_WDT1 ((uint32_t)0x40003400UL)
267#define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1)
268
269/******************************************************************************/
270/* System and User AES Keys */
271#define MXC_BASE_SYS_AESKEYS ((uint32_t)0x40205000UL)
272#define MXC_SYS_AESKEYS ((mxc_sys_aeskeys_regs_t *)MXC_BASE_SYS_AESKEYS)
273
274#define MXC_BASE_USR_AESKEYS ((uint32_t)0x40005000UL)
275#define MXC_USR_AESKEYS ((mxc_usr_aeskeys_regs_t *)MXC_BASE_USR_AESKEYS)
276
277/*
278 * @deprecated (1-10-2023): Scheduled for removal. Use MXC_BASE_SYS_AESKEYS instead.
279 */
280#define MXC_BASE_AESKEY MXC_BASE_SYS_AESKEYS
281
282/*
283 * @deprecated (1-10-2023): Scheduled for removal. Use MXC_SYS_AESKEYS instead.
284 */
285#define MXC_AESKEY ((mxc_aes_key_regs_t *)MXC_BASE_SYS_AESKEY)
286
287/*
288 * @deprecated (4-7-2023): Scheduled for removal. Use MXC_BASE_SYS_AESKEYS instead.
289 */
290#define MXC_BASE_AESKEYS MXC_BASE_SYS_AESKEYS
291
292/*
293 * @deprecated (4-7-2023): Scheduled for removal. Use MXC_SYS_AESKEYS instead.
294 */
295#define MXC_AESKEYS MXC_SYS_AESKEYS
296
297/******************************************************************************/
298/* Real Time Clock */
299#define MXC_BASE_RTC ((uint32_t)0x40106000UL)
300#define MXC_RTC ((mxc_rtc_regs_t *)MXC_BASE_RTC)
301
302/******************************************************************************/
303/* Power Sequencer */
304#define MXC_BASE_PWRSEQ ((uint32_t)0x40106800UL)
305#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
306
307/******************************************************************************/
308/* MISC Control */
309#define MXC_BASE_MCR ((uint32_t)0x40106C00UL)
310#define MXC_MCR ((mxc_mcr_regs_t *)MXC_BASE_MCR)
311
312/******************************************************************************/
313/* AES */
314#define MXC_BASE_AES ((uint32_t)0x40207400UL)
315#define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES)
316
317// DEPRECATED(10-24-2022): Scheduled for removal.
318typedef __attribute__((deprecated(
319 "Use MXC_AES (mxc_aes_regs_t), not the deprecated MXC_SYS_AES (mxc_sys_aes_regs_t) instance name and struct. 10-24-2022")))
320mxc_aes_regs_t mxc_sys_aes_regs_t;
321#define MXC_SYS_AES ((mxc_sys_aes_regs_t *)MXC_BASE_AES)
322
323/******************************************************************************/
324/* GPIO */
325#define MXC_CFG_GPIO_INSTANCES (3)
326#define MXC_CFG_GPIO_PINS_PORT (32)
327
328#define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL)
329#define MXC_GPIO0 ((mxc_gpio_regs_t *)MXC_BASE_GPIO0)
330#define MXC_BASE_GPIO1 ((uint32_t)0x40009000UL)
331#define MXC_GPIO1 ((mxc_gpio_regs_t *)MXC_BASE_GPIO1)
332
333#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : (p) == MXC_GPIO1 ? 1 : -1)
334
335#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : (i) == 1 ? MXC_GPIO1 : 0)
336
337#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : (i) == 1 ? GPIO1_IRQn : 0)
338
339/******************************************************************************/
340/* CRC */
341#define MXC_BASE_CRC ((uint32_t)0x4000F000UL)
342#define MXC_CRC ((mxc_crc_regs_t *)MXC_BASE_CRC)
343
344/******************************************************************************/
345/* Timer */
346#define SEC(s) (((uint32_t)s) * 1000000UL)
347#define MSEC(ms) (ms * 1000UL)
348#define USEC(us) (us)
349
350#define MXC_CFG_TMR_INSTANCES (6)
351
352#define MXC_BASE_TMR0 ((uint32_t)0x40010000UL)
353#define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0)
354#define MXC_BASE_TMR1 ((uint32_t)0x40011000UL)
355#define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1)
356#define MXC_BASE_TMR2 ((uint32_t)0x40012000UL)
357#define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2)
358#define MXC_BASE_TMR3 ((uint32_t)0x40013000UL)
359#define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3)
360#define MXC_BASE_TMR4 ((uint32_t)0x40114000UL)
361#define MXC_TMR4 ((mxc_tmr_regs_t *)MXC_BASE_TMR4)
362#define MXC_BASE_TMR5 ((uint32_t)0x40115000UL)
363#define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5)
364
365#define MXC_TMR_GET_IRQ(i) \
366 (IRQn_Type)((i) == 0 ? TMR0_IRQn : \
367 (i) == 1 ? TMR1_IRQn : \
368 (i) == 2 ? TMR2_IRQn : \
369 (i) == 3 ? TMR3_IRQn : \
370 (i) == 4 ? TMR4_IRQn : \
371 (i) == 5 ? TMR5_IRQn : \
372 0)
373
374#define MXC_TMR_GET_BASE(i) \
375 ((i) == 0 ? MXC_BASE_TMR0 : \
376 (i) == 1 ? MXC_BASE_TMR1 : \
377 (i) == 2 ? MXC_BASE_TMR2 : \
378 (i) == 3 ? MXC_BASE_TMR3 : \
379 (i) == 4 ? MXC_BASE_TMR4 : \
380 (i) == 5 ? MXC_BASE_TMR5 : \
381 0)
382
383#define MXC_TMR_GET_TMR(i) \
384 ((i) == 0 ? MXC_TMR0 : \
385 (i) == 1 ? MXC_TMR1 : \
386 (i) == 2 ? MXC_TMR2 : \
387 (i) == 3 ? MXC_TMR3 : \
388 (i) == 4 ? MXC_TMR4 : \
389 (i) == 5 ? MXC_TMR5 : \
390 0)
391
392#define MXC_TMR_GET_IDX(p) \
393 ((p) == MXC_TMR0 ? 0 : \
394 (p) == MXC_TMR1 ? 1 : \
395 (p) == MXC_TMR2 ? 2 : \
396 (p) == MXC_TMR3 ? 3 : \
397 (p) == MXC_TMR4 ? 4 : \
398 (p) == MXC_TMR5 ? 5 : \
399 -1)
400
401/******************************************************************************/
402/* I2C */
403#define MXC_I2C_INSTANCES (3)
404#define MXC_I2C_NUM_TARGET_ADDR (4)
405#define MXC_I2C_FIFO_DEPTH (8)
406
407#define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL)
408#define MXC_I2C0 ((mxc_i2c_regs_t *)MXC_BASE_I2C0)
409#define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL)
410#define MXC_I2C1 ((mxc_i2c_regs_t *)MXC_BASE_I2C1)
411#define MXC_BASE_I2C2 ((uint32_t)0x4001F000UL)
412#define MXC_I2C2 ((mxc_i2c_regs_t *)MXC_BASE_I2C2)
413
414#define MXC_I2C_GET_IRQ(i) \
415 (IRQn_Type)((i) == 0 ? I2C0_IRQn : (i) == 1 ? I2C1_IRQn : (i) == 2 ? I2C2_IRQn : 0)
416
417#define MXC_I2C_GET_BASE(i) \
418 ((i) == 0 ? MXC_BASE_I2C0 : (i) == 1 ? MXC_BASE_I2C1 : (i) == 2 ? MXC_BASE_I2C2 : 0)
419
420#define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : (i) == 1 ? MXC_I2C1 : (i) == 2 ? MXC_I2C2 : 0)
421
422#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : (p) == MXC_I2C1 ? 1 : (p) == MXC_I2C2 ? 2 : -1)
423
424/******************************************************************************/
425/* DMA */
426#define MXC_DMA_CHANNELS (12)
427#define MXC_DMA_INSTANCES (1)
428
429#define MXC_BASE_DMA ((uint32_t)0x40028000UL)
430#define MXC_DMA ((mxc_dma_regs_t *)MXC_BASE_DMA)
431
432#define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA ? 0 : -1)
433
434#define MXC_DMA_CH_GET_IRQ(i) \
435 ((IRQn_Type)(((i) == 0) ? DMA0_IRQn : \
436 ((i) == 1) ? DMA1_IRQn : \
437 ((i) == 2) ? DMA2_IRQn : \
438 ((i) == 3) ? DMA3_IRQn : \
439 ((i) == 4) ? DMA4_IRQn : \
440 ((i) == 5) ? DMA5_IRQn : \
441 ((i) == 6) ? DMA6_IRQn : \
442 ((i) == 7) ? DMA7_IRQn : \
443 ((i) == 8) ? DMA8_IRQn : \
444 ((i) == 9) ? DMA9_IRQn : \
445 ((i) == 10) ? DMA10_IRQn : \
446 ((i) == 11) ? DMA11_IRQn : \
447 0))
448
449/******************************************************************************/
450/* FLC */
451#define MXC_FLC_INSTANCES (2)
452
453#define MXC_BASE_FLC0 ((uint32_t)0x40029000UL)
454#define MXC_FLC0 ((mxc_flc_regs_t *)MXC_BASE_FLC0)
455#define MXC_BASE_FLC1 ((uint32_t)0x40029400UL)
456#define MXC_FLC1 ((mxc_flc_regs_t *)MXC_BASE_FLC1)
457
458#define MXC_FLC_GET_IRQ(i) (IRQn_Type)((i) == 0 ? FLC0_IRQn : \
459 (i) == 1 ? FLC1_IRQn 0)
460
461#define MXC_FLC_GET_BASE(i) ((i) == 0 ? MXC_BASE_FLC0 : (i) == 1 ? MXC_BASE_FLC1 : 0)
462
463#define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC0 : (i) == 1 ? MXC_FLC1 : 0)
464
465#define MXC_FLC_GET_IDX(p) ((p) == MXC_FLC0 ? 0 : (p) == MXC_FLC1 ? 1 : -1)
466
467/******************************************************************************/
468/* Instruction Cache */
469#define MXC_BASE_ICC ((uint32_t)0x4002A000UL)
470#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC)
471
472/******************************************************************************/
473/* ADC */
474#define MXC_BASE_ADC ((uint32_t)0x40034000UL)
475#define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC)
476
477/******************************************************************************/
478/* One Wire Master */
479#define MXC_BASE_OWM ((uint32_t)0x4003D000UL)
480#define MXC_OWM ((mxc_owm_regs_t *)MXC_BASE_OWM)
481
482/******************************************************************************/
483/* UART / Serial Port Interface */
484#define MXC_UART_INSTANCES (4)
485#define MXC_UART_FIFO_DEPTH (8)
486
487#define MXC_BASE_UART0 ((uint32_t)0x40042000UL)
488#define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0)
489#define MXC_BASE_UART1 ((uint32_t)0x40043000UL)
490#define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1)
491#define MXC_BASE_UART2 ((uint32_t)0x40044000UL)
492#define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2)
493#define MXC_BASE_UART3 ((uint32_t)0x40145000UL)
494#define MXC_UART3 ((mxc_uart_regs_t *)MXC_BASE_UART3)
495
496#define MXC_UART_GET_IRQ(i) \
497 (IRQn_Type)((i) == 0 ? UART0_IRQn : \
498 (i) == 1 ? UART1_IRQn : \
499 (i) == 2 ? UART2_IRQn : \
500 (i) == 3 ? UART3_IRQn : \
501 0)
502
503#define MXC_UART_GET_BASE(i) \
504 ((i) == 0 ? MXC_BASE_UART0 : \
505 (i) == 1 ? MXC_BASE_UART1 : \
506 (i) == 2 ? MXC_BASE_UART2 : \
507 (i) == 3 ? MXC_BASE_UART3 : \
508 0)
509
510#define MXC_UART_GET_UART(i) \
511 ((i) == 0 ? MXC_UART0 : (i) == 1 ? MXC_UART1 : (i) == 2 ? MXC_UART2 : (i) == 3 ? MXC_UART3 : 0)
512
513#define MXC_UART_GET_IDX(p) \
514 ((p) == MXC_UART0 ? 0 : (p) == MXC_UART1 ? 1 : (p) == MXC_UART2 ? 2 : (p) == MXC_UART3 ? 3 : -1)
515
516/******************************************************************************/
517/* SPI */
518#define MXC_SPI_INSTANCES (3)
519#define MXC_SPI_SS_INSTANCES (4)
520#define MXC_SPI_FIFO_DEPTH (32)
521
522#define MXC_BASE_SPI0 ((uint32_t)0x40046000UL)
523#define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0)
524#define MXC_BASE_SPI1 ((uint32_t)0x40047000UL)
525#define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1)
526#define MXC_BASE_SPI2 ((uint32_t)0x40048000UL)
527#define MXC_SPI2 ((mxc_spi_regs_t *)MXC_BASE_SPI2)
528
529#define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : (p) == MXC_SPI1 ? 1 : (p) == MXC_SPI2 ? 2 : -1)
530
531#define MXC_SPI_GET_BASE(i) \
532 ((i) == 0 ? MXC_BASE_SPI0 : (i) == 1 ? MXC_BASE_SPI1 : (i) == 2 ? MXC_BASE_SPI2 : 0)
533
534#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : (i) == 1 ? MXC_SPI1 : (i) == 2 ? MXC_SPI2 : 0)
535
536#define MXC_SPI_GET_IRQ(i) \
537 (IRQn_Type)((i) == 0 ? SPI0_IRQn : (i) == 1 ? SPI1_IRQn : (i) == 2 ? SPI2_IRQn : 0)
538
539/******************************************************************************/
540/* TRNG */
541#define MXC_BASE_TRNG ((uint32_t)0x4004D000UL)
542#define MXC_TRNG ((mxc_trng_regs_t *)MXC_BASE_TRNG)
543
544/******************************************************************************/
545#define MXC_BASE_I2S ((uint32_t)0x40060000UL)
546#define MXC_I2S ((mxc_i2s_regs_t *)MXC_BASE_I2S)
547
548/******************************************************************************/
549/* Quadrature Decoder Interface */
550#define MXC_BASE_QDEC ((uint32_t)0x40063000UL)
551#define MXC_QDEC ((mxc_qdec_regs_t *)MXC_BASE_QDEC)
552
553/******************************************************************************/
554/* Bit Shifting */
555#define MXC_F_BIT_0 (1 << 0)
556#define MXC_F_BIT_1 (1 << 1)
557#define MXC_F_BIT_2 (1 << 2)
558#define MXC_F_BIT_3 (1 << 3)
559#define MXC_F_BIT_4 (1 << 4)
560#define MXC_F_BIT_5 (1 << 5)
561#define MXC_F_BIT_6 (1 << 6)
562#define MXC_F_BIT_7 (1 << 7)
563#define MXC_F_BIT_8 (1 << 8)
564#define MXC_F_BIT_9 (1 << 9)
565#define MXC_F_BIT_10 (1 << 10)
566#define MXC_F_BIT_11 (1 << 11)
567#define MXC_F_BIT_12 (1 << 12)
568#define MXC_F_BIT_13 (1 << 13)
569#define MXC_F_BIT_14 (1 << 14)
570#define MXC_F_BIT_15 (1 << 15)
571#define MXC_F_BIT_16 (1 << 16)
572#define MXC_F_BIT_17 (1 << 17)
573#define MXC_F_BIT_18 (1 << 18)
574#define MXC_F_BIT_19 (1 << 19)
575#define MXC_F_BIT_20 (1 << 20)
576#define MXC_F_BIT_21 (1 << 21)
577#define MXC_F_BIT_22 (1 << 22)
578#define MXC_F_BIT_23 (1 << 23)
579#define MXC_F_BIT_24 (1 << 24)
580#define MXC_F_BIT_25 (1 << 25)
581#define MXC_F_BIT_26 (1 << 26)
582#define MXC_F_BIT_27 (1 << 27)
583#define MXC_F_BIT_28 (1 << 28)
584#define MXC_F_BIT_29 (1 << 29)
585#define MXC_F_BIT_30 (1 << 30)
586#define MXC_F_BIT_31 (1 << 31)
587
588/******************************************************************************/
589/* Bit Banding */
590#define BITBAND(reg, bit) \
591 ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg)&0x0fffffff) << 5) + \
592 ((bit) << 2))
593
594#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
595#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
596#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
597
598#define MXC_SETFIELD(reg, mask, setting) (reg = ((reg) & ~(mask)) | ((setting) & (mask)))
599
600/******************************************************************************/
601/* SCB CPACR */
602
603/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
604#define SCB_CPACR_CP10_Pos 20
605#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos)
606#define SCB_CPACR_CP11_Pos 22
607#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos)
609#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_MAX32672_H_
aes_regs.h
Registers, Bit Masks and Bit Positions for the AES Peripheral Module.
mxc_aes_regs_t
Definition: aes_regs.h:76
trimsir_regs.h
Registers, Bit Masks and Bit Positions for the TRIMSIR Peripheral Module.