MAX32672 Peripheral Driver API
Peripheral Driver API for the MAX32672
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mxc_pins.h
1
6/******************************************************************************
7 *
8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
9 * Analog Devices, Inc.),
10 * Copyright (C) 2023-2024 Analog Devices, Inc.
11 *
12 * Licensed under the Apache License, Version 2.0 (the "License");
13 * you may not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * http://www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an "AS IS" BASIS,
20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 *
24 ******************************************************************************/
25
26#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32672_MXC_PINS_H_
27#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32672_MXC_PINS_H_
28
29#include "gpio.h"
30
31// Pin mapping to use (i.e. UART0A, UART0B)
32typedef enum { MAP_A, MAP_B } sys_map_t;
33
34/***** Global Variables *****/
35// Predefined GPIO Configurations
36extern const mxc_gpio_cfg_t gpio_cfg_extclk;
37extern const mxc_gpio_cfg_t gpio_cfg_hfextclk;
38extern const mxc_gpio_cfg_t gpio_cfg_lpextclk;
39extern const mxc_gpio_cfg_t gpio_cfg_i2c0;
40extern const mxc_gpio_cfg_t gpio_cfg_i2c1;
41extern const mxc_gpio_cfg_t gpio_cfg_i2c2;
42extern const mxc_gpio_cfg_t gpio_cfg_i2c2b;
43extern const mxc_gpio_cfg_t gpio_cfg_i2c2c;
44
45extern const mxc_gpio_cfg_t gpio_cfg_uart0;
46extern const mxc_gpio_cfg_t gpio_cfg_uart0_flow;
47extern const mxc_gpio_cfg_t gpio_cfg_uart0_flow_disable;
48extern const mxc_gpio_cfg_t gpio_cfg_uart0b;
49extern const mxc_gpio_cfg_t gpio_cfg_uart0b_flow;
50extern const mxc_gpio_cfg_t gpio_cfg_uart0b_flow_disable;
51extern const mxc_gpio_cfg_t gpio_cfg_uart1;
52extern const mxc_gpio_cfg_t gpio_cfg_uart1_flow;
53extern const mxc_gpio_cfg_t gpio_cfg_uart1_flow_disable;
54extern const mxc_gpio_cfg_t gpio_cfg_uart1b;
55extern const mxc_gpio_cfg_t gpio_cfg_uart1b_flow;
56extern const mxc_gpio_cfg_t gpio_cfg_uart1b_flow_disable;
57extern const mxc_gpio_cfg_t gpio_cfg_uart2;
58extern const mxc_gpio_cfg_t gpio_cfg_uart2_flow;
59extern const mxc_gpio_cfg_t gpio_cfg_uart2_flow_disable;
60extern const mxc_gpio_cfg_t gpio_cfg_uart2b;
61extern const mxc_gpio_cfg_t gpio_cfg_uart2b_flow;
62extern const mxc_gpio_cfg_t gpio_cfg_uart2b_flow_disable;
63extern const mxc_gpio_cfg_t gpio_cfg_uart3;
64extern const mxc_gpio_cfg_t gpio_cfg_uart3_flow;
65extern const mxc_gpio_cfg_t gpio_cfg_uart3_flow_disable;
66
67extern const mxc_gpio_cfg_t gpio_cfg_spi0;
68extern const mxc_gpio_cfg_t gpio_cfg_spi0_ss0;
69extern const mxc_gpio_cfg_t gpio_cfg_spi0_ss1;
70extern const mxc_gpio_cfg_t gpio_cfg_spi0_ss2;
71extern const mxc_gpio_cfg_t gpio_cfg_spi0_ss3;
72
73// NOTE: SPI1 definied here with SS1 only, SS0 is on port0 by itself.
74extern const mxc_gpio_cfg_t gpio_cfg_spi1;
75// NOTE: SPI2 defined here with SS0 only, and NOT SS1 and SS2
76extern const mxc_gpio_cfg_t gpio_cfg_spi2;
77extern const mxc_gpio_cfg_t gpio_cfg_spi2b;
78// NOTE: SPI3 defined here with SS0 only, and NOT SS1, SS2, or SS3
79extern const mxc_gpio_cfg_t gpio_cfg_spi3;
80
81// Timers are only defined once, depending on package, each timer could be mapped to other pins
82extern const mxc_gpio_cfg_t gpio_cfg_tmr0a;
83extern const mxc_gpio_cfg_t gpio_cfg_tmr0b;
84extern const mxc_gpio_cfg_t gpio_cfg_tmr0c;
85extern const mxc_gpio_cfg_t gpio_cfg_tmr0d_in;
86extern const mxc_gpio_cfg_t gpio_cfg_tmr0d_out;
87
88extern const mxc_gpio_cfg_t gpio_cfg_tmr1a;
89extern const mxc_gpio_cfg_t gpio_cfg_tmr1b;
90extern const mxc_gpio_cfg_t gpio_cfg_tmr1c;
91extern const mxc_gpio_cfg_t gpio_cfg_tmr1d;
92
93extern const mxc_gpio_cfg_t gpio_cfg_tmr2a;
94extern const mxc_gpio_cfg_t gpio_cfg_tmr2b;
95extern const mxc_gpio_cfg_t gpio_cfg_tmr2c;
96
97extern const mxc_gpio_cfg_t gpio_cfg_tmr3a;
98extern const mxc_gpio_cfg_t gpio_cfg_tmr3b;
99extern const mxc_gpio_cfg_t gpio_cfg_tmr3c;
100extern const mxc_gpio_cfg_t gpio_cfg_tmr3d;
101
102extern const mxc_gpio_cfg_t gpio_cfg_lptmr0;
103extern const mxc_gpio_cfg_t gpio_cfg_lptmr1;
104
105extern const mxc_gpio_cfg_t gpio_cfg_i2s0;
106
107extern const mxc_gpio_cfg_t gpio_cfg_rtcsqw;
108extern const mxc_gpio_cfg_t gpio_cfg_rtcsqwb;
109
110extern const mxc_gpio_cfg_t gpio_cfg_qdec_in;
111extern const mxc_gpio_cfg_t gpio_cfg_qdec_out;
112
113extern const mxc_gpio_cfg_t gpio_cfg_lc1;
114extern const mxc_gpio_cfg_t gpio_cfg_mon_lc1;
115extern const mxc_gpio_cfg_t gpio_cfg_cmd_rs_lc1;
116extern const mxc_gpio_cfg_t gpio_cfg_chrg_lc1;
117extern const mxc_gpio_cfg_t gpio_cfg_lc2;
118extern const mxc_gpio_cfg_t gpio_cfg_mon_lc2;
119extern const mxc_gpio_cfg_t gpio_cfg_cmd_rs_lc2;
120extern const mxc_gpio_cfg_t gpio_cfg_chrg_lc2;
121
122extern const mxc_gpio_cfg_t gpio_cfg_adc_ain0;
123extern const mxc_gpio_cfg_t gpio_cfg_adc_ain1;
124extern const mxc_gpio_cfg_t gpio_cfg_adc_ain2;
125extern const mxc_gpio_cfg_t gpio_cfg_adc_ain3;
126extern const mxc_gpio_cfg_t gpio_cfg_adc_ain4;
127extern const mxc_gpio_cfg_t gpio_cfg_adc_ain5;
128extern const mxc_gpio_cfg_t gpio_cfg_adc_ain6;
129extern const mxc_gpio_cfg_t gpio_cfg_adc_ain7;
130extern const mxc_gpio_cfg_t gpio_cfg_adc_ain8;
131extern const mxc_gpio_cfg_t gpio_cfg_adc_ain9;
132extern const mxc_gpio_cfg_t gpio_cfg_adc_ain10;
133extern const mxc_gpio_cfg_t gpio_cfg_adc_ain11;
134
135// SPI v2 Pin Definitions
136extern const mxc_gpio_cfg_t gpio_cfg_spi0_standard;
137extern const mxc_gpio_cfg_t gpio_cfg_spi0_3wire;
138// MXC_SPI0 does not support Dual or Quad modes
139extern const mxc_gpio_cfg_t gpio_cfg_spi1_standard;
140extern const mxc_gpio_cfg_t gpio_cfg_spi1_3wire;
141// MXC_SPI1 does not support Dual or Quad modes
142extern const mxc_gpio_cfg_t gpio_cfg_spi2_standard;
143extern const mxc_gpio_cfg_t gpio_cfg_spi2_3wire;
144// MXC_SPI2 does not support Dual or Quad modes
145
146// SPI v2 Target Selects Pin Definitions
147extern const mxc_gpio_cfg_t gpio_cfg_spi0_ts0;
148extern const mxc_gpio_cfg_t gpio_cfg_spi0_ts1;
149extern const mxc_gpio_cfg_t gpio_cfg_spi0_ts2;
150extern const mxc_gpio_cfg_t gpio_cfg_spi0_ts3;
151extern const mxc_gpio_cfg_t gpio_cfg_spi1_ts0;
152extern const mxc_gpio_cfg_t gpio_cfg_spi2_ts0;
153
154#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32672_MXC_PINS_H_
mxc_gpio_cfg_t
Structure type for configuring a GPIO port.
Definition: gpio.h:165