trimsir_regs.h

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/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_TRIMSIR_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_TRIMSIR_REGS_H_
 
/* **** Includes **** */
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined (__ICCARM__)
  #pragma system_include
#endif
 
#if defined (__CC_ARM)
  #pragma anon_unions
#endif
/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif
#ifndef __R
#define __R  volatile const
#endif
 
/* **** Definitions **** */
 
typedef struct {
    __R  uint32_t rsv_0x0_0x7[2];
    __IO uint32_t bb_sir2;              
    __IO uint32_t bb_sir3;              
    __R  uint32_t rsv_0x10_0x17[2];
    __I  uint32_t bb_sir6;              
} mxc_trimsir_regs_t;
 
/* Register offsets for module TRIMSIR */
#define MXC_R_TRIMSIR_BB_SIR2              ((uint32_t)0x00000008UL) 
#define MXC_R_TRIMSIR_BB_SIR3              ((uint32_t)0x0000000CUL) 
#define MXC_R_TRIMSIR_BB_SIR6              ((uint32_t)0x00000018UL) 
#define MXC_F_TRIMSIR_BB_SIR2_TRIM_IBRO_RBIAS_POS      0 
#define MXC_F_TRIMSIR_BB_SIR2_TRIM_IBRO_RBIAS          ((uint32_t)(0x3FUL << MXC_F_TRIMSIR_BB_SIR2_TRIM_IBRO_RBIAS_POS)) 
#define MXC_F_TRIMSIR_BB_SIR2_RAM0_1ECCEN_POS          8 
#define MXC_F_TRIMSIR_BB_SIR2_RAM0_1ECCEN              ((uint32_t)(0x1UL << MXC_F_TRIMSIR_BB_SIR2_RAM0_1ECCEN_POS)) 
#define MXC_F_TRIMSIR_BB_SIR2_RAM2ECCEN_POS            9 
#define MXC_F_TRIMSIR_BB_SIR2_RAM2ECCEN                ((uint32_t)(0x1UL << MXC_F_TRIMSIR_BB_SIR2_RAM2ECCEN_POS)) 
#define MXC_F_TRIMSIR_BB_SIR2_RAM3ECCEN_POS            10 
#define MXC_F_TRIMSIR_BB_SIR2_RAM3ECCEN                ((uint32_t)(0x1UL << MXC_F_TRIMSIR_BB_SIR2_RAM3ECCEN_POS)) 
#define MXC_F_TRIMSIR_BB_SIR2_ICC0ECCEN_POS            11 
#define MXC_F_TRIMSIR_BB_SIR2_ICC0ECCEN                ((uint32_t)(0x1UL << MXC_F_TRIMSIR_BB_SIR2_ICC0ECCEN_POS)) 
#define MXC_F_TRIMSIR_BB_SIR2_FL0ECCEN_POS             12 
#define MXC_F_TRIMSIR_BB_SIR2_FL0ECCEN                 ((uint32_t)(0x1UL << MXC_F_TRIMSIR_BB_SIR2_FL0ECCEN_POS)) 
#define MXC_F_TRIMSIR_BB_SIR2_FL1ECCEN_POS             13 
#define MXC_F_TRIMSIR_BB_SIR2_FL1ECCEN                 ((uint32_t)(0x1UL << MXC_F_TRIMSIR_BB_SIR2_FL1ECCEN_POS)) 
#define MXC_F_TRIMSIR_BB_SIR2_TRIM_IBRO_POS            16 
#define MXC_F_TRIMSIR_BB_SIR2_TRIM_IBRO                ((uint32_t)(0xFFFFUL << MXC_F_TRIMSIR_BB_SIR2_TRIM_IBRO_POS)) 
#define MXC_F_TRIMSIR_BB_SIR6_RTCX1TRIM_POS            4 
#define MXC_F_TRIMSIR_BB_SIR6_RTCX1TRIM                ((uint32_t)(0x1FUL << MXC_F_TRIMSIR_BB_SIR6_RTCX1TRIM_POS)) 
#define MXC_F_TRIMSIR_BB_SIR6_RTCX2TRIM_POS            9 
#define MXC_F_TRIMSIR_BB_SIR6_RTCX2TRIM                ((uint32_t)(0x1FUL << MXC_F_TRIMSIR_BB_SIR6_RTCX2TRIM_POS)) 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_TRIMSIR_REGS_H_