MAX32675 Peripheral Driver API
Peripheral Driver API for the MAX32675
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aes_regs.h
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1
8/******************************************************************************
9 *
10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
11 * Analog Devices, Inc.),
12 * Copyright (C) 2023-2024 Analog Devices, Inc.
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 * http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *
26 ******************************************************************************/
27
28#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32675_INCLUDE_AES_REGS_H_
29#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32675_INCLUDE_AES_REGS_H_
30
31/* **** Includes **** */
32#include <stdint.h>
33
34#ifdef __cplusplus
35extern "C" {
36#endif
37
38#if defined (__ICCARM__)
39 #pragma system_include
40#endif
41
42#if defined (__CC_ARM)
43 #pragma anon_unions
44#endif
46/*
47 If types are not defined elsewhere (CMSIS) define them here
48*/
49#ifndef __IO
50#define __IO volatile
51#endif
52#ifndef __I
53#define __I volatile const
54#endif
55#ifndef __O
56#define __O volatile
57#endif
58#ifndef __R
59#define __R volatile const
60#endif
62
63/* **** Definitions **** */
64
76typedef struct {
77 __IO uint32_t ctrl;
78 __IO uint32_t status;
79 __IO uint32_t intfl;
80 __IO uint32_t inten;
81 __IO uint32_t fifo;
82} mxc_aes_regs_t;
83
84/* Register offsets for module AES */
91#define MXC_R_AES_CTRL ((uint32_t)0x00000000UL)
92#define MXC_R_AES_STATUS ((uint32_t)0x00000004UL)
93#define MXC_R_AES_INTFL ((uint32_t)0x00000008UL)
94#define MXC_R_AES_INTEN ((uint32_t)0x0000000CUL)
95#define MXC_R_AES_FIFO ((uint32_t)0x00000010UL)
104#define MXC_F_AES_CTRL_EN_POS 0
105#define MXC_F_AES_CTRL_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_EN_POS))
107#define MXC_F_AES_CTRL_DMA_RX_EN_POS 1
108#define MXC_F_AES_CTRL_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_DMA_RX_EN_POS))
110#define MXC_F_AES_CTRL_DMA_TX_EN_POS 2
111#define MXC_F_AES_CTRL_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_DMA_TX_EN_POS))
113#define MXC_F_AES_CTRL_START_POS 3
114#define MXC_F_AES_CTRL_START ((uint32_t)(0x1UL << MXC_F_AES_CTRL_START_POS))
116#define MXC_F_AES_CTRL_INPUT_FLUSH_POS 4
117#define MXC_F_AES_CTRL_INPUT_FLUSH ((uint32_t)(0x1UL << MXC_F_AES_CTRL_INPUT_FLUSH_POS))
119#define MXC_F_AES_CTRL_OUTPUT_FLUSH_POS 5
120#define MXC_F_AES_CTRL_OUTPUT_FLUSH ((uint32_t)(0x1UL << MXC_F_AES_CTRL_OUTPUT_FLUSH_POS))
122#define MXC_F_AES_CTRL_KEY_SIZE_POS 6
123#define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x3UL << MXC_F_AES_CTRL_KEY_SIZE_POS))
124#define MXC_V_AES_CTRL_KEY_SIZE_AES128 ((uint32_t)0x0UL)
125#define MXC_S_AES_CTRL_KEY_SIZE_AES128 (MXC_V_AES_CTRL_KEY_SIZE_AES128 << MXC_F_AES_CTRL_KEY_SIZE_POS)
126#define MXC_V_AES_CTRL_KEY_SIZE_AES192 ((uint32_t)0x1UL)
127#define MXC_S_AES_CTRL_KEY_SIZE_AES192 (MXC_V_AES_CTRL_KEY_SIZE_AES192 << MXC_F_AES_CTRL_KEY_SIZE_POS)
128#define MXC_V_AES_CTRL_KEY_SIZE_AES256 ((uint32_t)0x2UL)
129#define MXC_S_AES_CTRL_KEY_SIZE_AES256 (MXC_V_AES_CTRL_KEY_SIZE_AES256 << MXC_F_AES_CTRL_KEY_SIZE_POS)
131#define MXC_F_AES_CTRL_TYPE_POS 8
132#define MXC_F_AES_CTRL_TYPE ((uint32_t)(0x3UL << MXC_F_AES_CTRL_TYPE_POS))
142#define MXC_F_AES_STATUS_BUSY_POS 0
143#define MXC_F_AES_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_AES_STATUS_BUSY_POS))
145#define MXC_F_AES_STATUS_INPUT_EM_POS 1
146#define MXC_F_AES_STATUS_INPUT_EM ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_EM_POS))
148#define MXC_F_AES_STATUS_INPUT_FULL_POS 2
149#define MXC_F_AES_STATUS_INPUT_FULL ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_FULL_POS))
151#define MXC_F_AES_STATUS_OUTPUT_EM_POS 3
152#define MXC_F_AES_STATUS_OUTPUT_EM ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_EM_POS))
154#define MXC_F_AES_STATUS_OUTPUT_FULL_POS 4
155#define MXC_F_AES_STATUS_OUTPUT_FULL ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_FULL_POS))
165#define MXC_F_AES_INTFL_DONE_POS 0
166#define MXC_F_AES_INTFL_DONE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_DONE_POS))
168#define MXC_F_AES_INTFL_KEY_CHANGE_POS 1
169#define MXC_F_AES_INTFL_KEY_CHANGE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_CHANGE_POS))
171#define MXC_F_AES_INTFL_KEY_ZERO_POS 2
172#define MXC_F_AES_INTFL_KEY_ZERO ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_ZERO_POS))
174#define MXC_F_AES_INTFL_OV_POS 3
175#define MXC_F_AES_INTFL_OV ((uint32_t)(0x1UL << MXC_F_AES_INTFL_OV_POS))
177#define MXC_F_AES_INTFL_KEY_ONE_POS 4
178#define MXC_F_AES_INTFL_KEY_ONE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_ONE_POS))
188#define MXC_F_AES_INTEN_DONE_POS 0
189#define MXC_F_AES_INTEN_DONE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_DONE_POS))
191#define MXC_F_AES_INTEN_KEY_CHANGE_POS 1
192#define MXC_F_AES_INTEN_KEY_CHANGE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_CHANGE_POS))
194#define MXC_F_AES_INTEN_KEY_ZERO_POS 2
195#define MXC_F_AES_INTEN_KEY_ZERO ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_ZERO_POS))
197#define MXC_F_AES_INTEN_OV_POS 3
198#define MXC_F_AES_INTEN_OV ((uint32_t)(0x1UL << MXC_F_AES_INTEN_OV_POS))
200#define MXC_F_AES_INTEN_KEY_ONE_POS 4
201#define MXC_F_AES_INTEN_KEY_ONE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_ONE_POS))
211#define MXC_F_AES_FIFO_DATA_POS 0
212#define MXC_F_AES_FIFO_DATA ((uint32_t)(0x1UL << MXC_F_AES_FIFO_DATA_POS))
216#ifdef __cplusplus
217}
218#endif
219
220#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32675_INCLUDE_AES_REGS_H_
mxc_aes_regs_t::intfl
__IO uint32_t intfl
Definition: aes_regs.h:79
mxc_aes_regs_t::ctrl
__IO uint32_t ctrl
Definition: aes_regs.h:77
mxc_aes_regs_t::fifo
__IO uint32_t fifo
Definition: aes_regs.h:81
mxc_aes_regs_t::inten
__IO uint32_t inten
Definition: aes_regs.h:80
mxc_aes_regs_t::status
__IO uint32_t status
Definition: aes_regs.h:78
mxc_aes_regs_t
Definition: aes_regs.h:76