MAX32675 Peripheral Driver API
Peripheral Driver API for the MAX32675
max32675.h
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/******************************************************************************
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*
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* Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
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* Analog Devices, Inc.),
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* Copyright (C) 2023-2024 Analog Devices, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************/
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#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32675_INCLUDE_MAX32675_H_
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#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32675_INCLUDE_MAX32675_H_
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#ifndef TARGET_NUM
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#define TARGET_NUM 32675
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#endif
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#define MXC_NUMCORES 1
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#include <stdint.h>
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#ifndef FALSE
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#define FALSE (0)
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#endif
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#ifndef TRUE
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#define TRUE (1)
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#endif
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/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
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#if defined(__GNUC__)
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#ifndef __weak
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#define __weak __attribute__((weak))
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#endif
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#elif defined(__CC_ARM)
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#define inline __inline
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#pragma anon_unions
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#endif
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typedef
enum
{
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NonMaskableInt_IRQn = -14,
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HardFault_IRQn = -13,
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MemoryManagement_IRQn = -12,
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BusFault_IRQn = -11,
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UsageFault_IRQn = -10,
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SVCall_IRQn = -5,
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DebugMonitor_IRQn = -4,
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PendSV_IRQn = -2,
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SysTick_IRQn = -1,
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/* Device-specific interrupt sources (external to ARM core) */
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/* table entry number */
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/* |||| */
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/* |||| table offset address */
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/* vvvv vvvvvv */
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PF_IRQn = 0,
/* 0x10 0x0040 16: Power Fail */
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WDT0_IRQn,
/* 0x11 0x0044 17: Watchdog 0 */
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RSV02_IRQn,
/* 0x12 0x0048 18: Reserved */
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RTC_IRQn,
/* 0x13 0x004C 19: RTC */
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TRNG_IRQn,
/* 0x14 0x0050 20: True Random Number Generator */
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TMR0_IRQn,
/* 0x15 0x0054 21: Timer 0 */
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TMR1_IRQn,
/* 0x16 0x0058 22: Timer 1 */
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TMR2_IRQn,
/* 0x17 0x005C 23: Timer 2 */
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TMR3_IRQn,
/* 0x18 0x0060 24: Timer 3 */
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TMR4_IRQn,
/* 0x19 0x0064 25: Timer 4 */
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TMR5_IRQn,
/* 0x1A 0x0068 26: Timer 5 */
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RSV11_IRQn,
/* 0x1B 0x006C 27: Reserved */
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RSV12_IRQn,
/* 0x1C 0x0070 28: Reserved */
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I2C0_IRQn,
/* 0x1D 0x0074 29: I2C0 */
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UART0_IRQn,
/* 0x1E 0x0078 30: UART 0 */
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UART1_IRQn,
/* 0x1F 0x007C 31: UART 1 */
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SPI0_IRQn,
/* 0x20 0x0080 32: SPI0 */
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SPI1_IRQn,
/* 0x21 0x0084 33: SPI1 */
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SPI2_IRQn,
/* 0x22 0x0088 34: SPI2 */
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RSV19_IRQn,
/* 0x23 0x008C 35: Reserved */
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RSV20_IRQn,
/* 0x24 0x0090 36: Reserved */
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RSV21_IRQn,
/* 0x25 0x0094 37: Reserved */
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RSV22_IRQn,
/* 0x26 0x0098 38: Magstripe DSP */
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FLC0_IRQn,
/* 0x27 0x009C 39: Flash Controller 0 */
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GPIO0_IRQn,
/* 0x28 0x00A0 40: GPIO0 */
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GPIO1_IRQn,
/* 0x29 0x00A4 41: GPIO2 */
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RSV26_IRQn,
/* 0x2A 0x00A8 42: GPIO3 */
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RSV27_IRQn,
/* 0x2B 0x00AC 43: Crypto */
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DMA0_IRQn,
/* 0x2C 0x00B0 44: DMA0 */
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DMA1_IRQn,
/* 0x2D 0x00B4 45: DMA1 */
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DMA2_IRQn,
/* 0x2E 0x00B8 46: DMA2 */
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DMA3_IRQn,
/* 0x2F 0x00BC 47: DMA3 */
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RSV32_IRQn,
/* 0x30 0x00C0 48: Reserved */
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RSV33_IRQn,
/* 0x31 0x00C4 49: Reserved */
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UART2_IRQn,
/* 0x32 0x00C8 50: UART 2 */
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RSV35_IRQn,
/* 0x33 0x00CC 51: Contactless Link Control */
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I2C1_IRQn,
/* 0x34 0x00D0 52: I2C1 */
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RSV37_IRQn,
/* 0x35 0x00D4 53: Smart Card 1 */
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RSV38_IRQn,
/* 0x36 0x00D8 54: Reserved */
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RSV39_IRQn,
/* 0x37 0x00DC 55: Reserved */
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RSV40_IRQn,
/* 0x38 0x00E0 56: Reserved */
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RSV41_IRQn,
/* 0x39 0x00E4 57: Reserved */
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RSV42_IRQn,
/* 0x3A 0x00E8 58: Reserved */
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RSV43_IRQn,
/* 0x3B 0x00EC 59: Reserved */
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RSV44_IRQn,
/* 0x3C 0x00F0 60: Reserved */
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RSV45_IRQn,
/* 0x3D 0x00F4 61: Reserved */
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RSV46_IRQn,
/* 0x3E 0x00F8 62: Reserved */
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RSV47_IRQn,
/* 0x3F 0x00FC 63: Reserved */
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RSV48_IRQn,
/* 0x40 0x0100 64: Reserved */
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RSV49_IRQn,
/* 0x41 0x0104 65: Reserved */
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RSV50_IRQn,
/* 0x42 0x0108 66: Reserved */
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RSV51_IRQn,
/* 0x43 0x010C 67: Reserved */
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RSV52_IRQn,
/* 0x44 0x0110 68: Reserved */
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RSV53_IRQn,
/* 0x45 0x0114 69: Reserved */
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GPIOWAKE_IRQn,
/* 0x46 0x0118 70: GPIOWAKE */
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RSV55_IRQn,
/* 0x47 0x011C 71: Reserved */
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RSV56_IRQn,
/* 0x48 0x0120 72: Reserved */
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WDT1_IRQn,
/* 0x49 0x0124 73: Watchdog 1 */
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RSV57_IRQn,
/* 0x4A 0x0128 74: Reserved */
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RSV58_IRQn,
/* 0x4B 0x012C 75: Reserved */
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RSV59_IRQn,
/* 0x4C 0x0130 76: Reserved */
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RSV61_IRQn,
/* 0x4D 0x0134 77: Reserved */
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I2C2_IRQn,
/* 0x4E 0x0138 78: I2C 2 */
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RSV63_IRQn,
/* 0x4F 0x013C 79: Reserved */
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RSV64_IRQn,
/* 0x50 0x0140 80: Reserved */
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RSV65_IRQn,
/* 0x51 0x0144 81: Reserved */
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RSV66_IRQn,
/* 0x52 0x0148 82: Reserved */
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RSV67_IRQn,
/* 0x53 0x014C 83: One Wire Master */
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DMA4_IRQn,
/* 0x54 0x0150 84: DMA4 */
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DMA5_IRQn,
/* 0x55 0x0154 85: DMA5 */
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DMA6_IRQn,
/* 0x56 0x0158 86: DMA6 */
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DMA7_IRQn,
/* 0x57 0x015C 87: DMA7 */
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RSV72_IRQn,
/* 0x58 0x0160 88: Reserved */
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RSV73_IRQn,
/* 0x59 0x0164 89: Reserved */
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RSV74_IRQn,
/* 0x5A 0x0168 90: Reserved */
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RSV75_IRQn,
/* 0x5B 0x016C 91: Reserved */
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RSV76_IRQn,
/* 0x5C 0x0170 92: Reserved */
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RSV77_IRQn,
/* 0x5D 0x0174 93: Reserved */
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RSV78_IRQn,
/* 0x5E 0x0178 94: Reserved */
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RSV79_IRQn,
/* 0x5F 0x017C 95: Reserved */
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RSV80_IRQn,
/* 0x60 0x0180 96: Reserved */
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RSV81_IRQn,
/* 0x61 0x0184 97: Reserved */
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ECC_IRQn,
/* 0x62 0x0188 98: Error Correction */
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RSV83_IRQn,
/* 0x63 0x018C 99: Reserved */
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RSV84_IRQn,
/* 0x64 0x0190 100: Reserved */
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RSV85_IRQn,
/* 0x65 0x0194 101: Reserved */
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RSV86_IRQn,
/* 0x66 0x0198 102: Reserved */
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RSV87_IRQn,
/* 0x67 0x019C 103: Reserved */
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UART3_IRQn,
/* 0x68 0x01A0 104: UART 3 */
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RSV89_IRQn,
/* 0x69 0x01A4 105: Reserved */
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RSV90_IRQn,
/* 0x6A 0x01A8 106: Reserved */
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RSV91_IRQn,
/* 0x6B 0x01AC 107: Reserved */
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RSV92_IRQn,
/* 0x6C 0x01B0 108: Reserved */
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RSV93_IRQn,
/* 0x6D 0x01B4 109: Reserved */
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RSV94_IRQn,
/* 0x6E 0x01B8 110: Reserved */
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RSV95_IRQn,
/* 0x6F 0x01BC 111: Reserved */
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RSV96_IRQn,
/* 0x70 0x01C0 112: Reserved */
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AES_IRQn,
/* 0x71 0x01C4 113: Reserved */
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CRC_IRQn,
/* 0x72 0x01C8 114: Reserved */
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I2S_IRQn,
/* 0x73 0x01CC 115: Reserved */
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MXC_IRQ_EXT_COUNT,
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} IRQn_Type;
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#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
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/* ================================================================================ */
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/* ================ Processor and Core Peripheral Section ================ */
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/* ================================================================================ */
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/* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */
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#define __CM4_REV 0x0100
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#define __MPU_PRESENT 1
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#define __NVIC_PRIO_BITS 3
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#define __Vendor_SysTickConfig 0
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#define __FPU_PRESENT 1
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#include <core_cm4.h>
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#include "system_max32675.h"
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/* ================================================================================ */
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/* ================== Device Specific Memory Section ================== */
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/* ================================================================================ */
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#define MXC_ROM_MEM_BASE 0x00000000UL
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#define MXC_ROM_MEM_SIZE 0x00020000UL
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#define MXC_XIP_MEM_BASE 0x08000000UL
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#define MXC_XIP_MEM_SIZE 0x08000000UL
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#define MXC_FLASH0_MEM_BASE 0x10000000UL
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#define MXC_FLASH_MEM_BASE MXC_FLASH0_MEM_BASE
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#define MXC_FLASH_PAGE_SIZE 0x00002000UL
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#define MXC_FLASH_MEM_SIZE 0x00060000UL
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#define MXC_INFO0_MEM_BASE 0x10800000UL
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#define MXC_INFO_MEM_BASE MXC_INFO0_MEM_BASE
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#define MXC_INFO_MEM_SIZE 0x00004000UL
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#define MXC_SRAM_MEM_BASE 0x20000000UL
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#define MXC_SRAM_MEM_SIZE 0x000BE000UL
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#define MXC_XIP_DATA_MEM_BASE 0x80000000UL
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#define MXC_XIP_DATA_MEM_SIZE 0x20000000UL
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/* ================================================================================ */
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/* ================ Device Specific Peripheral Section ================ */
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/* ================================================================================ */
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/*
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Base addresses and configuration settings for all MAX32675 peripheral modules.
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*/
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/******************************************************************************/
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/* Global control */
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#define MXC_BASE_GCR ((uint32_t)0x40000000UL)
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#define MXC_GCR ((mxc_gcr_regs_t *)MXC_BASE_GCR)
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/******************************************************************************/
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/* Non-battery backed SI Registers */
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#define MXC_BASE_SIR ((uint32_t)0x40000400UL)
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#define MXC_SIR ((mxc_sir_regs_t *)MXC_BASE_SIR)
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/******************************************************************************/
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/* Non-battery backed Function Control */
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#define MXC_BASE_FCR ((uint32_t)0x40000800UL)
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#define MXC_FCR ((mxc_fcr_regs_t *)MXC_BASE_FCR)
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/******************************************************************************/
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/* Watchdog */
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#define MXC_BASE_WDT0 ((uint32_t)0x40003000UL)
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#define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
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#define MXC_BASE_WDT1 ((uint32_t)0x40003400UL)
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#define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1)
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/******************************************************************************/
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/* AES Keys */
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#define MXC_BASE_AESKEYS ((uint32_t)0x40005000UL)
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#define MXC_AESKEYS ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS)
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// DEPRECATED(1-10-2023): Scheduled for removal.
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#define MXC_BASE_AESKEY MXC_BASE_AESKEYS
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#define MXC_AESKEY ((mxc_aes_key_regs_t *)MXC_BASE_AESKEY)
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/******************************************************************************/
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/* Error Correcting Code */
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#define MXC_BASE_ECC ((uint32_t)0x40105400UL)
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#define MXC_ECC ((mxc_ecc_regs_t *)MXC_BASE_ECC)
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/******************************************************************************/
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/* (ECC) Trim System Initalization Register */
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#define MXC_BASE_TRIMSIR ((uint32_t)0x40105400UL)
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#define MXC_TRIMSIR ((mxc_ecc_regs_t *)MXC_BASE_TRIMSIR)
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/******************************************************************************/
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/* Real Time Clock */
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#define MXC_BASE_RTC ((uint32_t)0x40106000UL)
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#define MXC_RTC ((mxc_rtc_regs_t *)MXC_BASE_RTC)
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/******************************************************************************/
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/* Power Sequencer */
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#define MXC_BASE_PWRSEQ ((uint32_t)0x40106800UL)
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#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
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/******************************************************************************/
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/* MISC Control */
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#define MXC_BASE_MCR ((uint32_t)0x40106C00UL)
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#define MXC_MCR ((mxc_mcr_regs_t *)MXC_BASE_MCR)
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/******************************************************************************/
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/* AES */
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#define MXC_BASE_AES ((uint32_t)0x40007400UL)
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#define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES)
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/******************************************************************************/
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/* GPIO */
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#define MXC_CFG_GPIO_INSTANCES (3)
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#define MXC_CFG_GPIO_PINS_PORT (32)
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#define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL)
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#define MXC_GPIO0 ((mxc_gpio_regs_t *)MXC_BASE_GPIO0)
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#define MXC_BASE_GPIO1 ((uint32_t)0x40009000UL)
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#define MXC_GPIO1 ((mxc_gpio_regs_t *)MXC_BASE_GPIO1)
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#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : (p) == MXC_GPIO1 ? 1 : -1)
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#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : (i) == 1 ? MXC_GPIO1 : 0)
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#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : (i) == 1 ? GPIO1_IRQn : 0)
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/******************************************************************************/
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/* CRC */
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#define MXC_BASE_CRC ((uint32_t)0x4000F000UL)
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#define MXC_CRC ((mxc_crc_regs_t *)MXC_BASE_CRC)
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/******************************************************************************/
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/* Timer */
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#define SEC(s) (((uint32_t)s) * 1000000UL)
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#define MSEC(ms) (ms * 1000UL)
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#define USEC(us) (us)
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#define MXC_CFG_TMR_INSTANCES (6)
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#define MXC_BASE_TMR0 ((uint32_t)0x40010000UL)
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#define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0)
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#define MXC_BASE_TMR1 ((uint32_t)0x40011000UL)
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#define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1)
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#define MXC_BASE_TMR2 ((uint32_t)0x40012000UL)
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#define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2)
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#define MXC_BASE_TMR3 ((uint32_t)0x40013000UL)
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#define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3)
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#define MXC_BASE_TMR4 ((uint32_t)0x40114000UL)
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#define MXC_TMR4 ((mxc_tmr_regs_t *)MXC_BASE_TMR4)
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#define MXC_BASE_TMR5 ((uint32_t)0x40115000UL)
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#define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5)
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#define MXC_TMR_GET_IRQ(i) \
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(IRQn_Type)((i) == 0 ? TMR0_IRQn : \
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(i) == 1 ? TMR1_IRQn : \
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(i) == 2 ? TMR2_IRQn : \
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(i) == 3 ? TMR3_IRQn : \
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(i) == 4 ? TMR4_IRQn : \
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(i) == 5 ? TMR5_IRQn : \
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0)
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#define MXC_TMR_GET_BASE(i) \
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((i) == 0 ? MXC_BASE_TMR0 : \
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(i) == 1 ? MXC_BASE_TMR1 : \
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(i) == 2 ? MXC_BASE_TMR2 : \
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(i) == 3 ? MXC_BASE_TMR3 : \
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(i) == 4 ? MXC_BASE_TMR4 : \
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(i) == 5 ? MXC_BASE_TMR5 : \
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0)
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#define MXC_TMR_GET_TMR(i) \
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((i) == 0 ? MXC_TMR0 : \
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(i) == 1 ? MXC_TMR1 : \
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(i) == 2 ? MXC_TMR2 : \
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(i) == 3 ? MXC_TMR3 : \
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(i) == 4 ? MXC_TMR4 : \
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(i) == 5 ? MXC_TMR5 : \
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0)
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#define MXC_TMR_GET_IDX(p) \
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((p) == MXC_TMR0 ? 0 : \
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(p) == MXC_TMR1 ? 1 : \
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(p) == MXC_TMR2 ? 2 : \
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(p) == MXC_TMR3 ? 3 : \
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(p) == MXC_TMR4 ? 4 : \
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(p) == MXC_TMR5 ? 5 : \
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-1)
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/******************************************************************************/
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/* I2C */
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#define MXC_I2C_INSTANCES (3)
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#define MXC_I2C_FIFO_DEPTH (8)
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#define MXC_I2C_NUM_TARGET_ADDR (4)
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#define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL)
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#define MXC_I2C0 ((mxc_i2c_regs_t *)MXC_BASE_I2C0)
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#define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL)
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#define MXC_I2C1 ((mxc_i2c_regs_t *)MXC_BASE_I2C1)
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#define MXC_BASE_I2C2 ((uint32_t)0x4001F000UL)
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#define MXC_I2C2 ((mxc_i2c_regs_t *)MXC_BASE_I2C2)
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#define MXC_I2C_GET_IRQ(i) \
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(IRQn_Type)((i) == 0 ? I2C0_IRQn : (i) == 1 ? I2C1_IRQn : (i) == 2 ? I2C2_IRQn : 0)
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#define MXC_I2C_GET_BASE(i) \
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((i) == 0 ? MXC_BASE_I2C0 : (i) == 1 ? MXC_BASE_I2C1 : (i) == 2 ? MXC_BASE_I2C2 : 0)
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#define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : (i) == 1 ? MXC_I2C1 : (i) == 2 ? MXC_I2C2 : 0)
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#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : (p) == MXC_I2C1 ? 1 : (p) == MXC_I2C2 ? 2 : -1)
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/******************************************************************************/
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/* DMA */
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#define MXC_DMA_CHANNELS (8)
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#define MXC_DMA_INSTANCES (1)
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#define MXC_BASE_DMA ((uint32_t)0x40028000UL)
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#define MXC_DMA ((mxc_dma_regs_t *)MXC_BASE_DMA)
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#define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA ? 0 : -1)
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#define MXC_DMA_CH_GET_IRQ(i) \
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((IRQn_Type)(((i) == 0) ? DMA0_IRQn : \
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((i) == 1) ? DMA1_IRQn : \
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((i) == 2) ? DMA2_IRQn : \
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((i) == 3) ? DMA3_IRQn : \
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((i) == 4) ? DMA4_IRQn : \
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((i) == 5) ? DMA5_IRQn : \
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((i) == 6) ? DMA6_IRQn : \
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((i) == 7) ? DMA7_IRQn : \
398
0))
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400
/******************************************************************************/
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/* FLC */
402
#define MXC_FLC_INSTANCES (1)
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#define MXC_BASE_FLC0 ((uint32_t)0x40029000UL)
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#define MXC_FLC0 ((mxc_flc_regs_t *)MXC_BASE_FLC0)
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#define MXC_FLC_GET_IRQ(i) (IRQn_Type)((i) == 0 ? FLC0_IRQn : 0)
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#define MXC_FLC_GET_BASE(i) ((i) == 0 ? MXC_BASE_FLC0 : 0)
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#define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC0 : 0)
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#define MXC_FLC_GET_IDX(p) ((p) == MXC_FLC0 ? 0 : -1)
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/******************************************************************************/
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/* Instruction Cache */
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#define MXC_BASE_ICC ((uint32_t)0x4002A000UL)
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#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC)
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420
/******************************************************************************/
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/* Data Cache */
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#define MXC_BASE_EMCC ((uint32_t)0x40033000UL)
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#define MXC_EMCC ((mxc_emcc_regs_t *)MXC_BASE_EMCC)
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/******************************************************************************/
426
/* XXX Actually reserved! */
427
#define MXC_BASE_RESERVED ((uint32_t)0x40035000UL)
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/******************************************************************************/
430
/* One Wire Master */
431
#define MXC_BASE_OWM ((uint32_t)0x4003D000UL)
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#define MXC_OWM ((mxc_owm_regs_t *)MXC_BASE_OWM)
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/******************************************************************************/
435
/* UART / Serial Port Interface */
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#define MXC_UART_INSTANCES (4)
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#define MXC_UART_FIFO_DEPTH (8)
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#define MXC_BASE_UART0 ((uint32_t)0x40042000UL)
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#define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0)
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#define MXC_BASE_UART1 ((uint32_t)0x40043000UL)
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#define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1)
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#define MXC_BASE_UART2 ((uint32_t)0x40044000UL)
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#define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2)
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#define MXC_BASE_UART3 ((uint32_t)0x40145000UL)
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#define MXC_UART3 ((mxc_uart_regs_t *)MXC_BASE_UART3)
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#define MXC_UART_GET_IRQ(i) \
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(IRQn_Type)((i) == 0 ? UART0_IRQn : \
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(i) == 1 ? UART1_IRQn : \
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(i) == 2 ? UART2_IRQn : \
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(i) == 3 ? UART3_IRQn : \
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0)
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#define MXC_UART_GET_BASE(i) \
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((i) == 0 ? MXC_BASE_UART0 : \
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(i) == 1 ? MXC_BASE_UART1 : \
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(i) == 2 ? MXC_BASE_UART2 : \
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(i) == 3 ? MXC_BASE_UART3 : \
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0)
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#define MXC_UART_GET_UART(i) \
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((i) == 0 ? MXC_UART0 : (i) == 1 ? MXC_UART1 : (i) == 2 ? MXC_UART2 : (i) == 3 ? MXC_UART3 : 0)
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#define MXC_UART_GET_IDX(p) \
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((p) == MXC_UART0 ? 0 : (p) == MXC_UART1 ? 1 : (p) == MXC_UART2 ? 2 : (p) == MXC_UART3 ? 3 : -1)
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468
/******************************************************************************/
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/* SPI */
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#define MXC_SPI_INSTANCES (3)
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#define MXC_SPI_SS_INSTANCES (4)
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#define MXC_SPI_FIFO_DEPTH (32)
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#define MXC_BASE_SPI0 ((uint32_t)0x40046000UL)
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#define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0)
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#define MXC_BASE_SPI1 ((uint32_t)0x40047000UL)
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#define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1)
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#define MXC_BASE_SPI2 ((uint32_t)0x40048000UL)
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#define MXC_SPI2 ((mxc_spi_regs_t *)MXC_BASE_SPI2)
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#define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : (p) == MXC_SPI1 ? 1 : (p) == MXC_SPI2 ? 2 : -1)
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#define MXC_SPI_GET_BASE(i) \
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((i) == 0 ? MXC_BASE_SPI0 : (i) == 1 ? MXC_BASE_SPI1 : (i) == 2 ? MXC_BASE_SPI2 : 0)
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#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : (i) == 1 ? MXC_SPI1 : (i) == 2 ? MXC_SPI2 : 0)
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#define MXC_SPI_GET_IRQ(i) \
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(IRQn_Type)((i) == 0 ? SPI3_IRQn : (i) == 1 ? SPI0_IRQn : (i) == 2 ? SPI1_IRQn : 0)
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/******************************************************************************/
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/* TRNG */
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#define MXC_BASE_TRNG ((uint32_t)0x4004D000UL)
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#define MXC_TRNG ((mxc_trng_regs_t *)MXC_BASE_TRNG)
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/******************************************************************************/
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#define MXC_BASE_I2S ((uint32_t)0x40060000UL)
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#define MXC_I2S ((mxc_i2s_regs_t *)MXC_BASE_I2S)
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500
/******************************************************************************/
501
/* Bit Shifting */
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#define MXC_F_BIT_0 (1 << 0)
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#define MXC_F_BIT_1 (1 << 1)
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#define MXC_F_BIT_2 (1 << 2)
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#define MXC_F_BIT_3 (1 << 3)
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#define MXC_F_BIT_4 (1 << 4)
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#define MXC_F_BIT_5 (1 << 5)
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#define MXC_F_BIT_6 (1 << 6)
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#define MXC_F_BIT_7 (1 << 7)
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#define MXC_F_BIT_8 (1 << 8)
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#define MXC_F_BIT_9 (1 << 9)
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#define MXC_F_BIT_10 (1 << 10)
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#define MXC_F_BIT_11 (1 << 11)
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#define MXC_F_BIT_12 (1 << 12)
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#define MXC_F_BIT_13 (1 << 13)
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#define MXC_F_BIT_14 (1 << 14)
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#define MXC_F_BIT_15 (1 << 15)
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#define MXC_F_BIT_16 (1 << 16)
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#define MXC_F_BIT_17 (1 << 17)
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#define MXC_F_BIT_18 (1 << 18)
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#define MXC_F_BIT_19 (1 << 19)
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#define MXC_F_BIT_20 (1 << 20)
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#define MXC_F_BIT_21 (1 << 21)
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#define MXC_F_BIT_22 (1 << 22)
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#define MXC_F_BIT_23 (1 << 23)
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#define MXC_F_BIT_24 (1 << 24)
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#define MXC_F_BIT_25 (1 << 25)
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#define MXC_F_BIT_26 (1 << 26)
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#define MXC_F_BIT_27 (1 << 27)
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#define MXC_F_BIT_28 (1 << 28)
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#define MXC_F_BIT_29 (1 << 29)
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#define MXC_F_BIT_30 (1 << 30)
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#define MXC_F_BIT_31 (1 << 31)
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535
/******************************************************************************/
536
/* Bit Banding */
537
#define BITBAND(reg, bit) \
538
((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg)&0x0fffffff) << 5) + \
539
((bit) << 2))
540
541
#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
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#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
543
#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
544
545
#define MXC_SETFIELD(reg, mask, setting) (reg = ((reg) & ~(mask)) | ((setting) & (mask)))
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547
/******************************************************************************/
548
/* SCB CPACR */
549
550
/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
551
#define SCB_CPACR_CP10_Pos 20
552
#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos)
553
#define SCB_CPACR_CP11_Pos 22
554
#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos)
556
#endif
// LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32675_INCLUDE_MAX32675_H_
CMSIS
Device
Maxim
MAX32675
Include
max32675.h
Generated on Fri Oct 25 2024 14:39:34 for MAX32675 Peripheral Driver API by
1.9.4
1.9.4