mcr_regs.h

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/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32680_INCLUDE_MCR_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32680_INCLUDE_MCR_REGS_H_
 
/* **** Includes **** */
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined (__ICCARM__)
  #pragma system_include
#endif
 
#if defined (__CC_ARM)
  #pragma anon_unions
#endif
/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif
#ifndef __R
#define __R  volatile const
#endif
 
/* **** Definitions **** */
 
typedef struct {
    __IO uint32_t eccen;                
    __IO uint32_t ipo_mtrim;            
    __IO uint32_t outen;                
    __IO uint32_t cmp_ctrl;             
    __IO uint32_t ctrl;                 
    __R  uint32_t rsv_0x14_0x1f[3];
    __IO uint32_t gpio3_ctrl;           
} mxc_mcr_regs_t;
 
/* Register offsets for module MCR */
#define MXC_R_MCR_ECCEN                    ((uint32_t)0x00000000UL) 
#define MXC_R_MCR_IPO_MTRIM                ((uint32_t)0x00000004UL) 
#define MXC_R_MCR_OUTEN                    ((uint32_t)0x00000008UL) 
#define MXC_R_MCR_CMP_CTRL                 ((uint32_t)0x0000000CUL) 
#define MXC_R_MCR_CTRL                     ((uint32_t)0x00000010UL) 
#define MXC_R_MCR_GPIO3_CTRL               ((uint32_t)0x00000020UL) 
#define MXC_F_MCR_ECCEN_RAM0_POS                       0 
#define MXC_F_MCR_ECCEN_RAM0                           ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_RAM0_POS)) 
#define MXC_F_MCR_IPO_MTRIM_MTRIM_POS                  0 
#define MXC_F_MCR_IPO_MTRIM_MTRIM                      ((uint32_t)(0xFFUL << MXC_F_MCR_IPO_MTRIM_MTRIM_POS)) 
#define MXC_F_MCR_IPO_MTRIM_TRIM_RANGE_POS             8 
#define MXC_F_MCR_IPO_MTRIM_TRIM_RANGE                 ((uint32_t)(0x1UL << MXC_F_MCR_IPO_MTRIM_TRIM_RANGE_POS)) 
#define MXC_F_MCR_OUTEN_SQWOUT_EN_POS                  0 
#define MXC_F_MCR_OUTEN_SQWOUT_EN                      ((uint32_t)(0x1UL << MXC_F_MCR_OUTEN_SQWOUT_EN_POS)) 
#define MXC_F_MCR_OUTEN_PDOWN_OUT_EN_POS               1 
#define MXC_F_MCR_OUTEN_PDOWN_OUT_EN                   ((uint32_t)(0x1UL << MXC_F_MCR_OUTEN_PDOWN_OUT_EN_POS)) 
#define MXC_F_MCR_CMP_CTRL_EN_POS                      0 
#define MXC_F_MCR_CMP_CTRL_EN                          ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_EN_POS)) 
#define MXC_F_MCR_CMP_CTRL_POL_POS                     5 
#define MXC_F_MCR_CMP_CTRL_POL                         ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_POL_POS)) 
#define MXC_F_MCR_CMP_CTRL_INT_EN_POS                  6 
#define MXC_F_MCR_CMP_CTRL_INT_EN                      ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_INT_EN_POS)) 
#define MXC_F_MCR_CMP_CTRL_OUT_POS                     14 
#define MXC_F_MCR_CMP_CTRL_OUT                         ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_OUT_POS)) 
#define MXC_F_MCR_CMP_CTRL_INT_FL_POS                  15 
#define MXC_F_MCR_CMP_CTRL_INT_FL                      ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_INT_FL_POS)) 
#define MXC_F_MCR_CTRL_INRO_EN_POS                     2 
#define MXC_F_MCR_CTRL_INRO_EN                         ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_INRO_EN_POS)) 
#define MXC_F_MCR_CTRL_ERTCO_EN_POS                    3 
#define MXC_F_MCR_CTRL_ERTCO_EN                        ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_ERTCO_EN_POS)) 
#define MXC_F_MCR_CTRL_SIMO_CLKSCL_EN_POS              8 
#define MXC_F_MCR_CTRL_SIMO_CLKSCL_EN                  ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_SIMO_CLKSCL_EN_POS)) 
#define MXC_F_MCR_CTRL_SIMO_RSTD_POS                   9 
#define MXC_F_MCR_CTRL_SIMO_RSTD                       ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_SIMO_RSTD_POS)) 
#define MXC_F_MCR_GPIO3_CTRL_P30_DO_POS                0 
#define MXC_F_MCR_GPIO3_CTRL_P30_DO                    ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P30_DO_POS)) 
#define MXC_F_MCR_GPIO3_CTRL_P30_OE_POS                1 
#define MXC_F_MCR_GPIO3_CTRL_P30_OE                    ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P30_OE_POS)) 
#define MXC_F_MCR_GPIO3_CTRL_P30_PE_POS                2 
#define MXC_F_MCR_GPIO3_CTRL_P30_PE                    ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P30_PE_POS)) 
#define MXC_F_MCR_GPIO3_CTRL_P30_IN_POS                3 
#define MXC_F_MCR_GPIO3_CTRL_P30_IN                    ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P30_IN_POS)) 
#define MXC_F_MCR_GPIO3_CTRL_P31_DO_POS                4 
#define MXC_F_MCR_GPIO3_CTRL_P31_DO                    ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P31_DO_POS)) 
#define MXC_F_MCR_GPIO3_CTRL_P31_OE_POS                5 
#define MXC_F_MCR_GPIO3_CTRL_P31_OE                    ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P31_OE_POS)) 
#define MXC_F_MCR_GPIO3_CTRL_P31_PE_POS                6 
#define MXC_F_MCR_GPIO3_CTRL_P31_PE                    ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P31_PE_POS)) 
#define MXC_F_MCR_GPIO3_CTRL_P31_IN_POS                7 
#define MXC_F_MCR_GPIO3_CTRL_P31_IN                    ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P31_IN_POS)) 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32680_INCLUDE_MCR_REGS_H_