mxc_sys.h

/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32680_MXC_SYS_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32680_MXC_SYS_H_
 
#include "mxc_device.h"
#include "gcr_regs.h"
#include "lpgcr_regs.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
typedef enum {
    MXC_SYS_RESET0_DMA = MXC_F_GCR_RST0_DMA_POS, 
    MXC_SYS_RESET0_WDT0 = MXC_F_GCR_RST0_WDT0_POS, 
    MXC_SYS_RESET0_GPIO0 = MXC_F_GCR_RST0_GPIO0_POS, 
    MXC_SYS_RESET0_GPIO1 = MXC_F_GCR_RST0_GPIO1_POS, 
    MXC_SYS_RESET0_TMR0 = MXC_F_GCR_RST0_TMR0_POS, 
    MXC_SYS_RESET0_TMR1 = MXC_F_GCR_RST0_TMR1_POS, 
    MXC_SYS_RESET0_TMR2 = MXC_F_GCR_RST0_TMR2_POS, 
    MXC_SYS_RESET0_TMR3 = MXC_F_GCR_RST0_TMR3_POS, 
    MXC_SYS_RESET0_UART0 = MXC_F_GCR_RST0_UART0_POS, 
    MXC_SYS_RESET0_UART1 = MXC_F_GCR_RST0_UART1_POS, 
    MXC_SYS_RESET0_SPI1 = MXC_F_GCR_RST0_SPI1_POS, 
    MXC_SYS_RESET0_I2C0 = MXC_F_GCR_RST0_I2C0_POS, 
    MXC_SYS_RESET0_RTC = MXC_F_GCR_RST0_RTC_POS, 
    MXC_SYS_RESET0_SMPHR = MXC_F_GCR_RST0_SMPHR_POS, 
    MXC_SYS_RESET0_TRNG = MXC_F_GCR_RST0_TRNG_POS, 
    MXC_SYS_RESET0_CNN = MXC_F_GCR_RST0_CNN_POS, 
    MXC_SYS_RESET0_ADC = MXC_F_GCR_RST0_ADC_POS, 
    MXC_SYS_RESET0_UART2 = MXC_F_GCR_RST0_UART2_POS, 
    MXC_SYS_RESET0_SOFT = MXC_F_GCR_RST0_SOFT_POS, 
    MXC_SYS_RESET0_PERIPH = MXC_F_GCR_RST0_PERIPH_POS, 
    MXC_SYS_RESET0_SYS = MXC_F_GCR_RST0_SYS_POS, 
    /* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */
    MXC_SYS_RESET1_I2C1 = (MXC_F_GCR_RST1_I2C1_POS + 32), 
    MXC_SYS_RESET1_PT = (MXC_F_GCR_RST1_PT_POS + 32), 
    MXC_SYS_RESET1_OWM = (MXC_F_GCR_RST1_OWM_POS + 32), 
    MXC_SYS_RESET1_CRC = (MXC_F_GCR_RST1_CRC_POS + 32), 
    MXC_SYS_RESET1_AES = (MXC_F_GCR_RST1_AES_POS + 32), 
    MXC_SYS_RESET1_SMPHR = (MXC_F_GCR_RST1_SMPHR_POS + 32), 
    MXC_SYS_RESET1_I2C2 = (MXC_F_GCR_RST1_I2C2_POS + 32), 
    MXC_SYS_RESET1_I2S = (MXC_F_GCR_RST1_I2S_POS + 32), 
    // MXC_SYS_RESET1_BTLE      = (MXC_F_GCR_RST1_BTLE_POS + 32),     /**< Reset BTLE*/
    MXC_SYS_RESET1_DVS = (MXC_F_GCR_RST1_DVS_POS + 32), 
    MXC_SYS_RESET1_SIMO = (MXC_F_GCR_RST1_SIMO_POS + 32), 
    MXC_SYS_RESET1_SPI0 = (MXC_F_GCR_RST1_SPI0_POS + 32), 
    MXC_SYS_RESET1_CPU1 = (MXC_F_GCR_RST1_CPU1_POS + 32), 
    /* LPGCR RESET Below this line we add 64 to separate LPGCR and GCR */
    MXC_SYS_RESET_GPIO2 = (MXC_F_LPGCR_RST_GPIO2_POS + 64), 
    MXC_SYS_RESET_WDT1 = (MXC_F_LPGCR_RST_WDT1_POS + 64), 
    MXC_SYS_RESET_TMR4 = (MXC_F_LPGCR_RST_TMR4_POS + 64), 
    MXC_SYS_RESET_TMR5 = (MXC_F_LPGCR_RST_TMR5_POS + 64), 
    MXC_SYS_RESET_UART3 = (MXC_F_LPGCR_RST_UART3_POS + 64), 
    MXC_SYS_RESET_LPCOMP = (MXC_F_LPGCR_RST_LPCOMP_POS + 64), 
} mxc_sys_reset_t;
 
typedef enum {
    MXC_SYS_PERIPH_CLOCK_GPIO0 =
        MXC_F_GCR_PCLKDIS0_GPIO0_POS, 
    MXC_SYS_PERIPH_CLOCK_GPIO1 =
        MXC_F_GCR_PCLKDIS0_GPIO1_POS, 
    MXC_SYS_PERIPH_CLOCK_DMA =
        MXC_F_GCR_PCLKDIS0_DMA_POS, 
    MXC_SYS_PERIPH_CLOCK_SPI1 =
        MXC_F_GCR_PCLKDIS0_SPI1_POS, 
    MXC_SYS_PERIPH_CLOCK_UART0 =
        MXC_F_GCR_PCLKDIS0_UART0_POS, 
    MXC_SYS_PERIPH_CLOCK_UART1 =
        MXC_F_GCR_PCLKDIS0_UART1_POS, 
    MXC_SYS_PERIPH_CLOCK_I2C0 =
        MXC_F_GCR_PCLKDIS0_I2C0_POS, 
    MXC_SYS_PERIPH_CLOCK_TMR0 =
        MXC_F_GCR_PCLKDIS0_TMR0_POS, 
    MXC_SYS_PERIPH_CLOCK_TMR1 =
        MXC_F_GCR_PCLKDIS0_TMR1_POS, 
    MXC_SYS_PERIPH_CLOCK_TMR2 =
        MXC_F_GCR_PCLKDIS0_TMR2_POS, 
    MXC_SYS_PERIPH_CLOCK_TMR3 =
        MXC_F_GCR_PCLKDIS0_TMR3_POS, 
    MXC_SYS_PERIPH_CLOCK_ADC =
        MXC_F_GCR_PCLKDIS0_ADC_POS, 
    MXC_SYS_PERIPH_CLOCK_CNN =
        MXC_F_GCR_PCLKDIS0_CNN_POS, 
    MXC_SYS_PERIPH_CLOCK_I2C1 =
        MXC_F_GCR_PCLKDIS0_I2C1_POS, 
    MXC_SYS_PERIPH_CLOCK_PT = MXC_F_GCR_PCLKDIS0_PT_POS, 
    /* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */
    MXC_SYS_PERIPH_CLOCK_UART2 =
        (MXC_F_GCR_PCLKDIS1_UART2_POS + 32), 
    MXC_SYS_PERIPH_CLOCK_TRNG =
        (MXC_F_GCR_PCLKDIS1_TRNG_POS + 32), 
    MXC_SYS_PERIPH_CLOCK_SMPHR =
        (MXC_F_GCR_PCLKDIS1_SMPHR_POS + 32), 
    MXC_SYS_PERIPH_CLOCK_OWIRE =
        (MXC_F_GCR_PCLKDIS1_OWM_POS + 32), 
    MXC_SYS_PERIPH_CLOCK_CRC =
        (MXC_F_GCR_PCLKDIS1_CRC_POS + 32), 
    MXC_SYS_PERIPH_CLOCK_AES =
        (MXC_F_GCR_PCLKDIS1_AES_POS + 32), 
    MXC_SYS_PERIPH_CLOCK_I2S =
        (MXC_F_GCR_PCLKDIS1_I2S_POS + 32), 
    MXC_SYS_PERIPH_CLOCK_SPI0 =
        (MXC_F_GCR_PCLKDIS1_SPI0_POS + 32), 
    MXC_SYS_PERIPH_CLOCK_I2C2 =
        (MXC_F_GCR_PCLKDIS1_I2C2_POS + 32), 
    MXC_SYS_PERIPH_CLOCK_WDT0 =
        (MXC_F_GCR_PCLKDIS1_WDT0_POS + 32), 
    MXC_SYS_PERIPH_CLOCK_CPU1 =
        (MXC_F_GCR_PCLKDIS1_CPU1_POS + 32), 
    /* LPGCR PCLKDIS Below this line we add 64 to seperate GCR and LPGCR registers */
    MXC_SYS_PERIPH_CLOCK_GPIO2 =
        (MXC_F_LPGCR_PCLKDIS_GPIO2_POS + 64), 
    MXC_SYS_PERIPH_CLOCK_WDT1 =
        (MXC_F_LPGCR_PCLKDIS_WDT1_POS + 64), 
    MXC_SYS_PERIPH_CLOCK_TMR4 =
        (MXC_F_LPGCR_PCLKDIS_TMR4_POS + 64), 
    MXC_SYS_PERIPH_CLOCK_TMR5 =
        (MXC_F_LPGCR_PCLKDIS_TMR5_POS + 64), 
    MXC_SYS_PERIPH_CLOCK_UART3 =
        (MXC_F_LPGCR_PCLKDIS_UART3_POS + 64), 
    MXC_SYS_PERIPH_CLOCK_LPCOMP =
        (MXC_F_LPGCR_PCLKDIS_LPCOMP_POS + 64), 
} mxc_sys_periph_clock_t;
 
typedef enum {
    MXC_SYS_CLOCK_ISO =
        MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO, 
    MXC_SYS_CLOCK_IPO =
        MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO, 
    MXC_SYS_CLOCK_IBRO =
        MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO, 
    MXC_SYS_CLOCK_ERFO =
        MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO, 
    MXC_SYS_CLOCK_INRO =
        MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO, 
    MXC_SYS_CLOCK_ERTCO =
        MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO, 
    MXC_SYS_CLOCK_EXTCLK =
        MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK 
} mxc_sys_system_clock_t;
 
typedef enum {
    MXC_SYS_CLOCK_DIV_1 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1,
    MXC_SYS_CLOCK_DIV_2 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2,
    MXC_SYS_CLOCK_DIV_4 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4,
    MXC_SYS_CLOCK_DIV_8 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8,
    MXC_SYS_CLOCK_DIV_16 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16,
    MXC_SYS_CLOCK_DIV_32 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32,
    MXC_SYS_CLOCK_DIV_64 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64,
    MXC_SYS_CLOCK_DIV_128 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128
} mxc_sys_system_clock_div_t;
 
#define MXC_SYS_USN_CHECKSUM_LEN 16 // Length of the USN + padding for checksum compute
#define MXC_SYS_USN_CSUM_FIELD_LEN 2 // Size of the checksum field in the USN
#define MXC_SYS_USN_LEN 13 // Size of the USN including the checksum
 
/***** Function Prototypes *****/
 
typedef struct {
    int ie_status;
    int in_critical;
} mxc_crit_state_t;
 
static mxc_crit_state_t _state = { .ie_status = (int)0xFFFFFFFF, .in_critical = 0 };
 
static inline void _mxc_crit_get_state(void)
{
#ifndef __riscv
    /*
        On ARM M the 0th bit of the Priority Mask register indicates
        whether interrupts are enabled or not.
 
        0 = enabled
        1 = disabled
    */
    uint32_t primask = __get_PRIMASK();
    _state.ie_status = (primask == 0);
#else
    /*
        On RISC-V bit position 3 (Machine Interrupt Enable) of the
        mstatus register indicates whether interrupts are enabled.
 
        0 = disabled
        1 = enabled
    */
    uint32_t mstatus = get_mstatus();
    _state.ie_status = ((mstatus & (1 << 3)) != 0);
#endif
}
 
static inline void MXC_SYS_Crit_Enter(void)
{
    _mxc_crit_get_state();
    if (_state.ie_status)
        __disable_irq();
    _state.in_critical = 1;
}
 
static inline void MXC_SYS_Crit_Exit(void)
{
    if (_state.ie_status) {
        __enable_irq();
    }
    _state.in_critical = 0;
    _mxc_crit_get_state();
    /*
        ^ Reset the state again to prevent edge case
        where interrupts get disabled, then Crit_Exit() gets
        called, which would inadvertently re-enable interrupts
        from old state.
    */
}
 
static inline int MXC_SYS_In_Crit_Section(void)
{
    return _state.in_critical;
}
 
// clang-format off
#define MXC_CRITICAL(code) {\
    MXC_SYS_Crit_Enter();\
    code;\
    MXC_SYS_Crit_Exit();\
}
// clang-format on
 
int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum);
 
int MXC_SYS_IsClockEnabled(mxc_sys_periph_clock_t clock);
 
void MXC_SYS_ClockDisable(mxc_sys_periph_clock_t clock);
 
void MXC_SYS_ClockEnable(mxc_sys_periph_clock_t clock);
 
void MXC_SYS_RTCClockEnable(void);
 
int MXC_SYS_RTCClockDisable(void);
 
int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock);
 
int MXC_SYS_ClockSourceDisable(mxc_sys_system_clock_t clock);
 
int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock);
 
void MXC_SYS_SetClockDiv(mxc_sys_system_clock_div_t div);
 
mxc_sys_system_clock_div_t MXC_SYS_GetClockDiv(void);
 
int MXC_SYS_Clock_Timeout(uint32_t ready);
void MXC_SYS_Reset_Periph(mxc_sys_reset_t reset);
 
void MXC_SYS_RISCVRun(void);
 
void MXC_SYS_RISCVShutdown(void);
 
uint32_t MXC_SYS_RiscVClockRate(void);
 
int MXC_SYS_LockDAP_Permanent(void);
 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32680_MXC_SYS_H_