Documentation/MAX32690/dma__regs_8h_source.html

/******************************************************************************

 *

 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by

 * Analog Devices, Inc.),

 * Copyright (C) 2023-2024 Analog Devices, Inc.

 *

 * Licensed under the Apache License, Version 2.0 (the "License");

 * you may not use this file except in compliance with the License.

 * You may obtain a copy of the License at

 *

 *     http://www.apache.org/licenses/LICENSE-2.0

 *

 * Unless required by applicable law or agreed to in writing, software

 * distributed under the License is distributed on an "AS IS" BASIS,

 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

 * See the License for the specific language governing permissions and

 * limitations under the License.

 *

 ******************************************************************************/


#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_DMA_REGS_H_

#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_DMA_REGS_H_


/* **** Includes **** */

#include <stdint.h>


#ifdef __cplusplus

extern "C" {

#endif


#if defined (__ICCARM__)

  #pragma system_include

#endif


#if defined (__CC_ARM)

  #pragma anon_unions

#endif

/*

    If types are not defined elsewhere (CMSIS) define them here

*/

#ifndef __IO

#define __IO volatile

#endif

#ifndef __I

#define __I  volatile const

#endif

#ifndef __O

#define __O  volatile

#endif

#ifndef __R

#define __R  volatile const

#endif


/* **** Definitions **** */


typedef struct {

    __IO uint32_t ctrl;

    __IO uint32_t status;

    __IO uint32_t src;

    __IO uint32_t dst;

    __IO uint32_t cnt;

    __IO uint32_t srcrld;

    __IO uint32_t dstrld;

    __IO uint32_t cntrld;

} mxc_dma_ch_regs_t;


typedef struct {

    __IO uint32_t inten;

    __I  uint32_t intfl;

    __R  uint32_t rsv_0x8_0xff[62];

    __IO mxc_dma_ch_regs_t    ch[16];

} mxc_dma_regs_t;


/* Register offsets for module DMA */

#define MXC_R_DMA_CTRL                     ((uint32_t)0x00000000UL)

#define MXC_R_DMA_STATUS                   ((uint32_t)0x00000004UL)

#define MXC_R_DMA_SRC                      ((uint32_t)0x00000008UL)

#define MXC_R_DMA_DST                      ((uint32_t)0x0000000CUL)

#define MXC_R_DMA_CNT                      ((uint32_t)0x00000010UL)

#define MXC_R_DMA_SRCRLD                   ((uint32_t)0x00000014UL)

#define MXC_R_DMA_DSTRLD                   ((uint32_t)0x00000018UL)

#define MXC_R_DMA_CNTRLD                   ((uint32_t)0x0000001CUL)

#define MXC_R_DMA_INTEN                    ((uint32_t)0x00000000UL)

#define MXC_R_DMA_INTFL                    ((uint32_t)0x00000004UL)

#define MXC_R_DMA_CH                       ((uint32_t)0x00000100UL)

#define MXC_F_DMA_INTEN_CH0_POS                        0

#define MXC_F_DMA_INTEN_CH0                            ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH0_POS))

#define MXC_F_DMA_INTEN_CH1_POS                        1

#define MXC_F_DMA_INTEN_CH1                            ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH1_POS))

#define MXC_F_DMA_INTEN_CH2_POS                        2

#define MXC_F_DMA_INTEN_CH2                            ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH2_POS))

#define MXC_F_DMA_INTEN_CH3_POS                        3

#define MXC_F_DMA_INTEN_CH3                            ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH3_POS))

#define MXC_F_DMA_INTEN_CH4_POS                        4

#define MXC_F_DMA_INTEN_CH4                            ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH4_POS))

#define MXC_F_DMA_INTEN_CH5_POS                        5

#define MXC_F_DMA_INTEN_CH5                            ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH5_POS))

#define MXC_F_DMA_INTEN_CH6_POS                        6

#define MXC_F_DMA_INTEN_CH6                            ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH6_POS))

#define MXC_F_DMA_INTEN_CH7_POS                        7

#define MXC_F_DMA_INTEN_CH7                            ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH7_POS))

#define MXC_F_DMA_INTEN_CH8_POS                        8

#define MXC_F_DMA_INTEN_CH8                            ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH8_POS))

#define MXC_F_DMA_INTEN_CH9_POS                        9

#define MXC_F_DMA_INTEN_CH9                            ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH9_POS))

#define MXC_F_DMA_INTEN_CH10_POS                       10

#define MXC_F_DMA_INTEN_CH10                           ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH10_POS))

#define MXC_F_DMA_INTEN_CH11_POS                       11

#define MXC_F_DMA_INTEN_CH11                           ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH11_POS))

#define MXC_F_DMA_INTEN_CH12_POS                       12

#define MXC_F_DMA_INTEN_CH12                           ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH12_POS))

#define MXC_F_DMA_INTEN_CH13_POS                       13

#define MXC_F_DMA_INTEN_CH13                           ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH13_POS))

#define MXC_F_DMA_INTEN_CH14_POS                       14

#define MXC_F_DMA_INTEN_CH14                           ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH14_POS))

#define MXC_F_DMA_INTEN_CH15_POS                       15

#define MXC_F_DMA_INTEN_CH15                           ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH15_POS))

#define MXC_F_DMA_INTFL_CH0_POS                        0

#define MXC_F_DMA_INTFL_CH0                            ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH0_POS))

#define MXC_F_DMA_INTFL_CH1_POS                        1

#define MXC_F_DMA_INTFL_CH1                            ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH1_POS))

#define MXC_F_DMA_INTFL_CH2_POS                        2

#define MXC_F_DMA_INTFL_CH2                            ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH2_POS))

#define MXC_F_DMA_INTFL_CH3_POS                        3

#define MXC_F_DMA_INTFL_CH3                            ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH3_POS))

#define MXC_F_DMA_INTFL_CH4_POS                        4

#define MXC_F_DMA_INTFL_CH4                            ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH4_POS))

#define MXC_F_DMA_INTFL_CH5_POS                        5

#define MXC_F_DMA_INTFL_CH5                            ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH5_POS))

#define MXC_F_DMA_INTFL_CH6_POS                        6

#define MXC_F_DMA_INTFL_CH6                            ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH6_POS))

#define MXC_F_DMA_INTFL_CH7_POS                        7

#define MXC_F_DMA_INTFL_CH7                            ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH7_POS))

#define MXC_F_DMA_INTFL_CH8_POS                        8

#define MXC_F_DMA_INTFL_CH8                            ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH8_POS))

#define MXC_F_DMA_INTFL_CH9_POS                        9

#define MXC_F_DMA_INTFL_CH9                            ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH9_POS))

#define MXC_F_DMA_INTFL_CH10_POS                       10

#define MXC_F_DMA_INTFL_CH10                           ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH10_POS))

#define MXC_F_DMA_INTFL_CH11_POS                       11

#define MXC_F_DMA_INTFL_CH11                           ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH11_POS))

#define MXC_F_DMA_INTFL_CH12_POS                       12

#define MXC_F_DMA_INTFL_CH12                           ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH12_POS))

#define MXC_F_DMA_INTFL_CH13_POS                       13

#define MXC_F_DMA_INTFL_CH13                           ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH13_POS))

#define MXC_F_DMA_INTFL_CH14_POS                       14

#define MXC_F_DMA_INTFL_CH14                           ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH14_POS))

#define MXC_F_DMA_INTFL_CH15_POS                       15

#define MXC_F_DMA_INTFL_CH15                           ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH15_POS))

#define MXC_F_DMA_CTRL_EN_POS                          0

#define MXC_F_DMA_CTRL_EN                              ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_EN_POS))

#define MXC_F_DMA_CTRL_RLDEN_POS                       1

#define MXC_F_DMA_CTRL_RLDEN                           ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_RLDEN_POS))

#define MXC_F_DMA_CTRL_PRI_POS                         2

#define MXC_F_DMA_CTRL_PRI                             ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_PRI_POS))

#define MXC_V_DMA_CTRL_PRI_HIGH                        ((uint32_t)0x0UL)

#define MXC_S_DMA_CTRL_PRI_HIGH                        (MXC_V_DMA_CTRL_PRI_HIGH << MXC_F_DMA_CTRL_PRI_POS)

#define MXC_V_DMA_CTRL_PRI_MEDHIGH                     ((uint32_t)0x1UL)

#define MXC_S_DMA_CTRL_PRI_MEDHIGH                     (MXC_V_DMA_CTRL_PRI_MEDHIGH << MXC_F_DMA_CTRL_PRI_POS)

#define MXC_V_DMA_CTRL_PRI_MEDLOW                      ((uint32_t)0x2UL)

#define MXC_S_DMA_CTRL_PRI_MEDLOW                      (MXC_V_DMA_CTRL_PRI_MEDLOW << MXC_F_DMA_CTRL_PRI_POS)

#define MXC_V_DMA_CTRL_PRI_LOW                         ((uint32_t)0x3UL)

#define MXC_S_DMA_CTRL_PRI_LOW                         (MXC_V_DMA_CTRL_PRI_LOW << MXC_F_DMA_CTRL_PRI_POS)

#define MXC_F_DMA_CTRL_REQUEST_POS                     4

#define MXC_F_DMA_CTRL_REQUEST                         ((uint32_t)(0x3FUL << MXC_F_DMA_CTRL_REQUEST_POS))

#define MXC_V_DMA_CTRL_REQUEST_MEMTOMEM                ((uint32_t)0x0UL)

#define MXC_S_DMA_CTRL_REQUEST_MEMTOMEM                (MXC_V_DMA_CTRL_REQUEST_MEMTOMEM << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_SPI0RX                  ((uint32_t)0x1UL)

#define MXC_S_DMA_CTRL_REQUEST_SPI0RX                  (MXC_V_DMA_CTRL_REQUEST_SPI0RX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_SPI1RX                  ((uint32_t)0x2UL)

#define MXC_S_DMA_CTRL_REQUEST_SPI1RX                  (MXC_V_DMA_CTRL_REQUEST_SPI1RX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_SPI2RX                  ((uint32_t)0x3UL)

#define MXC_S_DMA_CTRL_REQUEST_SPI2RX                  (MXC_V_DMA_CTRL_REQUEST_SPI2RX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_UART0RX                 ((uint32_t)0x4UL)

#define MXC_S_DMA_CTRL_REQUEST_UART0RX                 (MXC_V_DMA_CTRL_REQUEST_UART0RX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_UART1RX                 ((uint32_t)0x5UL)

#define MXC_S_DMA_CTRL_REQUEST_UART1RX                 (MXC_V_DMA_CTRL_REQUEST_UART1RX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_CAN0RX                  ((uint32_t)0x6UL)

#define MXC_S_DMA_CTRL_REQUEST_CAN0RX                  (MXC_V_DMA_CTRL_REQUEST_CAN0RX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_I2C0RX                  ((uint32_t)0x7UL)

#define MXC_S_DMA_CTRL_REQUEST_I2C0RX                  (MXC_V_DMA_CTRL_REQUEST_I2C0RX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_I2C1RX                  ((uint32_t)0x8UL)

#define MXC_S_DMA_CTRL_REQUEST_I2C1RX                  (MXC_V_DMA_CTRL_REQUEST_I2C1RX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_ADC                     ((uint32_t)0x9UL)

#define MXC_S_DMA_CTRL_REQUEST_ADC                     (MXC_V_DMA_CTRL_REQUEST_ADC << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_I2C2RX                  ((uint32_t)0xAUL)

#define MXC_S_DMA_CTRL_REQUEST_I2C2RX                  (MXC_V_DMA_CTRL_REQUEST_I2C2RX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_UART2RX                 ((uint32_t)0xEUL)

#define MXC_S_DMA_CTRL_REQUEST_UART2RX                 (MXC_V_DMA_CTRL_REQUEST_UART2RX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_SPI3RX                  ((uint32_t)0xFUL)

#define MXC_S_DMA_CTRL_REQUEST_SPI3RX                  (MXC_V_DMA_CTRL_REQUEST_SPI3RX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_SPI4RX                  ((uint32_t)0x10UL)

#define MXC_S_DMA_CTRL_REQUEST_SPI4RX                  (MXC_V_DMA_CTRL_REQUEST_SPI4RX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_USBRX1                  ((uint32_t)0x11UL)

#define MXC_S_DMA_CTRL_REQUEST_USBRX1                  (MXC_V_DMA_CTRL_REQUEST_USBRX1 << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_USBRX2                  ((uint32_t)0x12UL)

#define MXC_S_DMA_CTRL_REQUEST_USBRX2                  (MXC_V_DMA_CTRL_REQUEST_USBRX2 << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_USBRX3                  ((uint32_t)0x13UL)

#define MXC_S_DMA_CTRL_REQUEST_USBRX3                  (MXC_V_DMA_CTRL_REQUEST_USBRX3 << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_USBRX4                  ((uint32_t)0x14UL)

#define MXC_S_DMA_CTRL_REQUEST_USBRX4                  (MXC_V_DMA_CTRL_REQUEST_USBRX4 << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_USBRX5                  ((uint32_t)0x15UL)

#define MXC_S_DMA_CTRL_REQUEST_USBRX5                  (MXC_V_DMA_CTRL_REQUEST_USBRX5 << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_USBRX6                  ((uint32_t)0x16UL)

#define MXC_S_DMA_CTRL_REQUEST_USBRX6                  (MXC_V_DMA_CTRL_REQUEST_USBRX6 << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_USBRX7                  ((uint32_t)0x17UL)

#define MXC_S_DMA_CTRL_REQUEST_USBRX7                  (MXC_V_DMA_CTRL_REQUEST_USBRX7 << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_USBRX8                  ((uint32_t)0x18UL)

#define MXC_S_DMA_CTRL_REQUEST_USBRX8                  (MXC_V_DMA_CTRL_REQUEST_USBRX8 << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_USBRX9                  ((uint32_t)0x19UL)

#define MXC_S_DMA_CTRL_REQUEST_USBRX9                  (MXC_V_DMA_CTRL_REQUEST_USBRX9 << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_USBRX10                 ((uint32_t)0x1AUL)

#define MXC_S_DMA_CTRL_REQUEST_USBRX10                 (MXC_V_DMA_CTRL_REQUEST_USBRX10 << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_USBRX11                 ((uint32_t)0x1BUL)

#define MXC_S_DMA_CTRL_REQUEST_USBRX11                 (MXC_V_DMA_CTRL_REQUEST_USBRX11 << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_UART3RX                 ((uint32_t)0x1CUL)

#define MXC_S_DMA_CTRL_REQUEST_UART3RX                 (MXC_V_DMA_CTRL_REQUEST_UART3RX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_I2SRX                   ((uint32_t)0x1EUL)

#define MXC_S_DMA_CTRL_REQUEST_I2SRX                   (MXC_V_DMA_CTRL_REQUEST_I2SRX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_CAN1RX                  ((uint32_t)0x1FUL)

#define MXC_S_DMA_CTRL_REQUEST_CAN1RX                  (MXC_V_DMA_CTRL_REQUEST_CAN1RX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_SPI0TX                  ((uint32_t)0x21UL)

#define MXC_S_DMA_CTRL_REQUEST_SPI0TX                  (MXC_V_DMA_CTRL_REQUEST_SPI0TX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_SPI1TX                  ((uint32_t)0x22UL)

#define MXC_S_DMA_CTRL_REQUEST_SPI1TX                  (MXC_V_DMA_CTRL_REQUEST_SPI1TX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_SPI2TX                  ((uint32_t)0x23UL)

#define MXC_S_DMA_CTRL_REQUEST_SPI2TX                  (MXC_V_DMA_CTRL_REQUEST_SPI2TX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_UART0TX                 ((uint32_t)0x24UL)

#define MXC_S_DMA_CTRL_REQUEST_UART0TX                 (MXC_V_DMA_CTRL_REQUEST_UART0TX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_UART1TX                 ((uint32_t)0x25UL)

#define MXC_S_DMA_CTRL_REQUEST_UART1TX                 (MXC_V_DMA_CTRL_REQUEST_UART1TX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_CAN0TX                  ((uint32_t)0x26UL)

#define MXC_S_DMA_CTRL_REQUEST_CAN0TX                  (MXC_V_DMA_CTRL_REQUEST_CAN0TX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_I2C0TX                  ((uint32_t)0x27UL)

#define MXC_S_DMA_CTRL_REQUEST_I2C0TX                  (MXC_V_DMA_CTRL_REQUEST_I2C0TX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_I2C1TX                  ((uint32_t)0x28UL)

#define MXC_S_DMA_CTRL_REQUEST_I2C1TX                  (MXC_V_DMA_CTRL_REQUEST_I2C1TX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_I2C2TX                  ((uint32_t)0x2AUL)

#define MXC_S_DMA_CTRL_REQUEST_I2C2TX                  (MXC_V_DMA_CTRL_REQUEST_I2C2TX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_UART2TX                 ((uint32_t)0x2EUL)

#define MXC_S_DMA_CTRL_REQUEST_UART2TX                 (MXC_V_DMA_CTRL_REQUEST_UART2TX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_SPI3TX                  ((uint32_t)0x2FUL)

#define MXC_S_DMA_CTRL_REQUEST_SPI3TX                  (MXC_V_DMA_CTRL_REQUEST_SPI3TX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_SPI4TX                  ((uint32_t)0x30UL)

#define MXC_S_DMA_CTRL_REQUEST_SPI4TX                  (MXC_V_DMA_CTRL_REQUEST_SPI4TX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_USBTX1                  ((uint32_t)0x31UL)

#define MXC_S_DMA_CTRL_REQUEST_USBTX1                  (MXC_V_DMA_CTRL_REQUEST_USBTX1 << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_USBTX2                  ((uint32_t)0x32UL)

#define MXC_S_DMA_CTRL_REQUEST_USBTX2                  (MXC_V_DMA_CTRL_REQUEST_USBTX2 << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_USBTX3                  ((uint32_t)0x33UL)

#define MXC_S_DMA_CTRL_REQUEST_USBTX3                  (MXC_V_DMA_CTRL_REQUEST_USBTX3 << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_USBTX4                  ((uint32_t)0x34UL)

#define MXC_S_DMA_CTRL_REQUEST_USBTX4                  (MXC_V_DMA_CTRL_REQUEST_USBTX4 << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_USBTX5                  ((uint32_t)0x35UL)

#define MXC_S_DMA_CTRL_REQUEST_USBTX5                  (MXC_V_DMA_CTRL_REQUEST_USBTX5 << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_USBTX6                  ((uint32_t)0x36UL)

#define MXC_S_DMA_CTRL_REQUEST_USBTX6                  (MXC_V_DMA_CTRL_REQUEST_USBTX6 << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_USBTX7                  ((uint32_t)0x37UL)

#define MXC_S_DMA_CTRL_REQUEST_USBTX7                  (MXC_V_DMA_CTRL_REQUEST_USBTX7 << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_USBTX8                  ((uint32_t)0x38UL)

#define MXC_S_DMA_CTRL_REQUEST_USBTX8                  (MXC_V_DMA_CTRL_REQUEST_USBTX8 << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_USBTX9                  ((uint32_t)0x39UL)

#define MXC_S_DMA_CTRL_REQUEST_USBTX9                  (MXC_V_DMA_CTRL_REQUEST_USBTX9 << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_USBTX10                 ((uint32_t)0x3AUL)

#define MXC_S_DMA_CTRL_REQUEST_USBTX10                 (MXC_V_DMA_CTRL_REQUEST_USBTX10 << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_USBTX11                 ((uint32_t)0x3BUL)

#define MXC_S_DMA_CTRL_REQUEST_USBTX11                 (MXC_V_DMA_CTRL_REQUEST_USBTX11 << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_UART3TX                 ((uint32_t)0x3CUL)

#define MXC_S_DMA_CTRL_REQUEST_UART3TX                 (MXC_V_DMA_CTRL_REQUEST_UART3TX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_I2STX                   ((uint32_t)0x3EUL)

#define MXC_S_DMA_CTRL_REQUEST_I2STX                   (MXC_V_DMA_CTRL_REQUEST_I2STX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_V_DMA_CTRL_REQUEST_CAN1TX                  ((uint32_t)0x3FUL)

#define MXC_S_DMA_CTRL_REQUEST_CAN1TX                  (MXC_V_DMA_CTRL_REQUEST_CAN1TX << MXC_F_DMA_CTRL_REQUEST_POS)

#define MXC_F_DMA_CTRL_TO_WAIT_POS                     10

#define MXC_F_DMA_CTRL_TO_WAIT                         ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_TO_WAIT_POS))

#define MXC_F_DMA_CTRL_TO_PER_POS                      11

#define MXC_F_DMA_CTRL_TO_PER                          ((uint32_t)(0x7UL << MXC_F_DMA_CTRL_TO_PER_POS))

#define MXC_V_DMA_CTRL_TO_PER_TO4                      ((uint32_t)0x0UL)

#define MXC_S_DMA_CTRL_TO_PER_TO4                      (MXC_V_DMA_CTRL_TO_PER_TO4 << MXC_F_DMA_CTRL_TO_PER_POS)

#define MXC_V_DMA_CTRL_TO_PER_TO8                      ((uint32_t)0x1UL)

#define MXC_S_DMA_CTRL_TO_PER_TO8                      (MXC_V_DMA_CTRL_TO_PER_TO8 << MXC_F_DMA_CTRL_TO_PER_POS)

#define MXC_V_DMA_CTRL_TO_PER_TO16                     ((uint32_t)0x2UL)

#define MXC_S_DMA_CTRL_TO_PER_TO16                     (MXC_V_DMA_CTRL_TO_PER_TO16 << MXC_F_DMA_CTRL_TO_PER_POS)

#define MXC_V_DMA_CTRL_TO_PER_TO32                     ((uint32_t)0x3UL)

#define MXC_S_DMA_CTRL_TO_PER_TO32                     (MXC_V_DMA_CTRL_TO_PER_TO32 << MXC_F_DMA_CTRL_TO_PER_POS)

#define MXC_V_DMA_CTRL_TO_PER_TO64                     ((uint32_t)0x4UL)

#define MXC_S_DMA_CTRL_TO_PER_TO64                     (MXC_V_DMA_CTRL_TO_PER_TO64 << MXC_F_DMA_CTRL_TO_PER_POS)

#define MXC_V_DMA_CTRL_TO_PER_TO128                    ((uint32_t)0x5UL)

#define MXC_S_DMA_CTRL_TO_PER_TO128                    (MXC_V_DMA_CTRL_TO_PER_TO128 << MXC_F_DMA_CTRL_TO_PER_POS)

#define MXC_V_DMA_CTRL_TO_PER_TO256                    ((uint32_t)0x6UL)

#define MXC_S_DMA_CTRL_TO_PER_TO256                    (MXC_V_DMA_CTRL_TO_PER_TO256 << MXC_F_DMA_CTRL_TO_PER_POS)

#define MXC_V_DMA_CTRL_TO_PER_TO512                    ((uint32_t)0x7UL)

#define MXC_S_DMA_CTRL_TO_PER_TO512                    (MXC_V_DMA_CTRL_TO_PER_TO512 << MXC_F_DMA_CTRL_TO_PER_POS)

#define MXC_F_DMA_CTRL_TO_CLKDIV_POS                   14

#define MXC_F_DMA_CTRL_TO_CLKDIV                       ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_TO_CLKDIV_POS))

#define MXC_V_DMA_CTRL_TO_CLKDIV_DIS                   ((uint32_t)0x0UL)

#define MXC_S_DMA_CTRL_TO_CLKDIV_DIS                   (MXC_V_DMA_CTRL_TO_CLKDIV_DIS << MXC_F_DMA_CTRL_TO_CLKDIV_POS)

#define MXC_V_DMA_CTRL_TO_CLKDIV_DIV256                ((uint32_t)0x1UL)

#define MXC_S_DMA_CTRL_TO_CLKDIV_DIV256                (MXC_V_DMA_CTRL_TO_CLKDIV_DIV256 << MXC_F_DMA_CTRL_TO_CLKDIV_POS)

#define MXC_V_DMA_CTRL_TO_CLKDIV_DIV64K                ((uint32_t)0x2UL)

#define MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K                (MXC_V_DMA_CTRL_TO_CLKDIV_DIV64K << MXC_F_DMA_CTRL_TO_CLKDIV_POS)

#define MXC_V_DMA_CTRL_TO_CLKDIV_DIV16M                ((uint32_t)0x3UL)

#define MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M                (MXC_V_DMA_CTRL_TO_CLKDIV_DIV16M << MXC_F_DMA_CTRL_TO_CLKDIV_POS)

#define MXC_F_DMA_CTRL_SRCWD_POS                       16

#define MXC_F_DMA_CTRL_SRCWD                           ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_SRCWD_POS))

#define MXC_V_DMA_CTRL_SRCWD_BYTE                      ((uint32_t)0x0UL)

#define MXC_S_DMA_CTRL_SRCWD_BYTE                      (MXC_V_DMA_CTRL_SRCWD_BYTE << MXC_F_DMA_CTRL_SRCWD_POS)

#define MXC_V_DMA_CTRL_SRCWD_HALFWORD                  ((uint32_t)0x1UL)

#define MXC_S_DMA_CTRL_SRCWD_HALFWORD                  (MXC_V_DMA_CTRL_SRCWD_HALFWORD << MXC_F_DMA_CTRL_SRCWD_POS)

#define MXC_V_DMA_CTRL_SRCWD_WORD                      ((uint32_t)0x2UL)

#define MXC_S_DMA_CTRL_SRCWD_WORD                      (MXC_V_DMA_CTRL_SRCWD_WORD << MXC_F_DMA_CTRL_SRCWD_POS)

#define MXC_F_DMA_CTRL_SRCINC_POS                      18

#define MXC_F_DMA_CTRL_SRCINC                          ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_SRCINC_POS))

#define MXC_F_DMA_CTRL_DSTWD_POS                       20

#define MXC_F_DMA_CTRL_DSTWD                           ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_DSTWD_POS))

#define MXC_V_DMA_CTRL_DSTWD_BYTE                      ((uint32_t)0x0UL)

#define MXC_S_DMA_CTRL_DSTWD_BYTE                      (MXC_V_DMA_CTRL_DSTWD_BYTE << MXC_F_DMA_CTRL_DSTWD_POS)

#define MXC_V_DMA_CTRL_DSTWD_HALFWORD                  ((uint32_t)0x1UL)

#define MXC_S_DMA_CTRL_DSTWD_HALFWORD                  (MXC_V_DMA_CTRL_DSTWD_HALFWORD << MXC_F_DMA_CTRL_DSTWD_POS)

#define MXC_V_DMA_CTRL_DSTWD_WORD                      ((uint32_t)0x2UL)

#define MXC_S_DMA_CTRL_DSTWD_WORD                      (MXC_V_DMA_CTRL_DSTWD_WORD << MXC_F_DMA_CTRL_DSTWD_POS)

#define MXC_F_DMA_CTRL_DSTINC_POS                      22

#define MXC_F_DMA_CTRL_DSTINC                          ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_DSTINC_POS))

#define MXC_F_DMA_CTRL_BURST_SIZE_POS                  24

#define MXC_F_DMA_CTRL_BURST_SIZE                      ((uint32_t)(0x1FUL << MXC_F_DMA_CTRL_BURST_SIZE_POS))

#define MXC_F_DMA_CTRL_DIS_IE_POS                      30

#define MXC_F_DMA_CTRL_DIS_IE                          ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_DIS_IE_POS))

#define MXC_F_DMA_CTRL_CTZ_IE_POS                      31

#define MXC_F_DMA_CTRL_CTZ_IE                          ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_CTZ_IE_POS))

#define MXC_F_DMA_STATUS_STATUS_POS                    0

#define MXC_F_DMA_STATUS_STATUS                        ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_STATUS_POS))

#define MXC_F_DMA_STATUS_IPEND_POS                     1

#define MXC_F_DMA_STATUS_IPEND                         ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_IPEND_POS))

#define MXC_F_DMA_STATUS_CTZ_IF_POS                    2

#define MXC_F_DMA_STATUS_CTZ_IF                        ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_CTZ_IF_POS))

#define MXC_F_DMA_STATUS_RLD_IF_POS                    3

#define MXC_F_DMA_STATUS_RLD_IF                        ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_RLD_IF_POS))

#define MXC_F_DMA_STATUS_BUS_ERR_POS                   4

#define MXC_F_DMA_STATUS_BUS_ERR                       ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_BUS_ERR_POS))

#define MXC_F_DMA_STATUS_TO_IF_POS                     6

#define MXC_F_DMA_STATUS_TO_IF                         ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_TO_IF_POS))

#define MXC_F_DMA_SRC_ADDR_POS                         0

#define MXC_F_DMA_SRC_ADDR                             ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_ADDR_POS))

#define MXC_F_DMA_DST_ADDR_POS                         0

#define MXC_F_DMA_DST_ADDR                             ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_ADDR_POS))

#define MXC_F_DMA_CNT_CNT_POS                          0

#define MXC_F_DMA_CNT_CNT                              ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS))

#define MXC_F_DMA_SRCRLD_ADDR_POS                      0

#define MXC_F_DMA_SRCRLD_ADDR                          ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRCRLD_ADDR_POS))

#define MXC_F_DMA_DSTRLD_ADDR_POS                      0

#define MXC_F_DMA_DSTRLD_ADDR                          ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DSTRLD_ADDR_POS))

#define MXC_F_DMA_CNTRLD_CNT_POS                       0

#define MXC_F_DMA_CNTRLD_CNT                           ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNTRLD_CNT_POS))

#define MXC_F_DMA_CNTRLD_EN_POS                        31

#define MXC_F_DMA_CNTRLD_EN                            ((uint32_t)(0x1UL << MXC_F_DMA_CNTRLD_EN_POS))

#ifdef __cplusplus

}

#endif


#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_DMA_REGS_H_

mxc_dma_ch_regs_t::dst
__IO uint32_t dst
Definition: dma_regs.h:80

mxc_dma_ch_regs_t::src
__IO uint32_t src
Definition: dma_regs.h:79

mxc_dma_ch_regs_t::ctrl
__IO uint32_t ctrl
Definition: dma_regs.h:77

mxc_dma_ch_regs_t::cnt
__IO uint32_t cnt
Definition: dma_regs.h:81

mxc_dma_ch_regs_t::srcrld
__IO uint32_t srcrld
Definition: dma_regs.h:82

mxc_dma_ch_regs_t::cntrld
__IO uint32_t cntrld
Definition: dma_regs.h:84

mxc_dma_ch_regs_t::dstrld
__IO uint32_t dstrld
Definition: dma_regs.h:83

mxc_dma_ch_regs_t::status
__IO uint32_t status
Definition: dma_regs.h:78

mxc_dma_ch_regs_t
Definition: dma_regs.h:76