MAX32690 Peripheral Driver API
Peripheral Driver API for the MAX32690
max32690.h
1/******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_MAX32690_H_
22#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_MAX32690_H_
23
24#ifndef TARGET_NUM
25#define TARGET_NUM 32690
26#endif
27
28#define MXC_NUMCORES 1
29
30#include <stdint.h>
31
32#ifndef FALSE
33#define FALSE (0)
34#endif
35
36#ifndef TRUE
37#define TRUE (1)
38#endif
39
40/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
41#if defined(__GNUC__)
42#ifndef __weak
43#define __weak __attribute__((weak))
44#endif
45
46#elif defined(__CC_ARM)
47
48#define inline __inline
49#pragma anon_unions
50
51#endif
52
53typedef enum {
54#ifndef __riscv // not RISC-V
55 NonMaskableInt_IRQn = -14,
56 HardFault_IRQn = -13,
57 MemoryManagement_IRQn = -12,
58 BusFault_IRQn = -11,
59 UsageFault_IRQn = -10,
60 SVCall_IRQn = -5,
61 DebugMonitor_IRQn = -4,
62 PendSV_IRQn = -2,
63 SysTick_IRQn = -1,
64
65 /* Device-specific interrupt sources (external to ARM core) */
66 /* table entry number */
67 /* |||| */
68 /* |||| table offset address */
69 /* vvvv vvvvvv */
70
71 PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */
72 WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */
73 USB_IRQn, /* 0x12 0x0048 18: USB */
74 RTC_IRQn, /* 0x13 0x004C 19: RTC */
75 TRNG_IRQn, /* 0x14 0x0050 20: True Random Number Generator */
76 TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */
77 TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */
78 TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */
79 TMR3_IRQn, /* 0x18 0x0060 24: Timer 3 */
80 TMR4_IRQn, /* 0x19 0x0064 25: Timer 4 (LP) */
81 TMR5_IRQn, /* 0x1A 0x0068 26: Timer 5 (LP) */
82 RSV11_IRQn, /* 0x1B 0x006C 27: Reserved */
83 RSV12_IRQn, /* 0x1C 0x0070 28: Reserved */
84 I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */
85 UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */
86 UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */
87 SPI0_IRQn, /* 0x20 0x0080 32: SPI0 */
88 SPI1_IRQn, /* 0x21 0x0084 33: SPI1 */
89 SPI2_IRQn, /* 0x22 0x0088 34: SPI2 */
90 RSV19_IRQn, /* 0x23 0x008C 35: Reserved */
91 ADC_IRQn, /* 0x24 0x0090 36: ADC */
92 RSV21_IRQn, /* 0x25 0x0094 37: Reserved */
93 RSV22_IRQn, /* 0x26 0x0098 38: Reserved */
94 FLC0_IRQn, /* 0x27 0x009C 39: Flash Controller 0 */
95 GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */
96 GPIO1_IRQn, /* 0x29 0x00A4 41: GPIO1 */
97 GPIO2_IRQn, /* 0x2A 0x00A8 42: GPIO2 */
98 CRYPTO_IRQn, /* 0x2B 0x00AC 43: Crypto */
99 DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */
100 DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */
101 DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */
102 DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */
103 RSV32_IRQn, /* 0x30 0x00C0 48: Reserved */
104 RSV33_IRQn, /* 0x31 0x00C4 49: Reserved */
105 UART2_IRQn, /* 0x32 0x00C8 50: UART 2 */
106 RSV35_IRQn, /* 0x33 0x00CC 51: Reserved */
107 I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */
108 RSV37_IRQn, /* 0x35 0x00D4 53: Reserved */
109 SPIXC_IRQn, /* 0x36 0x00D8 54: SPI execute in place */
110 BTLE_TX_DONE_IRQn, /* 0x37 0x00DC 55: BTLE TX Done */
111 BTLE_RX_RCVD_IRQn, /* 0x38 0x00E0 56: BTLE RX Received */
112 BTLE_RX_ENG_DET_IRQn, /* 0x39 0x00E4 57: BTLE RX Energy Detected */
113 BTLE_SFD_DET_IRQn, /* 0x3A 0x00E8 58: BTLE SFD Detected */
114 BTLE_SFD_TO_IRQn, /* 0x3B 0x00EC 59: BTLE SFD Timeout*/
115 BTLE_GP_EVENT_IRQn, /* 0x3C 0x00F0 60: BTLE Timestamp*/
116 BTLE_CFO_IRQn, /* 0x3D 0x00F4 61: BTLE CFO Done */
117 BTLE_SIG_DET_IRQn, /* 0x3E 0x00F8 62: BTLE Signal Detected */
118 BTLE_AGC_EVENT_IRQn, /* 0x3F 0x00FC 63: BTLE AGC Event */
119 BTLE_RFFE_SPIM_IRQn, /* 0x40 0x0100 64: BTLE RFFE SPIM Done */
120 BTLE_TX_AES_IRQn, /* 0x41 0x0104 65: BTLE TX AES Done */
121 BTLE_RX_AES_IRQn, /* 0x42 0x0108 66: BTLE RX AES Done */
122 BTLE_INV_APB_ADDR_IRQn, /* 0x43 0x010C 67: BTLE Invalid APB Address*/
123 BTLE_IQ_DATA_VALID_IRQn, /* 0x44 0x0110 68: BTLE IQ Data Valid */
124 WUT0_IRQn, /* 0x45 0x0114 69: Wakeup Timer 0 */
125 GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIO and AIN Wakeup */
126 RSV55_IRQn, /* 0x47 0x011C 71: Reserved */
127 SPI3_IRQn, /* 0x48 0x0120 72: SPI3 */
128 WDT1_IRQn, /* 0x49 0x0124 73: LP Watchdog */
129 GPIO3_IRQn, /* 0x4A 0x0128 74: GPIO3 */
130 PT_IRQn, /* 0x4B 0x012C 75: Pulse Train */
131 RSV60_IRQn, /* 0x4C 0x0130 76: Reserved */
132 HPB_IRQn, /* 0x4D 0x0134 77: Hyperbus */
133 I2C2_IRQn, /* 0x4E 0x0138 78: I2C2 */
134 RISCV_IRQn, /* 0x4F 0x013C 79: RISC-V */
135 RSV64_IRQn, /* 0x50 0x0140 80: Reserved */
136 RSV65_IRQn, /* 0x51 0x0144 81: Reserved */
137 RSV66_IRQn, /* 0x52 0x0148 82: Reserved */
138 OWM_IRQn, /* 0x53 0x014C 83: One Wire Master */
139 DMA4_IRQn, /* 0x54 0x0150 84: DMA4 */
140 DMA5_IRQn, /* 0x55 0x0154 85: DMA5 */
141 DMA6_IRQn, /* 0x56 0x0158 86: DMA6 */
142 DMA7_IRQn, /* 0x57 0x015C 87: DMA7 */
143 DMA8_IRQn, /* 0x58 0x0160 88: DMA8 */
144 DMA9_IRQn, /* 0x59 0x0164 89: DMA9 */
145 DMA10_IRQn, /* 0x5A 0x0168 90: DMA10 */
146 DMA11_IRQn, /* 0x5B 0x016C 91: DMA11 */
147 DMA12_IRQn, /* 0x5C 0x0170 92: DMA12 */
148 DMA13_IRQn, /* 0x5D 0x0174 93: DMA13 */
149 DMA14_IRQn, /* 0x5E 0x0178 94: DMA14 */
150 DMA15_IRQn, /* 0x5F 0x017C 95: DMA15 */
151 USBDMA_IRQn, /* 0x60 0x0180 96: USB DMA */
152 RSV81_IRQn, /* 0x61 0x0184 97: Reserved */
153 ECC_IRQn, /* 0x62 0x0188 98: ECC */
154 RSV83_IRQn, /* 0x63 0x018C 99: Reserved */
155 RSV84_IRQn, /* 0x64 0x0190 100: Resevred */
156 SCA_IRQn, /* 0x65 0x0194 101: SCA Crypto Accelerator */
157 RSV86_IRQn, /* 0x66 0x0198 102: Reserved */
158 FLC1_IRQn, /* 0x67 0x019C 103: Flash Controller 1 */
159 UART3_IRQn, /* 0x68 0x01A0 104: UART 3 (LP) */
160 RSV89_IRQn, /* 0x69 0x01A4 105: Reserved */
161 RSV90_IRQn, /* 0x6A 0x01A8 106: Reserved */
162 RSV91_IRQn, /* 0x6B 0x01AC 107: Reserved */
163 RSV92_IRQn, /* 0x6C 0x01B0 108: Reserved */
164 RSV93_IRQn, /* 0x6D 0x01B4 109: Reserved */
165 RSV94_IRQn, /* 0x6E 0x01B8 110: Reserved */
166 RSV95_IRQn, /* 0x6F 0x01BC 111: Reserved */
167 RSV96_IRQn, /* 0x70 0x01C0 112: Reserved */
168 RSV97_IRQn, /* 0x71 0x01C4 113: Reserved */
169 RSV98_IRQn, /* 0x72 0x01C8 114: Reserved */
170 I2S_IRQn, /* 0x73 0x01CC 115: I2S */
171 RSV100_IRQn, /* 0x74 0x01D0 116: Reserved */
172 RSV101_IRQn, /* 0x75 0x01D4 117: Reserved */
173 RSV102_IRQn, /* 0x76 0x01D8 118: Reserved */
174 LPCMP_IRQn, /* 0x77 0x01Dc 119: LP Comparator */
175 RSV104_IRQn, /* 0x78 0x01E0 120: Reserved */
176 SPI4_IRQn, /* 0x79 0x01E4 121: SPI4 */
177 RSV106_IRQn, /* 0x7A 0x01E8 122: Reserved */
178 CAN0_IRQn, /* 0x7B 0x01EC 123: CAN0 */
179 CAN1_IRQn, /* 0x7C 0x01F0 124: CAN1 */
180 WUT1_IRQn, /* 0x7D 0x01F4 125: Wake up timer 1 */
181 RSV110_IRQn, /* 0x7E 0x01F8 126: Reserved */
182 RSV111_IRQn, /* 0x7F 0x01FC 127: Reserved */
183#else // __riscv
184 HardFault_IRQn = 3, /* 0x03,3 HardFault */
185 PF_IRQn = 4, /* 0x04,4 PFW | SYSFAULT | CM4 */
186 WDT0_IRQn, /* 0x05,5 Watchdog 0 */
187 GPIOWAKE_IRQn = 6, /* 0x06,6 GPIO Wakeup */
188 AINComp_IRQn = 6, /* 0x06,6 Analog In Comparator */
189 RTC_IRQn, /* 0x07,7 RTC */
190 TMR0_IRQn, /* 0x08,8 Timer 0 */
191 TMR1_IRQn, /* 0x09,9 Timer 1 */
192 TMR2_IRQn, /* 0x0A,10 Timer 2 */
193 TMR3_IRQn, /* 0x0B,11 Timer 3 */
194 TMR4_IRQn, /* 0x0C,12 Timer 4 (LP) */
195 TMR5_IRQn, /* 0x0D,13 Timer 5 (LP) */
196 I2C0_IRQn, /* 0x0E,14 I2C0 */
197 UART0_IRQn, /* 0x0F,15 UART 0 */
198 CM4_IRQn, /* 0x10,16 CM4 */
199 I2C1_IRQn, /* 0x11,17 I2C1 */
200 UART1_IRQn, /* 0x12,18 UART 1 */
201 UART2_IRQn, /* 0x13,19 UART 2 */
202 I2C2_IRQn, /* 0x14,20 I2C2 */
203 UART3_IRQn, /* 0x15,21 LPUART */
204 SPI0_IRQn, /* 0x16,22 SPI0 */
205 WUT0_IRQn, /* 0x17,23 WUT0 */
206 FLC1_IRQn, /* 0x18,24 Flash Controller 1 */
207 GPIO0_IRQn, /* 0x19,25 GPIO0 */
208 GPIO1_IRQn, /* 0x1A,26 GPIO1 */
209 GPIO3_IRQn, /* 0x1B,27 GPIO3 (LP) */
210 DMA0_IRQn, /* 0x1C,28 DMA0 */
211 DMA1_IRQn, /* 0x1D,29 DMA1 */
212 DMA2_IRQn, /* 0x1E,30 DMA2 */
213 DMA3_IRQn, /* 0x1F,31 DMA3 */
214 BTLE_TX_DONE_IRQn, /* 0x20,32 Reserved */
215 BTLE_RX_RCVD_IRQn, /* 0x21,33 Reserved */
216 BTLE_RX_ENG_DET_IRQn, /* 0x22,34 Reserved */
217 BTLE_SFD_DET_IRQn, /* 0x23,35 Reserved */
218 BTLE_SFD_TO_IRQn, /* 0x24,36 Reserved */
219 BTLE_GP_EVENT_IRQn, /* 0x25,37 Reserved */
220 BTLE_CFO_IRQn, /* 0x26,38 Reserved */
221 BTLE_SIG_DET_IRQn, /* 0x27,39 Reserved */
222 BTLE_AGC_EVENT_IRQn, /* 0x28,40 Reserved */
223 BTLE_RFFE_SPIM_IRQn, /* 0x29,41 Reserved */
224 BTLE_TX_AES_IRQn, /* 0x2A,42 Reserved */
225 BTLE_RX_AES_IRQn, /* 0x2B,43 Reserved */
226 BTLE_INV_APB_ADDR_IRQn, /* 0x2C,44 Reserved */
227 BTLE_IQ_DATA_VALID_IRQn, /* 0x2D,45 Reserved */
228 DMA4_15_IRQn, /* 0x2E,46 DMA4 - 15 */
229 TRNG_IRQn, /* 0x2F,47 True Random Number Generator */
230 WDT1_IRQn, /* 0x30,48 Watchdog 1 (LP) */
231 RSV49_IRQn, /* 0x31,49 Reserved */
232 RSV50_IRQn, /* 0x32,50 Reserved */
233 WUT1_IRQn, /* 0x33,51 WUT1 */
234 PT_IRQn, /* 0x34,52 Pulse train */
235 ADC_IRQn, /* 0x35,53 ADC */
236 OWM_IRQn, /* 0x36,54 One Wire Master */
237 I2S_IRQn, /* 0x37,55 I2S */
238 RSV56_IRQn, /* 0x38,56 Reserved */
239 RSV57_IRQn, /* 0x39,57 Reserved */
240 CAN0_IRQn, /* 0x3A,58 CAN0 */
241 RSV59_IRQn, /* 0x3B,59 Reserved */
242 GPIO2_IRQn, /* 0x3C,60 GPIO2 */
243 SPI1_IRQn, /* 0x3D,61 SPI1 */
244 SPI2_IRQn, /* 0x3E,62 SPI2 */
245 CAN1_IRQn, /* 0x3F,63 CAN1 */
246#endif // __riscv
247 MXC_IRQ_EXT_COUNT,
248} IRQn_Type;
249
250#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
251
252/* ================================================================================ */
253/* ================ Processor and Core Peripheral Section ================ */
254/* ================================================================================ */
255
256#ifndef __riscv
257/* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */
258#define __CM4_REV 0x0100
259#define __MPU_PRESENT 1
260#define __NVIC_PRIO_BITS 3
261#define __Vendor_SysTickConfig 0
262#define __FPU_PRESENT 1
264#include <core_cm4.h>
266#else // __riscv
267
268#include <core_rv32.h>
269
270#endif // __riscv
271
272#include "system_max32690.h"
274/* ================================================================================ */
275/* ================== Device Specific Memory Section ================== */
276/* ================================================================================ */
277
278#define MXC_ROM_MEM_BASE 0x00000000UL
279#define MXC_ROM_MEM_SIZE 0x00020000UL
280#define MXC_XIP_MEM_BASE 0x08000000UL
281#define MXC_XIP_MEM_SIZE 0x08000000UL
282#define MXC_FLASH0_MEM_BASE 0x10000000UL
283#define MXC_FLASH1_MEM_BASE 0x10300000UL
284#define MXC_FLASH_MEM_BASE MXC_FLASH0_MEM_BASE
285#define MXC_FLASH_PAGE_SIZE 0x00004000UL
286#define MXC_FLASH0_PAGE_SIZE 0x00004000UL
287#define MXC_FLASH1_PAGE_SIZE 0x00002000UL
288#define MXC_FLASH0_MEM_SIZE 0x00300000UL
289#define MXC_FLASH1_MEM_SIZE 0x00040000UL
290#define MXC_FLASH_MEM_SIZE (MXC_FLASH0_MEM_SIZE + MXC_FLASH1_MEM_SIZE)
291#define MXC_INFO0_MEM_BASE 0x10800000UL
292#define MXC_INFO1_MEM_BASE 0x10802000UL
293#define MXC_INFO_MEM_BASE MXC_INFO0_MEM_BASE
294#define MXC_INFO_MEM_SIZE 0x00002000UL
295#define MXC_INFO0_MEM_SIZE 0x00002000UL
296#define MXC_INFO1_MEM_SIZE 0x00002000UL
297#define MXC_SRAM_MEM_BASE 0x20000000UL
298#define MXC_SRAM_MEM_SIZE 0x00120000UL
299#define MXC_HPB_MEM_BASE 0x60000000UL
300#define MXC_HPB_MEM_SIZE 0x20000000UL
301#define MXC_XIP_DATA_MEM_BASE 0x80000000UL
302#define MXC_XIP_DATA_MEM_SIZE 0x20000000UL
303
304/* ================================================================================ */
305/* ================ Device Specific Peripheral Section ================ */
306/* ================================================================================ */
307
308/*
309 Base addresses and configuration settings for all MAX32690 peripheral modules.
310*/
311
312/******************************************************************************/
313/* Global control */
314#define MXC_BASE_GCR ((uint32_t)0x40000000UL)
315#define MXC_GCR ((mxc_gcr_regs_t *)MXC_BASE_GCR)
316
317/******************************************************************************/
318/* Non-battery backed SI Registers */
319#define MXC_BASE_SIR ((uint32_t)0x40000400UL)
320#define MXC_SIR ((mxc_sir_regs_t *)MXC_BASE_SIR)
321
322/******************************************************************************/
323/* Non-Battery Backed Function Control */
324#define MXC_BASE_FCR ((uint32_t)0x40000800UL)
325#define MXC_FCR ((mxc_fcr_regs_t *)MXC_BASE_FCR)
326
327/******************************************************************************/
328/* CTB */
329#define MXC_BASE_CTB ((uint32_t)0x40001000UL)
330#define MXC_CTB ((mxc_ctb_regs_t *)MXC_BASE_CTB)
331
332/******************************************************************************/
333/* Windowed Watchdog Timer */
334#define MXC_CFG_WDT_INSTANCES (2)
335
336#define MXC_BASE_WDT0 ((uint32_t)0x40003000UL)
337#define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
338#define MXC_WDT MXC_WDT0
339#define MXC_BASE_WDT1 ((uint32_t)0x40080800UL)
340#define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1)
341
342#define MXC_WDT_GET_IDX(p) ((p) == MXC_WDT0 ? 0 : (p) == MXC_WDT1 ? 1 : -1)
343
344/******************************************************************************/
345/* AES Keys */
346#define MXC_BASE_AESKEYS ((uint32_t)0x40005000UL)
347#define MXC_AESKEYS ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS)
348
349// DEPRECATED(1-10-2023): Scheduled for removal.
350#define MXC_BASE_AESKEY MXC_BASE_AESKEYS
351#define MXC_AESKEY ((mxc_aes_key_regs_t *)MXC_BASE_AESKEY)
352
353/******************************************************************************/
354/* Trim System Initalization Register */
355#define MXC_BASE_TRIMSIR ((uint32_t)0x40005400UL)
356#define MXC_TRIMSIR ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR)
357
358/******************************************************************************/
359/* GCFR */
360#define MXC_BASE_GCFR ((uint32_t)0x40005800UL)
361#define MXC_GCFR ((mxc_gcfr_regs_t *)MXC_BASE_GCFR)
362
363/******************************************************************************/
364/* Real Time Clock */
365#define MXC_BASE_RTC ((uint32_t)0x40006000UL)
366#define MXC_RTC ((mxc_rtc_regs_t *)MXC_BASE_RTC)
367
368/******************************************************************************/
369/* Wake-Up Timer (WUT) */
370#define MXC_CFG_WUT_INSTANCES (2)
371
372#define MXC_BASE_WUT0 ((uint32_t)0x40006400UL)
373#define MXC_WUT0 ((mxc_wut_regs_t *)MXC_BASE_WUT0)
374#define MXC_WUT MXC_WUT0
375#define MXC_BASE_WUT1 ((uint32_t)0x40006600UL)
376#define MXC_WUT1 ((mxc_wut_regs_t *)MXC_BASE_WUT1)
377
378/******************************************************************************/
379/* Power Sequencer */
380#define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL)
381#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
382
383/******************************************************************************/
384/* Misc Control */
385#define MXC_BASE_MCR ((uint32_t)0x40006C00UL)
386#define MXC_MCR ((mxc_mcr_regs_t *)MXC_BASE_MCR)
387
388/******************************************************************************/
389/* GPIO */
390#define MXC_CFG_GPIO_INSTANCES (5)
391#define MXC_CFG_GPIO_PINS_PORT (32)
392
393#define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL)
394#define MXC_GPIO0 ((mxc_gpio_regs_t *)MXC_BASE_GPIO0)
395#define MXC_BASE_GPIO1 ((uint32_t)0x40009000UL)
396#define MXC_GPIO1 ((mxc_gpio_regs_t *)MXC_BASE_GPIO1)
397#define MXC_BASE_GPIO2 ((uint32_t)0x4000A000UL)
398#define MXC_GPIO2 ((mxc_gpio_regs_t *)MXC_BASE_GPIO2)
399#define MXC_BASE_GPIO3 ((uint32_t)0x40080400UL)
400#define MXC_GPIO3 ((mxc_gpio_regs_t *)MXC_BASE_GPIO3)
401//GPIO4 dummy address it does not live here and will be handled in code different than other gpios but this allow our macros to work.
402#define MXC_BASE_GPIO4 ((uint32_t)0x4000C000UL)
403#define MXC_GPIO4 ((mxc_gpio_regs_t *)MXC_BASE_GPIO4)
404
405#define MXC_GPIO_GET_IDX(p) \
406 ((p) == MXC_GPIO0 ? 0 : \
407 (p) == MXC_GPIO1 ? 1 : \
408 (p) == MXC_GPIO2 ? 2 : \
409 (p) == MXC_GPIO3 ? 3 : \
410 (p) == MXC_GPIO4 ? 4 : \
411 -1)
412
413#define MXC_GPIO_GET_GPIO(i) \
414 ((i) == 0 ? MXC_GPIO0 : \
415 (i) == 1 ? MXC_GPIO1 : \
416 (i) == 2 ? MXC_GPIO2 : \
417 (i) == 3 ? MXC_GPIO3 : \
418 (i) == 4 ? MXC_GPIO4 : \
419 0)
420
421#define MXC_GPIO_GET_IRQ(i) \
422 ((i) == 0 ? GPIO0_IRQn : \
423 (i) == 1 ? GPIO1_IRQn : \
424 (i) == 2 ? GPIO2_IRQn : \
425 (i) == 3 ? GPIO3_IRQn : \
426 (i) == 4 ? GPIOWAKE_IRQn : \
427 0)
428
429/******************************************************************************/
430/* Timer */
431#define SEC(s) (((uint32_t)s) * 1000000UL)
432#define MSEC(ms) (ms * 1000UL)
433#define USEC(us) (us)
434
435#define MXC_CFG_TMR_INSTANCES (6)
436
437#define MXC_BASE_TMR0 ((uint32_t)0x40010000UL)
438#define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0)
439#define MXC_BASE_TMR1 ((uint32_t)0x40011000UL)
440#define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1)
441#define MXC_BASE_TMR2 ((uint32_t)0x40012000UL)
442#define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2)
443#define MXC_BASE_TMR3 ((uint32_t)0x40013000UL)
444#define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3)
445#define MXC_BASE_TMR4 ((uint32_t)0x40080C00UL)
446#define MXC_TMR4 ((mxc_tmr_regs_t *)MXC_BASE_TMR4)
447#define MXC_BASE_TMR5 ((uint32_t)0x40081000UL)
448#define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5)
449
450#define MXC_TMR_GET_IRQ(i) \
451 (IRQn_Type)((i) == 0 ? TMR0_IRQn : \
452 (i) == 1 ? TMR1_IRQn : \
453 (i) == 2 ? TMR2_IRQn : \
454 (i) == 3 ? TMR3_IRQn : \
455 (i) == 4 ? TMR4_IRQn : \
456 (i) == 5 ? TMR5_IRQn : \
457 0)
458
459#define MXC_TMR_GET_BASE(i) \
460 ((i) == 0 ? MXC_BASE_TMR0 : \
461 (i) == 1 ? MXC_BASE_TMR1 : \
462 (i) == 2 ? MXC_BASE_TMR2 : \
463 (i) == 3 ? MXC_BASE_TMR3 : \
464 (i) == 4 ? MXC_BASE_TMR4 : \
465 (i) == 5 ? MXC_BASE_TMR5 : \
466 0)
467
468#define MXC_TMR_GET_TMR(i) \
469 ((i) == 0 ? MXC_TMR0 : \
470 (i) == 1 ? MXC_TMR1 : \
471 (i) == 2 ? MXC_TMR2 : \
472 (i) == 3 ? MXC_TMR3 : \
473 (i) == 4 ? MXC_TMR4 : \
474 (i) == 5 ? MXC_TMR5 : \
475 0)
476
477#define MXC_TMR_GET_IDX(p) \
478 ((p) == MXC_TMR0 ? 0 : \
479 (p) == MXC_TMR1 ? 1 : \
480 (p) == MXC_TMR2 ? 2 : \
481 (p) == MXC_TMR3 ? 3 : \
482 (p) == MXC_TMR4 ? 4 : \
483 (p) == MXC_TMR5 ? 5 : \
484 -1)
485
486/******************************************************************************/
487/* I2C */
488#define MXC_I2C_INSTANCES (3)
489
490#define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL)
491#define MXC_I2C0 ((mxc_i2c_regs_t *)MXC_BASE_I2C0)
492#define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL)
493#define MXC_I2C1 ((mxc_i2c_regs_t *)MXC_BASE_I2C1)
494#define MXC_BASE_I2C2 ((uint32_t)0x4001F000UL)
495#define MXC_I2C2 ((mxc_i2c_regs_t *)MXC_BASE_I2C2)
496
497#define MXC_I2C_GET_IRQ(i) \
498 (IRQn_Type)((i) == 0 ? I2C0_IRQn : (i) == 1 ? I2C1_IRQn : (i) == 2 ? I2C2_IRQn : 0)
499
500#define MXC_I2C_GET_BASE(i) \
501 ((i) == 0 ? MXC_BASE_I2C0 : (i) == 1 ? MXC_BASE_I2C1 : (i) == 2 ? MXC_BASE_I2C2 : 0)
502
503#define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : (i) == 1 ? MXC_I2C1 : (i) == 2 ? MXC_I2C2 : 0)
504
505#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : (p) == MXC_I2C1 ? 1 : (p) == MXC_I2C2 ? 2 : -1)
506
507#define MXC_I2C_FIFO_DEPTH (8)
508
509/* ************************************************************************** */
510/* SPI Execute in Place Master */
511#define MXC_BASE_SPIXFM ((uint32_t)0x40026000UL)
512#define MXC_SPIXFM ((mxc_spixfm_regs_t *)MXC_BASE_SPIXFM)
513
514/* ************************************************************************** */
515/* SPI Execute in Place Master Controller */
516#define MXC_CFG_SPIXFC_FIFO_DEPTH (16)
517
518#define MXC_BASE_SPIXFC ((uint32_t)0x40027000UL)
519#define MXC_SPIXFC ((mxc_spixfc_regs_t *)MXC_BASE_SPIXFC)
520#define MXC_BASE_SPIXFC_FIFO ((uint32_t)0x400BC000UL)
521#define MXC_SPIXFC_FIFO ((mxc_spixfc_fifo_regs_t *)MXC_BASE_SPIXFC_FIFO)
522
523/******************************************************************************/
524/* DMA */
525#define MXC_DMA_CHANNELS (16)
526#define MXC_DMA_INSTANCES (1)
527
528#define MXC_BASE_DMA ((uint32_t)0x40028000UL)
529#define MXC_DMA ((mxc_dma_regs_t *)MXC_BASE_DMA)
530
531#define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA ? 0 : -1)
532
533#define MXC_DMA_CH_GET_IRQ(i) \
534 ((IRQn_Type)(((i) == 0) ? DMA0_IRQn : \
535 ((i) == 1) ? DMA1_IRQn : \
536 ((i) == 2) ? DMA2_IRQn : \
537 ((i) == 3) ? DMA3_IRQn : \
538 ((i) == 4) ? DMA4_IRQn : \
539 ((i) == 5) ? DMA5_IRQn : \
540 ((i) == 6) ? DMA6_IRQn : \
541 ((i) == 7) ? DMA7_IRQn : \
542 ((i) == 8) ? DMA8_IRQn : \
543 ((i) == 9) ? DMA9_IRQn : \
544 ((i) == 10) ? DMA10_IRQn : \
545 ((i) == 11) ? DMA11_IRQn : \
546 ((i) == 12) ? DMA12_IRQn : \
547 ((i) == 13) ? DMA13_IRQn : \
548 ((i) == 14) ? DMA14_IRQn : \
549 ((i) == 15) ? DMA15_IRQn : \
550 0))
551
552/******************************************************************************/
553/* FLC */
554#define MXC_FLC_INSTANCES (2)
555
556#define MXC_BASE_FLC0 ((uint32_t)0x40029000UL)
557#define MXC_FLC0 ((mxc_flc_regs_t *)MXC_BASE_FLC0)
558#define MXC_FLC MXC_FLC0
559#define MXC_BASE_FLC1 ((uint32_t)0x40029400UL)
560#define MXC_FLC1 ((mxc_flc_regs_t *)MXC_BASE_FLC1)
561
562#define MXC_FLC_GET_IRQ(i) (IRQn_Type)((i) == 0 ? FLC0_IRQn : (i) == 1 ? FLC1_IRQn : 0)
563
564#define MXC_FLC_GET_BASE(i) ((i) == 0 ? MXC_BASE_FLC0 : (i) == 1 ? MXC_BASE_FLC1 : 0)
565
566#define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC0 : (i) == 1 ? MXC_FLC1 : 0)
567
568#define MXC_FLC_GET_IDX(p) ((p) == MXC_FLC0 ? 0 : (p) == MXC_FLC1 ? 1 : -1)
569
570/******************************************************************************/
571/* Internal Cache Controller */
572#define MXC_ICC_INSTANCES (2)
573
574#define MXC_BASE_ICC0 ((uint32_t)0x4002A000UL)
575#define MXC_ICC0 ((mxc_icc_regs_t *)MXC_BASE_ICC0)
576
577#define MXC_BASE_ICC1 ((uint32_t)0x4002A800UL)
578#define MXC_ICC1 ((mxc_icc_regs_t *)MXC_BASE_ICC1)
579
580#define MXC_ICC MXC_ICC0
581// ICC1 is the RISC-V cache
582
583/******************************************************************************/
584/* Internal Cache XIP Controller */
585#define MXC_BASE_SFCC ((uint32_t)0x4002F000UL)
586#define MXC_SFCC ((mxc_icc_regs_t *)MXC_BASE_SFCC)
587
588/******************************************************************************/
589/* External Memory Cache Controller */
590#define MXC_BASE_EMCC ((uint32_t)0x40033000UL)
591#define MXC_EMCC ((mxc_emcc_regs_t *)MXC_BASE_EMCC)
592
593/******************************************************************************/
594/* ADC */
595#define MXC_BASE_ADC ((uint32_t)0x40034000UL)
596#define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC)
597#define MXC_ADC_MAX_CLOCK 8000000 // Maximum ADC clock in Hz
598
599/******************************************************************************/
600/* HyperBus */
601#define MXC_BASE_HPB ((uint32_t)0x40039000UL)
602#define MXC_HPB ((mxc_hpb_regs_t *)MXC_BASE_HPB)
603
604/* ************************************************************************** */
605/* SPI Execute in Place Data Master Controller */
606#define MXC_BASE_SPIXR ((uint32_t)0x4003A000UL)
607#define MXC_SPIXR ((mxc_spixr_regs_t *)MXC_BASE_SPIXR)
608
609/*******************************************************************************/
610/* Pulse Train Generation */
611#define MXC_CFG_PT_INSTANCES (16)
612
613#define MXC_BASE_PTG ((uint32_t)0x4003C000UL)
614#define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG)
615#define MXC_BASE_PT0 ((uint32_t)0x4003C020UL)
616#define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0)
617#define MXC_BASE_PT1 ((uint32_t)0x4003C040UL)
618#define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1)
619#define MXC_BASE_PT2 ((uint32_t)0x4003C060UL)
620#define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2)
621#define MXC_BASE_PT3 ((uint32_t)0x4003C080UL)
622#define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3)
623#define MXC_BASE_PT4 ((uint32_t)0x4003C0A0UL)
624#define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4)
625#define MXC_BASE_PT5 ((uint32_t)0x4003C0C0UL)
626#define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5)
627#define MXC_BASE_PT6 ((uint32_t)0x4003C0E0UL)
628#define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6)
629#define MXC_BASE_PT7 ((uint32_t)0x4003C100UL)
630#define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7)
631#define MXC_BASE_PT8 ((uint32_t)0x4003C120UL)
632#define MXC_PT8 ((mxc_pt_regs_t *)MXC_BASE_PT8)
633#define MXC_BASE_PT9 ((uint32_t)0x4003C140UL)
634#define MXC_PT9 ((mxc_pt_regs_t *)MXC_BASE_PT9)
635#define MXC_BASE_PT10 ((uint32_t)0x4003C160UL)
636#define MXC_PT10 ((mxc_pt_regs_t *)MXC_BASE_PT10)
637#define MXC_BASE_PT11 ((uint32_t)0x4003C180UL)
638#define MXC_PT11 ((mxc_pt_regs_t *)MXC_BASE_PT11)
639#define MXC_BASE_PT12 ((uint32_t)0x4003C1A0UL)
640#define MXC_PT12 ((mxc_pt_regs_t *)MXC_BASE_PT12)
641#define MXC_BASE_PT13 ((uint32_t)0x4003C1C0UL)
642#define MXC_PT13 ((mxc_pt_regs_t *)MXC_BASE_PT13)
643#define MXC_BASE_PT14 ((uint32_t)0x4003C1E0UL)
644#define MXC_PT14 ((mxc_pt_regs_t *)MXC_BASE_PT14)
645#define MXC_BASE_PT15 ((uint32_t)0x4003C200UL)
646#define MXC_PT15 ((mxc_pt_regs_t *)MXC_BASE_PT15)
647
648#define MXC_PT_GET_BASE(i) \
649 ((i) == 0 ? MXC_BASE_PT0 : \
650 (i) == 1 ? MXC_BASE_PT1 : \
651 (i) == 2 ? MXC_BASE_PT2 : \
652 (i) == 3 ? MXC_BASE_PT3 : \
653 (i) == 4 ? MXC_BASE_PT4 : \
654 (i) == 5 ? MXC_BASE_PT5 : \
655 (i) == 6 ? MXC_BASE_PT6 : \
656 (i) == 7 ? MXC_BASE_PT7 : \
657 (i) == 8 ? MXC_BASE_PT8 : \
658 (i) == 9 ? MXC_BASE_PT9 : \
659 (i) == 10 ? MXC_BASE_PT10 : \
660 (i) == 11 ? MXC_BASE_PT11 : \
661 (i) == 12 ? MXC_BASE_PT12 : \
662 (i) == 13 ? MXC_BASE_PT13 : \
663 (i) == 14 ? MXC_BASE_PT14 : \
664 (i) == 15 ? MXC_BASE_PT15 : \
665 0)
666
667#define MXC_PT_GET_PT(i) \
668 ((i) == 0 ? MXC_PT0 : \
669 (i) == 1 ? MXC_PT1 : \
670 (i) == 2 ? MXC_PT2 : \
671 (i) == 3 ? MXC_PT3 : \
672 (i) == 4 ? MXC_PT4 : \
673 (i) == 5 ? MXC_PT5 : \
674 (i) == 6 ? MXC_PT6 : \
675 (i) == 7 ? MXC_PT7 : \
676 (i) == 8 ? MXC_PT8 : \
677 (i) == 9 ? MXC_PT9 : \
678 (i) == 10 ? MXC_PT10 : \
679 (i) == 11 ? MXC_PT11 : \
680 (i) == 12 ? MXC_PT12 : \
681 (i) == 13 ? MXC_PT13 : \
682 (i) == 14 ? MXC_PT14 : \
683 (i) == 15 ? MXC_PT15 : \
684 0)
685
686#define MXC_PT_GET_IDX(p) \
687 ((p) == MXC_PT0 ? 0 : \
688 (p) == MXC_PT1 ? 1 : \
689 (p) == MXC_PT2 ? 2 : \
690 (p) == MXC_PT3 ? 3 : \
691 (p) == MXC_PT4 ? 4 : \
692 (p) == MXC_PT5 ? 5 : \
693 (p) == MXC_PT6 ? 6 : \
694 (p) == MXC_PT7 ? 7 : \
695 (p) == MXC_PT8 ? 8 : \
696 (p) == MXC_PT9 ? 9 : \
697 (p) == MXC_PT10 ? 10 : \
698 (p) == MXC_PT11 ? 11 : \
699 (p) == MXC_PT12 ? 12 : \
700 (p) == MXC_PT13 ? 13 : \
701 (p) == MXC_PT14 ? 14 : \
702 (p) == MXC_PT15 ? 15 : \
703 -1)
704
705/******************************************************************************/
706/* One Wire Master */
707#define MXC_BASE_OWM ((uint32_t)0x4003D000UL)
708#define MXC_OWM ((mxc_owm_regs_t *)MXC_BASE_OWM)
709
710/******************************************************************************/
711/* Semaphore */
712#define MXC_CFG_SEMA_INSTANCES (8)
713
714#define MXC_BASE_SEMA ((uint32_t)0x4003E000UL)
715#define MXC_SEMA ((mxc_sema_regs_t *)MXC_BASE_SEMA)
716
717/******************************************************************************/
718/* UART / Serial Port Interface */
719#define MXC_UART_INSTANCES (4)
720#define MXC_UART_FIFO_DEPTH (8)
721
722#define MXC_BASE_UART0 ((uint32_t)0x40042000UL)
723#define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0)
724#define MXC_BASE_UART1 ((uint32_t)0x40043000UL)
725#define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1)
726#define MXC_BASE_UART2 ((uint32_t)0x40044000UL)
727#define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2)
728#define MXC_BASE_UART3 ((uint32_t)0x40081400UL)
729#define MXC_UART3 ((mxc_uart_regs_t *)MXC_BASE_UART3)
730
731#define MXC_UART_GET_IRQ(i) \
732 (IRQn_Type)((i) == 0 ? UART0_IRQn : \
733 (IRQn_Type)(i) == 1 ? UART1_IRQn : \
734 (IRQn_Type)(i) == 2 ? UART2_IRQn : \
735 (IRQn_Type)(i) == 3 ? UART3_IRQn : \
736 0)
737
738#define MXC_UART_GET_BASE(i) \
739 ((i) == 0 ? MXC_BASE_UART0 : \
740 (i) == 1 ? MXC_BASE_UART1 : \
741 (i) == 2 ? MXC_BASE_UART2 : \
742 (i) == 3 ? MXC_BASE_UART3 : \
743 0)
744
745#define MXC_UART_GET_UART(i) \
746 ((i) == 0 ? MXC_UART0 : (i) == 1 ? MXC_UART1 : (i) == 2 ? MXC_UART2 : (i) == 3 ? MXC_UART3 : 0)
747
748#define MXC_UART_GET_IDX(p) \
749 ((p) == MXC_UART0 ? 0 : (p) == MXC_UART1 ? 1 : (p) == MXC_UART2 ? 2 : (p) == MXC_UART3 ? 3 : -1)
750
751/******************************************************************************/
752/* SPI */
753#ifndef __riscv
754#define MXC_SPI_INSTANCES (5)
755#else
756#define MXC_SPI_INSTANCES (3)
757#endif // __riscv
758#define MXC_SPI_SS_INSTANCES (4)
759#define MXC_SPI_FIFO_DEPTH (32)
760
761#define MXC_BASE_SPI0 ((uint32_t)0x40046000UL)
762#define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0)
763#define MXC_BASE_SPI1 ((uint32_t)0x40047000UL)
764#define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1)
765#define MXC_BASE_SPI2 ((uint32_t)0x40048000UL)
766#define MXC_SPI2 ((mxc_spi_regs_t *)MXC_BASE_SPI2)
767
768#ifndef __riscv
769#define MXC_BASE_SPI3 ((uint32_t)0x400BE000UL)
770#define MXC_SPI3 ((mxc_spi_regs_t *)MXC_BASE_SPI3)
771#define MXC_BASE_SPI4 ((uint32_t)0x400BE400UL)
772#define MXC_SPI4 ((mxc_spi_regs_t *)MXC_BASE_SPI4)
773
774#define MXC_SPI_GET_IDX(p) \
775 ((p) == MXC_SPI0 ? 0 : \
776 (p) == MXC_SPI1 ? 1 : \
777 (p) == MXC_SPI2 ? 2 : \
778 (p) == MXC_SPI3 ? 3 : \
779 (p) == MXC_SPI4 ? 4 : \
780 -1)
781
782#define MXC_SPI_GET_BASE(i) \
783 ((i) == 0 ? MXC_BASE_SPI0 : \
784 (i) == 1 ? MXC_BASE_SPI1 : \
785 (i) == 2 ? MXC_BASE_SPI2 : \
786 (i) == 3 ? MXC_BASE_SPI3 : \
787 (i) == 4 ? MXC_BASE_SPI4 : \
788 0)
789
790#define MXC_SPI_GET_SPI(i) \
791 ((i) == 0 ? MXC_SPI0 : \
792 (i) == 1 ? MXC_SPI1 : \
793 (i) == 2 ? MXC_SPI2 : \
794 (i) == 3 ? MXC_SPI3 : \
795 (i) == 4 ? MXC_SPI4 : \
796 0)
797
798#define MXC_SPI_GET_IRQ(i) \
799 (IRQn_Type)((i) == 0 ? SPI0_IRQn : \
800 (i) == 1 ? SPI1_IRQn : \
801 (i) == 2 ? SPI2_IRQn : \
802 (i) == 3 ? SPI3_IRQn : \
803 (i) == 4 ? SPI4_IRQn : \
804 0)
805#else // __riscv
806
807#define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : (p) == MXC_SPI1 ? 1 : (p) == MXC_SPI2 ? 2 : -1)
808
809#define MXC_SPI_GET_BASE(i) \
810 ((i) == 0 ? MXC_BASE_SPI0 : (i) == 1 ? MXC_BASE_SPI1 : (i) == 2 ? MXC_BASE_SPI2 : 0)
811
812#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 \
813 (i) == 1 ? MXC_SPI1 \
814 (i) == 2 ? MXC_SPI2 : 0)
815
816#define MXC_SPI_GET_IRQ(i) \
817 (IRQn_Type)((i) == 0 ? SPI0_IRQn : (i) == 1 ? SPI1_IRQn : (i) == 2 ? SPI2_IRQn : 0)
818
819#endif // __riscv
820
821/******************************************************************************/
822/* TRNG */
823#define MXC_BASE_TRNG ((uint32_t)0x4004D000UL)
824#define MXC_TRNG ((mxc_trng_regs_t *)MXC_BASE_TRNG)
825
826/******************************************************************************/
827/* I2S */
828#define MXC_BASE_I2S ((uint32_t)0x40060000UL)
829#define MXC_I2S ((mxc_i2s_regs_t *)MXC_BASE_I2S)
830
831/******************************************************************************/
832/* USB */
833#define MXC_BASE_USBHS ((uint32_t)0x400B1000UL)
834#define MXC_USBHS ((mxc_usbhs_regs_t *)MXC_BASE_USBHS)
835#define MXC_USBHS_NUM_EP 12 /* HW must have at least EP 0 CONTROL + 11 IN/OUT */
836#define MXC_USBHS_NUM_DMA 8 /* HW must have at least this many DMA channels */
837#define MXC_USBHS_MAX_PACKET 512
838
840typedef enum {
841 MXC_USB_CLOCK_SYS_DIV_10 = 0,
842 MXC_USB_CLOCK_EXTCLK = 1,
843 MXC_USB_CLOCK_ERFO = 2
844} _mxc_usb_clock_t;
845
852#define mxc_usb_clock_t _mxc_usb_clock_t
853
854/******************************************************************************/
855/* Low Power General control */
856#define MXC_BASE_LPGCR ((uint32_t)0x40080000UL)
857#define MXC_LPGCR ((mxc_lpgcr_regs_t *)MXC_BASE_LPGCR)
858
859/******************************************************************************/
860/* Low-Power Comparator */
861#define MXC_BASE_LPCMP ((uint32_t)0x40088000UL)
862#define MXC_LPCMP ((mxc_lpcmp_regs_t *)MXC_BASE_LPCMP)
863
864/******************************************************************************/
865/* CAN */
866#define MXC_CAN_INSTANCES (2)
867
868#define MXC_BASE_CAN0 ((uint32_t)0x40064000UL)
869#define MXC_CAN0 ((mxc_can_regs_t *)MXC_BASE_CAN0)
870#define MXC_BASE_CAN1 ((uint32_t)0x40065000UL)
871#define MXC_CAN1 ((mxc_can_regs_t *)MXC_BASE_CAN1)
872
873#define MXC_CAN_GET_IDX(p) ((p) == MXC_CAN0 ? 0 : (p) == MXC_CAN1 ? 1 : -1)
874
875#define MXC_CAN_GET_BASE(i) ((i) == 0 ? MXC_BASE_CAN0 : (i) == 1 ? MXC_BASE_CAN1 : 0)
876
877#define MXC_CAN_GET_CAN(i) ((i) == 0 ? MXC_CAN0 : (i) == 1 ? MXC_CAN1 : 0)
878
879#define MXC_CAN_GET_IRQ(i) (IRQn_Type)((i) == 0 ? CAN0_IRQn : (i) == 1 ? CAN1_IRQn : 0)
880
881/******************************************************************************/
882/* Bit Shifting */
883
884#define MXC_F_BIT_0 (1 << 0)
885#define MXC_F_BIT_1 (1 << 1)
886#define MXC_F_BIT_2 (1 << 2)
887#define MXC_F_BIT_3 (1 << 3)
888#define MXC_F_BIT_4 (1 << 4)
889#define MXC_F_BIT_5 (1 << 5)
890#define MXC_F_BIT_6 (1 << 6)
891#define MXC_F_BIT_7 (1 << 7)
892#define MXC_F_BIT_8 (1 << 8)
893#define MXC_F_BIT_9 (1 << 9)
894#define MXC_F_BIT_10 (1 << 10)
895#define MXC_F_BIT_11 (1 << 11)
896#define MXC_F_BIT_12 (1 << 12)
897#define MXC_F_BIT_13 (1 << 13)
898#define MXC_F_BIT_14 (1 << 14)
899#define MXC_F_BIT_15 (1 << 15)
900#define MXC_F_BIT_16 (1 << 16)
901#define MXC_F_BIT_17 (1 << 17)
902#define MXC_F_BIT_18 (1 << 18)
903#define MXC_F_BIT_19 (1 << 19)
904#define MXC_F_BIT_20 (1 << 20)
905#define MXC_F_BIT_21 (1 << 21)
906#define MXC_F_BIT_22 (1 << 22)
907#define MXC_F_BIT_23 (1 << 23)
908#define MXC_F_BIT_24 (1 << 24)
909#define MXC_F_BIT_25 (1 << 25)
910#define MXC_F_BIT_26 (1 << 26)
911#define MXC_F_BIT_27 (1 << 27)
912#define MXC_F_BIT_28 (1 << 28)
913#define MXC_F_BIT_29 (1 << 29)
914#define MXC_F_BIT_30 (1 << 30)
915#define MXC_F_BIT_31 (1 << 31)
916
917/******************************************************************************/
918/* Bit Banding */
919
920#define BITBAND(reg, bit) \
921 ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg)&0x0fffffff) << 5) + \
922 ((bit) << 2))
923
924#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
925#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
926#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
927
928#define MXC_SETFIELD(reg, mask, setting) (reg = ((reg) & ~(mask)) | ((setting) & (mask)))
929
930/******************************************************************************/
931/* SCB CPACR */
932
933/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
934#define SCB_CPACR_CP10_Pos 20
935#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos)
936#define SCB_CPACR_CP11_Pos 22
937#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos)
939#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_MAX32690_H_