pwrseq_regs.h

Go to the documentation of this file.

 
/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_PWRSEQ_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_PWRSEQ_REGS_H_
 
/* **** Includes **** */
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined (__ICCARM__)
  #pragma system_include
#endif
 
#if defined (__CC_ARM)
  #pragma anon_unions
#endif
/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif
#ifndef __R
#define __R  volatile const
#endif
 
/* **** Definitions **** */
 
typedef struct {
    __IO uint32_t lpcn;                 
    __IO uint32_t lpwkst0;              
    __IO uint32_t lpwken0;              
    __IO uint32_t lpwkst1;              
    __IO uint32_t lpwken1;              
    __IO uint32_t lpwkst2;              
    __IO uint32_t lpwken2;              
    __IO uint32_t lpwkst3;              
    __IO uint32_t lpwken3;              
    __IO uint32_t lpwkst4;              
    __IO uint32_t lpwken4;              
    __R  uint32_t rsv_0x2c;
    __IO uint32_t lppwst;               
    __IO uint32_t lppwen;               
    __R  uint32_t rsv_0x38_0x47[4];
    __IO uint32_t gp0;                  
    __IO uint32_t gp1;                  
} mxc_pwrseq_regs_t;
 
/* Register offsets for module PWRSEQ */
#define MXC_R_PWRSEQ_LPCN                  ((uint32_t)0x00000000UL) 
#define MXC_R_PWRSEQ_LPWKST0               ((uint32_t)0x00000004UL) 
#define MXC_R_PWRSEQ_LPWKEN0               ((uint32_t)0x00000008UL) 
#define MXC_R_PWRSEQ_LPWKST1               ((uint32_t)0x0000000CUL) 
#define MXC_R_PWRSEQ_LPWKEN1               ((uint32_t)0x00000010UL) 
#define MXC_R_PWRSEQ_LPWKST2               ((uint32_t)0x00000014UL) 
#define MXC_R_PWRSEQ_LPWKEN2               ((uint32_t)0x00000018UL) 
#define MXC_R_PWRSEQ_LPWKST3               ((uint32_t)0x0000001CUL) 
#define MXC_R_PWRSEQ_LPWKEN3               ((uint32_t)0x00000020UL) 
#define MXC_R_PWRSEQ_LPWKST4               ((uint32_t)0x00000024UL) 
#define MXC_R_PWRSEQ_LPWKEN4               ((uint32_t)0x00000028UL) 
#define MXC_R_PWRSEQ_LPPWST                ((uint32_t)0x00000030UL) 
#define MXC_R_PWRSEQ_LPPWEN                ((uint32_t)0x00000034UL) 
#define MXC_R_PWRSEQ_GP0                   ((uint32_t)0x00000048UL) 
#define MXC_R_PWRSEQ_GP1                   ((uint32_t)0x0000004CUL) 
#define MXC_F_PWRSEQ_LPCN_RAMRET0_POS                  0 
#define MXC_F_PWRSEQ_LPCN_RAMRET0                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET0_POS)) 
#define MXC_F_PWRSEQ_LPCN_RAMRET1_POS                  1 
#define MXC_F_PWRSEQ_LPCN_RAMRET1                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET1_POS)) 
#define MXC_F_PWRSEQ_LPCN_RAMRET2_POS                  2 
#define MXC_F_PWRSEQ_LPCN_RAMRET2                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET2_POS)) 
#define MXC_F_PWRSEQ_LPCN_RAMRET3_POS                  3 
#define MXC_F_PWRSEQ_LPCN_RAMRET3                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET3_POS)) 
#define MXC_F_PWRSEQ_LPCN_RAMRET4_POS                  4 
#define MXC_F_PWRSEQ_LPCN_RAMRET4                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET4_POS)) 
#define MXC_F_PWRSEQ_LPCN_RAMRET5_POS                  5 
#define MXC_F_PWRSEQ_LPCN_RAMRET5                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET5_POS)) 
#define MXC_F_PWRSEQ_LPCN_RAMRET6_POS                  6 
#define MXC_F_PWRSEQ_LPCN_RAMRET6                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET6_POS)) 
#define MXC_F_PWRSEQ_LPCN_RAMRET8_POS                  7 
#define MXC_F_PWRSEQ_LPCN_RAMRET8                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET8_POS)) 
#define MXC_F_PWRSEQ_LPCN_ISOCLK_SELECT_POS            8 
#define MXC_F_PWRSEQ_LPCN_ISOCLK_SELECT                ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_ISOCLK_SELECT_POS)) 
#define MXC_F_PWRSEQ_LPCN_FAST_ENTRY_DIS_POS           9 
#define MXC_F_PWRSEQ_LPCN_FAST_ENTRY_DIS               ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FAST_ENTRY_DIS_POS)) 
#define MXC_F_PWRSEQ_LPCN_BGOFF_POS                    11 
#define MXC_F_PWRSEQ_LPCN_BGOFF                        ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BGOFF_POS)) 
#define MXC_F_PWRSEQ_LPCN_WKRST_POS                    31 
#define MXC_F_PWRSEQ_LPCN_WKRST                        ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_WKRST_POS)) 
#define MXC_F_PWRSEQ_LPWKST0_WAKEST_POS                0 
#define MXC_F_PWRSEQ_LPWKST0_WAKEST                    ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPWKST0_WAKEST_POS)) 
#define MXC_F_PWRSEQ_LPWKEN0_WAKEEN_POS                0 
#define MXC_F_PWRSEQ_LPWKEN0_WAKEEN                    ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKEN0_WAKEEN_POS)) 
#define MXC_F_PWRSEQ_LPWKST1_WAKEST_POS                0 
#define MXC_F_PWRSEQ_LPWKST1_WAKEST                    ((uint32_t)(0x3FFUL << MXC_F_PWRSEQ_LPWKST1_WAKEST_POS)) 
#define MXC_F_PWRSEQ_LPWKEN1_WAKEEN_POS                0 
#define MXC_F_PWRSEQ_LPWKEN1_WAKEEN                    ((uint32_t)(0x3FFUL << MXC_F_PWRSEQ_LPWKEN1_WAKEEN_POS)) 
#define MXC_F_PWRSEQ_LPWKST2_WAKEST_POS                0 
#define MXC_F_PWRSEQ_LPWKST2_WAKEST                    ((uint32_t)(0xFFUL << MXC_F_PWRSEQ_LPWKST2_WAKEST_POS)) 
#define MXC_F_PWRSEQ_LPWKEN2_WAKEEN_POS                0 
#define MXC_F_PWRSEQ_LPWKEN2_WAKEEN                    ((uint32_t)(0xFFUL << MXC_F_PWRSEQ_LPWKEN2_WAKEEN_POS)) 
#define MXC_F_PWRSEQ_LPWKST3_WAKEST_POS                0 
#define MXC_F_PWRSEQ_LPWKST3_WAKEST                    ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKST3_WAKEST_POS)) 
#define MXC_F_PWRSEQ_LPWKEN3_WAKEEN_POS                0 
#define MXC_F_PWRSEQ_LPWKEN3_WAKEEN                    ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKEN3_WAKEEN_POS)) 
#define MXC_F_PWRSEQ_LPWKST4_WAKEST_POS                0 
#define MXC_F_PWRSEQ_LPWKST4_WAKEST                    ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKST4_WAKEST_POS)) 
#define MXC_F_PWRSEQ_LPWKEN4_WAKEEN_POS                0 
#define MXC_F_PWRSEQ_LPWKEN4_WAKEEN                    ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKEN4_WAKEEN_POS)) 
#define MXC_F_PWRSEQ_LPPWST_AINCOMP0_POS               4 
#define MXC_F_PWRSEQ_LPPWST_AINCOMP0                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP0_POS)) 
#define MXC_F_PWRSEQ_LPPWST_BACKUP_POS                 16 
#define MXC_F_PWRSEQ_LPPWST_BACKUP                     ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_BACKUP_POS)) 
#define MXC_F_PWRSEQ_LPPWST_RESET_POS                  17 
#define MXC_F_PWRSEQ_LPPWST_RESET                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_RESET_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_USBLS_POS                  0 
#define MXC_F_PWRSEQ_LPPWEN_USBLS                      ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPPWEN_USBLS_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_USBVBUS_POS                2 
#define MXC_F_PWRSEQ_LPPWEN_USBVBUS                    ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_USBVBUS_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_AINCOMP0_POS               4 
#define MXC_F_PWRSEQ_LPPWEN_AINCOMP0                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_AINCOMP0_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_WDT0_POS                   8 
#define MXC_F_PWRSEQ_LPPWEN_WDT0                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_WDT0_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_WDT1_POS                   9 
#define MXC_F_PWRSEQ_LPPWEN_WDT1                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_WDT1_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_CPU1_POS                   10 
#define MXC_F_PWRSEQ_LPPWEN_CPU1                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_CPU1_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_TMR0_POS                   11 
#define MXC_F_PWRSEQ_LPPWEN_TMR0                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_TMR0_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_TMR1_POS                   12 
#define MXC_F_PWRSEQ_LPPWEN_TMR1                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_TMR1_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_TMR2_POS                   13 
#define MXC_F_PWRSEQ_LPPWEN_TMR2                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_TMR2_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_TMR3_POS                   14 
#define MXC_F_PWRSEQ_LPPWEN_TMR3                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_TMR3_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_TMR4_POS                   15 
#define MXC_F_PWRSEQ_LPPWEN_TMR4                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_TMR4_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_TMR5_POS                   16 
#define MXC_F_PWRSEQ_LPPWEN_TMR5                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_TMR5_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_UART0_POS                  17 
#define MXC_F_PWRSEQ_LPPWEN_UART0                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_UART0_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_UART1_POS                  18 
#define MXC_F_PWRSEQ_LPPWEN_UART1                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_UART1_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_UART2_POS                  19 
#define MXC_F_PWRSEQ_LPPWEN_UART2                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_UART2_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_UART3_POS                  20 
#define MXC_F_PWRSEQ_LPPWEN_UART3                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_UART3_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_I2C0_POS                   21 
#define MXC_F_PWRSEQ_LPPWEN_I2C0                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_I2C0_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_I2C1_POS                   22 
#define MXC_F_PWRSEQ_LPPWEN_I2C1                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_I2C1_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_I2C2_POS                   23 
#define MXC_F_PWRSEQ_LPPWEN_I2C2                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_I2C2_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_I2S_POS                    24 
#define MXC_F_PWRSEQ_LPPWEN_I2S                        ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_I2S_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_SPI0_POS                   25 
#define MXC_F_PWRSEQ_LPPWEN_SPI0                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_SPI0_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_LPCMP_POS                  26 
#define MXC_F_PWRSEQ_LPPWEN_LPCMP                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_LPCMP_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_BTLE_POS                   27 
#define MXC_F_PWRSEQ_LPPWEN_BTLE                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_BTLE_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_SPI1_POS                   28 
#define MXC_F_PWRSEQ_LPPWEN_SPI1                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_SPI1_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_SPI2_POS                   29 
#define MXC_F_PWRSEQ_LPPWEN_SPI2                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_SPI2_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_CAN0_POS                   30 
#define MXC_F_PWRSEQ_LPPWEN_CAN0                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_CAN0_POS)) 
#define MXC_F_PWRSEQ_LPPWEN_CAN1_POS                   31 
#define MXC_F_PWRSEQ_LPPWEN_CAN1                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_CAN1_POS)) 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_PWRSEQ_REGS_H_