gcr_regs.h

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/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78000_INCLUDE_GCR_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78000_INCLUDE_GCR_REGS_H_
 
/* **** Includes **** */
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined (__ICCARM__)
  #pragma system_include
#endif
 
#if defined (__CC_ARM)
  #pragma anon_unions
#endif
/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif
#ifndef __R
#define __R  volatile const
#endif
 
/* **** Definitions **** */
 
typedef struct {
    __IO uint32_t sysctrl;              
    __IO uint32_t rst0;                 
    __IO uint32_t clkctrl;              
    __IO uint32_t pm;                   
    __R  uint32_t rsv_0x10_0x17[2];
    __IO uint32_t pclkdiv;              
    __R  uint32_t rsv_0x1c_0x23[2];
    __IO uint32_t pclkdis0;             
    __IO uint32_t memctrl;              
    __IO uint32_t memz;                 
    __R  uint32_t rsv_0x30_0x3f[4];
    __IO uint32_t sysst;                
    __IO uint32_t rst1;                 
    __IO uint32_t pclkdis1;             
    __IO uint32_t eventen;              
    __I  uint32_t revision;             
    __IO uint32_t sysie;                
    __R  uint32_t rsv_0x58_0x63[3];
    __IO uint32_t eccerr;               
    __IO uint32_t eccced;               
    __IO uint32_t eccie;                
    __IO uint32_t eccaddr;              
    __R  uint32_t rsv_0x74_0x7f[3];
    __IO uint32_t gpr;                  
} mxc_gcr_regs_t;
 
/* Register offsets for module GCR */
#define MXC_R_GCR_SYSCTRL                  ((uint32_t)0x00000000UL) 
#define MXC_R_GCR_RST0                     ((uint32_t)0x00000004UL) 
#define MXC_R_GCR_CLKCTRL                  ((uint32_t)0x00000008UL) 
#define MXC_R_GCR_PM                       ((uint32_t)0x0000000CUL) 
#define MXC_R_GCR_PCLKDIV                  ((uint32_t)0x00000018UL) 
#define MXC_R_GCR_PCLKDIS0                 ((uint32_t)0x00000024UL) 
#define MXC_R_GCR_MEMCTRL                  ((uint32_t)0x00000028UL) 
#define MXC_R_GCR_MEMZ                     ((uint32_t)0x0000002CUL) 
#define MXC_R_GCR_SYSST                    ((uint32_t)0x00000040UL) 
#define MXC_R_GCR_RST1                     ((uint32_t)0x00000044UL) 
#define MXC_R_GCR_PCLKDIS1                 ((uint32_t)0x00000048UL) 
#define MXC_R_GCR_EVENTEN                  ((uint32_t)0x0000004CUL) 
#define MXC_R_GCR_REVISION                 ((uint32_t)0x00000050UL) 
#define MXC_R_GCR_SYSIE                    ((uint32_t)0x00000054UL) 
#define MXC_R_GCR_ECCERR                   ((uint32_t)0x00000064UL) 
#define MXC_R_GCR_ECCCED                   ((uint32_t)0x00000068UL) 
#define MXC_R_GCR_ECCIE                    ((uint32_t)0x0000006CUL) 
#define MXC_R_GCR_ECCADDR                  ((uint32_t)0x00000070UL) 
#define MXC_R_GCR_GPR                      ((uint32_t)0x00000080UL) 
#define MXC_F_GCR_SYSCTRL_BSTAPEN_POS                  1 
#define MXC_F_GCR_SYSCTRL_BSTAPEN                      ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_BSTAPEN_POS)) 
#define MXC_F_GCR_SYSCTRL_FLASH_PAGE_FLIP_POS          4 
#define MXC_F_GCR_SYSCTRL_FLASH_PAGE_FLIP              ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_FLASH_PAGE_FLIP_POS)) 
#define MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS               6 
#define MXC_F_GCR_SYSCTRL_ICC0_FLUSH                   ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS)) 
#define MXC_F_GCR_SYSCTRL_ROMDONE_POS                  12 
#define MXC_F_GCR_SYSCTRL_ROMDONE                      ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ROMDONE_POS)) 
#define MXC_F_GCR_SYSCTRL_CCHK_POS                     13 
#define MXC_F_GCR_SYSCTRL_CCHK                         ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CCHK_POS)) 
#define MXC_F_GCR_SYSCTRL_SWD_DIS_POS                  14 
#define MXC_F_GCR_SYSCTRL_SWD_DIS                      ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_SWD_DIS_POS)) 
#define MXC_F_GCR_SYSCTRL_CHKRES_POS                   15 
#define MXC_F_GCR_SYSCTRL_CHKRES                       ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CHKRES_POS)) 
#define MXC_F_GCR_SYSCTRL_OVR_POS                      16 
#define MXC_F_GCR_SYSCTRL_OVR                          ((uint32_t)(0x3UL << MXC_F_GCR_SYSCTRL_OVR_POS)) 
#define MXC_F_GCR_RST0_DMA_POS                         0 
#define MXC_F_GCR_RST0_DMA                             ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS)) 
#define MXC_F_GCR_RST0_WDT0_POS                        1 
#define MXC_F_GCR_RST0_WDT0                            ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS)) 
#define MXC_F_GCR_RST0_GPIO0_POS                       2 
#define MXC_F_GCR_RST0_GPIO0                           ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS)) 
#define MXC_F_GCR_RST0_GPIO1_POS                       3 
#define MXC_F_GCR_RST0_GPIO1                           ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO1_POS)) 
#define MXC_F_GCR_RST0_TMR0_POS                        5 
#define MXC_F_GCR_RST0_TMR0                            ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR0_POS)) 
#define MXC_F_GCR_RST0_TMR1_POS                        6 
#define MXC_F_GCR_RST0_TMR1                            ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR1_POS)) 
#define MXC_F_GCR_RST0_TMR2_POS                        7 
#define MXC_F_GCR_RST0_TMR2                            ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR2_POS)) 
#define MXC_F_GCR_RST0_TMR3_POS                        8 
#define MXC_F_GCR_RST0_TMR3                            ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR3_POS)) 
#define MXC_F_GCR_RST0_UART0_POS                       11 
#define MXC_F_GCR_RST0_UART0                           ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS)) 
#define MXC_F_GCR_RST0_UART1_POS                       12 
#define MXC_F_GCR_RST0_UART1                           ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS)) 
#define MXC_F_GCR_RST0_SPI1_POS                        13 
#define MXC_F_GCR_RST0_SPI1                            ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS)) 
#define MXC_F_GCR_RST0_I2C0_POS                        16 
#define MXC_F_GCR_RST0_I2C0                            ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS)) 
#define MXC_F_GCR_RST0_RTC_POS                         17 
#define MXC_F_GCR_RST0_RTC                             ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS)) 
#define MXC_F_GCR_RST0_SMPHR_POS                       22 
#define MXC_F_GCR_RST0_SMPHR                           ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SMPHR_POS)) 
#define MXC_F_GCR_RST0_TRNG_POS                        24 
#define MXC_F_GCR_RST0_TRNG                            ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TRNG_POS)) 
#define MXC_F_GCR_RST0_CNN_POS                         25 
#define MXC_F_GCR_RST0_CNN                             ((uint32_t)(0x1UL << MXC_F_GCR_RST0_CNN_POS)) 
#define MXC_F_GCR_RST0_ADC_POS                         26 
#define MXC_F_GCR_RST0_ADC                             ((uint32_t)(0x1UL << MXC_F_GCR_RST0_ADC_POS)) 
#define MXC_F_GCR_RST0_UART2_POS                       28 
#define MXC_F_GCR_RST0_UART2                           ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART2_POS)) 
#define MXC_F_GCR_RST0_SOFT_POS                        29 
#define MXC_F_GCR_RST0_SOFT                            ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS)) 
#define MXC_F_GCR_RST0_PERIPH_POS                      30 
#define MXC_F_GCR_RST0_PERIPH                          ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS)) 
#define MXC_F_GCR_RST0_SYS_POS                         31 
#define MXC_F_GCR_RST0_SYS                             ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYS_POS)) 
#define MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS               6 
#define MXC_F_GCR_CLKCTRL_SYSCLK_DIV                   ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)) 
#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1              ((uint32_t)0x0UL) 
#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1              (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) 
#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2              ((uint32_t)0x1UL) 
#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2              (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) 
#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4              ((uint32_t)0x2UL) 
#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4              (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) 
#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8              ((uint32_t)0x3UL) 
#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8              (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) 
#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16             ((uint32_t)0x4UL) 
#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16             (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) 
#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32             ((uint32_t)0x5UL) 
#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32             (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) 
#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64             ((uint32_t)0x6UL) 
#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64             (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) 
#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128            ((uint32_t)0x7UL) 
#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128            (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) 
#define MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS               9 
#define MXC_F_GCR_CLKCTRL_SYSCLK_SEL                   ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)) 
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO               ((uint32_t)0x0UL) 
#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ISO               (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) 
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO              ((uint32_t)0x3UL) 
#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO              (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) 
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO               ((uint32_t)0x4UL) 
#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO               (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) 
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO              ((uint32_t)0x5UL) 
#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO              (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) 
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO             ((uint32_t)0x6UL) 
#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO             (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) 
#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK            ((uint32_t)0x7UL) 
#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK            (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) 
#define MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS               13 
#define MXC_F_GCR_CLKCTRL_SYSCLK_RDY                   ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS)) 
#define MXC_F_GCR_CLKCTRL_ERTCO_EN_POS                 17 
#define MXC_F_GCR_CLKCTRL_ERTCO_EN                     ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_EN_POS)) 
#define MXC_F_GCR_CLKCTRL_ISO_EN_POS                   18 
#define MXC_F_GCR_CLKCTRL_ISO_EN                       ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ISO_EN_POS)) 
#define MXC_F_GCR_CLKCTRL_IPO_EN_POS                   19 
#define MXC_F_GCR_CLKCTRL_IPO_EN                       ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_EN_POS)) 
#define MXC_F_GCR_CLKCTRL_IBRO_EN_POS                  20 
#define MXC_F_GCR_CLKCTRL_IBRO_EN                      ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_EN_POS)) 
#define MXC_F_GCR_CLKCTRL_IBRO_VS_POS                  21 
#define MXC_F_GCR_CLKCTRL_IBRO_VS                      ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_VS_POS)) 
#define MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS                25 
#define MXC_F_GCR_CLKCTRL_ERTCO_RDY                    ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS)) 
#define MXC_F_GCR_CLKCTRL_ISO_RDY_POS                  26 
#define MXC_F_GCR_CLKCTRL_ISO_RDY                      ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ISO_RDY_POS)) 
#define MXC_F_GCR_CLKCTRL_IPO_RDY_POS                  27 
#define MXC_F_GCR_CLKCTRL_IPO_RDY                      ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_RDY_POS)) 
#define MXC_F_GCR_CLKCTRL_IBRO_RDY_POS                 28 
#define MXC_F_GCR_CLKCTRL_IBRO_RDY                     ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_RDY_POS)) 
#define MXC_F_GCR_CLKCTRL_INRO_RDY_POS                 29 
#define MXC_F_GCR_CLKCTRL_INRO_RDY                     ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_INRO_RDY_POS)) 
#define MXC_F_GCR_PM_MODE_POS                          0 
#define MXC_F_GCR_PM_MODE                              ((uint32_t)(0xFUL << MXC_F_GCR_PM_MODE_POS)) 
#define MXC_V_GCR_PM_MODE_ACTIVE                       ((uint32_t)0x0UL) 
#define MXC_S_GCR_PM_MODE_ACTIVE                       (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) 
#define MXC_V_GCR_PM_MODE_SLEEP                        ((uint32_t)0x1UL) 
#define MXC_S_GCR_PM_MODE_SLEEP                        (MXC_V_GCR_PM_MODE_SLEEP << MXC_F_GCR_PM_MODE_POS) 
#define MXC_V_GCR_PM_MODE_STANDBY                      ((uint32_t)0x2UL) 
#define MXC_S_GCR_PM_MODE_STANDBY                      (MXC_V_GCR_PM_MODE_STANDBY << MXC_F_GCR_PM_MODE_POS) 
#define MXC_V_GCR_PM_MODE_BACKUP                       ((uint32_t)0x4UL) 
#define MXC_S_GCR_PM_MODE_BACKUP                       (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) 
#define MXC_V_GCR_PM_MODE_LPM                          ((uint32_t)0x8UL) 
#define MXC_S_GCR_PM_MODE_LPM                          (MXC_V_GCR_PM_MODE_LPM << MXC_F_GCR_PM_MODE_POS) 
#define MXC_V_GCR_PM_MODE_UPM                          ((uint32_t)0x9UL) 
#define MXC_S_GCR_PM_MODE_UPM                          (MXC_V_GCR_PM_MODE_UPM << MXC_F_GCR_PM_MODE_POS) 
#define MXC_V_GCR_PM_MODE_POWERDOWN                    ((uint32_t)0xAUL) 
#define MXC_S_GCR_PM_MODE_POWERDOWN                    (MXC_V_GCR_PM_MODE_POWERDOWN << MXC_F_GCR_PM_MODE_POS) 
#define MXC_F_GCR_PM_GPIO_WE_POS                       4 
#define MXC_F_GCR_PM_GPIO_WE                           ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIO_WE_POS)) 
#define MXC_F_GCR_PM_RTC_WE_POS                        5 
#define MXC_F_GCR_PM_RTC_WE                            ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTC_WE_POS)) 
#define MXC_F_GCR_PM_WUT_WE_POS                        7 
#define MXC_F_GCR_PM_WUT_WE                            ((uint32_t)(0x1UL << MXC_F_GCR_PM_WUT_WE_POS)) 
#define MXC_F_GCR_PM_AINCOMP_WE_POS                    9 
#define MXC_F_GCR_PM_AINCOMP_WE                        ((uint32_t)(0x1UL << MXC_F_GCR_PM_AINCOMP_WE_POS)) 
#define MXC_F_GCR_PM_ISO_PD_POS                        15 
#define MXC_F_GCR_PM_ISO_PD                            ((uint32_t)(0x1UL << MXC_F_GCR_PM_ISO_PD_POS)) 
#define MXC_F_GCR_PM_IPO_PD_POS                        16 
#define MXC_F_GCR_PM_IPO_PD                            ((uint32_t)(0x1UL << MXC_F_GCR_PM_IPO_PD_POS)) 
#define MXC_F_GCR_PM_IBRO_PD_POS                       17 
#define MXC_F_GCR_PM_IBRO_PD                           ((uint32_t)(0x1UL << MXC_F_GCR_PM_IBRO_PD_POS)) 
#define MXC_F_GCR_PCLKDIV_ADCFRQ_POS                   10 
#define MXC_F_GCR_PCLKDIV_ADCFRQ                       ((uint32_t)(0xFUL << MXC_F_GCR_PCLKDIV_ADCFRQ_POS)) 
#define MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS                14 
#define MXC_F_GCR_PCLKDIV_CNNCLKDIV                    ((uint32_t)(0x7UL << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS)) 
#define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV2               ((uint32_t)0x0UL) 
#define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV2               (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV2 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS) 
#define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV4               ((uint32_t)0x1UL) 
#define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV4               (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV4 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS) 
#define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV8               ((uint32_t)0x2UL) 
#define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV8               (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV8 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS) 
#define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV16              ((uint32_t)0x3UL) 
#define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV16              (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV16 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS) 
#define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV1               ((uint32_t)0x4UL) 
#define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV1               (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV1 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS) 
#define MXC_F_GCR_PCLKDIV_CNNCLKSEL_POS                17 
#define MXC_F_GCR_PCLKDIV_CNNCLKSEL                    ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIV_CNNCLKSEL_POS)) 
#define MXC_F_GCR_PCLKDIS0_GPIO0_POS                   0 
#define MXC_F_GCR_PCLKDIS0_GPIO0                       ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO0_POS)) 
#define MXC_F_GCR_PCLKDIS0_GPIO1_POS                   1 
#define MXC_F_GCR_PCLKDIS0_GPIO1                       ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO1_POS)) 
#define MXC_F_GCR_PCLKDIS0_DMA_POS                     5 
#define MXC_F_GCR_PCLKDIS0_DMA                         ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_DMA_POS)) 
#define MXC_F_GCR_PCLKDIS0_SPI1_POS                    6 
#define MXC_F_GCR_PCLKDIS0_SPI1                        ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI1_POS)) 
#define MXC_F_GCR_PCLKDIS0_UART0_POS                   9 
#define MXC_F_GCR_PCLKDIS0_UART0                       ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART0_POS)) 
#define MXC_F_GCR_PCLKDIS0_UART1_POS                   10 
#define MXC_F_GCR_PCLKDIS0_UART1                       ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART1_POS)) 
#define MXC_F_GCR_PCLKDIS0_I2C0_POS                    13 
#define MXC_F_GCR_PCLKDIS0_I2C0                        ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C0_POS)) 
#define MXC_F_GCR_PCLKDIS0_TMR0_POS                    15 
#define MXC_F_GCR_PCLKDIS0_TMR0                        ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR0_POS)) 
#define MXC_F_GCR_PCLKDIS0_TMR1_POS                    16 
#define MXC_F_GCR_PCLKDIS0_TMR1                        ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR1_POS)) 
#define MXC_F_GCR_PCLKDIS0_TMR2_POS                    17 
#define MXC_F_GCR_PCLKDIS0_TMR2                        ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR2_POS)) 
#define MXC_F_GCR_PCLKDIS0_TMR3_POS                    18 
#define MXC_F_GCR_PCLKDIS0_TMR3                        ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR3_POS)) 
#define MXC_F_GCR_PCLKDIS0_ADC_POS                     23 
#define MXC_F_GCR_PCLKDIS0_ADC                         ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_ADC_POS)) 
#define MXC_F_GCR_PCLKDIS0_CNN_POS                     25 
#define MXC_F_GCR_PCLKDIS0_CNN                         ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_CNN_POS)) 
#define MXC_F_GCR_PCLKDIS0_I2C1_POS                    28 
#define MXC_F_GCR_PCLKDIS0_I2C1                        ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C1_POS)) 
#define MXC_F_GCR_PCLKDIS0_PT_POS                      29 
#define MXC_F_GCR_PCLKDIS0_PT                          ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_PT_POS)) 
#define MXC_F_GCR_MEMCTRL_FWS_POS                      0 
#define MXC_F_GCR_MEMCTRL_FWS                          ((uint32_t)(0x7UL << MXC_F_GCR_MEMCTRL_FWS_POS)) 
#define MXC_F_GCR_MEMCTRL_SYSRAM0ECC_POS               16 
#define MXC_F_GCR_MEMCTRL_SYSRAM0ECC                   ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_SYSRAM0ECC_POS)) 
#define MXC_F_GCR_MEMZ_RAM0_POS                        0 
#define MXC_F_GCR_MEMZ_RAM0                            ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM0_POS)) 
#define MXC_F_GCR_MEMZ_RAM1_POS                        1 
#define MXC_F_GCR_MEMZ_RAM1                            ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM1_POS)) 
#define MXC_F_GCR_MEMZ_RAM2_POS                        2 
#define MXC_F_GCR_MEMZ_RAM2                            ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM2_POS)) 
#define MXC_F_GCR_MEMZ_RAM3_POS                        3 
#define MXC_F_GCR_MEMZ_RAM3                            ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM3_POS)) 
#define MXC_F_GCR_MEMZ_SYSRAM0ECC_POS                  4 
#define MXC_F_GCR_MEMZ_SYSRAM0ECC                      ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_SYSRAM0ECC_POS)) 
#define MXC_F_GCR_MEMZ_ICC0_POS                        5 
#define MXC_F_GCR_MEMZ_ICC0                            ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC0_POS)) 
#define MXC_F_GCR_MEMZ_ICC1_POS                        6 
#define MXC_F_GCR_MEMZ_ICC1                            ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC1_POS)) 
#define MXC_F_GCR_SYSST_ICELOCK_POS                    0 
#define MXC_F_GCR_SYSST_ICELOCK                        ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICELOCK_POS)) 
#define MXC_F_GCR_RST1_I2C1_POS                        0 
#define MXC_F_GCR_RST1_I2C1                            ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) 
#define MXC_F_GCR_RST1_PT_POS                          1 
#define MXC_F_GCR_RST1_PT                              ((uint32_t)(0x1UL << MXC_F_GCR_RST1_PT_POS)) 
#define MXC_F_GCR_RST1_OWM_POS                         7 
#define MXC_F_GCR_RST1_OWM                             ((uint32_t)(0x1UL << MXC_F_GCR_RST1_OWM_POS)) 
#define MXC_F_GCR_RST1_CRC_POS                         9 
#define MXC_F_GCR_RST1_CRC                             ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CRC_POS)) 
#define MXC_F_GCR_RST1_AES_POS                         10 
#define MXC_F_GCR_RST1_AES                             ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AES_POS)) 
#define MXC_F_GCR_RST1_SPI0_POS                        11 
#define MXC_F_GCR_RST1_SPI0                            ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPI0_POS)) 
#define MXC_F_GCR_RST1_SMPHR_POS                       16 
#define MXC_F_GCR_RST1_SMPHR                           ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SMPHR_POS)) 
#define MXC_F_GCR_RST1_I2S_POS                         19 
#define MXC_F_GCR_RST1_I2S                             ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS)) 
#define MXC_F_GCR_RST1_I2C2_POS                        20 
#define MXC_F_GCR_RST1_I2C2                            ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C2_POS)) 
#define MXC_F_GCR_RST1_DVS_POS                         24 
#define MXC_F_GCR_RST1_DVS                             ((uint32_t)(0x1UL << MXC_F_GCR_RST1_DVS_POS)) 
#define MXC_F_GCR_RST1_SIMO_POS                        25 
#define MXC_F_GCR_RST1_SIMO                            ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SIMO_POS)) 
#define MXC_F_GCR_RST1_CPU1_POS                        31 
#define MXC_F_GCR_RST1_CPU1                            ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CPU1_POS)) 
#define MXC_F_GCR_PCLKDIS1_UART2_POS                   1 
#define MXC_F_GCR_PCLKDIS1_UART2                       ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART2_POS)) 
#define MXC_F_GCR_PCLKDIS1_TRNG_POS                    2 
#define MXC_F_GCR_PCLKDIS1_TRNG                        ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_TRNG_POS)) 
#define MXC_F_GCR_PCLKDIS1_SMPHR_POS                   9 
#define MXC_F_GCR_PCLKDIS1_SMPHR                       ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SMPHR_POS)) 
#define MXC_F_GCR_PCLKDIS1_OWM_POS                     13 
#define MXC_F_GCR_PCLKDIS1_OWM                         ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_OWM_POS)) 
#define MXC_F_GCR_PCLKDIS1_CRC_POS                     14 
#define MXC_F_GCR_PCLKDIS1_CRC                         ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CRC_POS)) 
#define MXC_F_GCR_PCLKDIS1_AES_POS                     15 
#define MXC_F_GCR_PCLKDIS1_AES                         ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_AES_POS)) 
#define MXC_F_GCR_PCLKDIS1_SPI0_POS                    16 
#define MXC_F_GCR_PCLKDIS1_SPI0                        ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SPI0_POS)) 
#define MXC_F_GCR_PCLKDIS1_PCIF_POS                    18 
#define MXC_F_GCR_PCLKDIS1_PCIF                        ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_PCIF_POS)) 
#define MXC_F_GCR_PCLKDIS1_I2S_POS                     23 
#define MXC_F_GCR_PCLKDIS1_I2S                         ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2S_POS)) 
#define MXC_F_GCR_PCLKDIS1_I2C2_POS                    24 
#define MXC_F_GCR_PCLKDIS1_I2C2                        ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2C2_POS)) 
#define MXC_F_GCR_PCLKDIS1_WDT0_POS                    27 
#define MXC_F_GCR_PCLKDIS1_WDT0                        ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WDT0_POS)) 
#define MXC_F_GCR_PCLKDIS1_CPU1_POS                    31 
#define MXC_F_GCR_PCLKDIS1_CPU1                        ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CPU1_POS)) 
#define MXC_F_GCR_EVENTEN_DMA_POS                      0 
#define MXC_F_GCR_EVENTEN_DMA                          ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_DMA_POS)) 
#define MXC_F_GCR_EVENTEN_RX_POS                       1 
#define MXC_F_GCR_EVENTEN_RX                           ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_RX_POS)) 
#define MXC_F_GCR_EVENTEN_TX_POS                       2 
#define MXC_F_GCR_EVENTEN_TX                           ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_TX_POS)) 
#define MXC_F_GCR_REVISION_REVISION_POS                0 
#define MXC_F_GCR_REVISION_REVISION                    ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS)) 
#define MXC_F_GCR_SYSIE_ICEUNLOCK_POS                  0 
#define MXC_F_GCR_SYSIE_ICEUNLOCK                      ((uint32_t)(0x1UL << MXC_F_GCR_SYSIE_ICEUNLOCK_POS)) 
#define MXC_F_GCR_ECCERR_RAM_POS                       0 
#define MXC_F_GCR_ECCERR_RAM                           ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM_POS)) 
#define MXC_F_GCR_ECCCED_RAM_POS                       0 
#define MXC_F_GCR_ECCCED_RAM                           ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM_POS)) 
#define MXC_F_GCR_ECCIE_RAM_POS                        0 
#define MXC_F_GCR_ECCIE_RAM                            ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM_POS)) 
#define MXC_F_GCR_ECCADDR_ECCERRAD_POS                 0 
#define MXC_F_GCR_ECCADDR_ECCERRAD                     ((uint32_t)(0xFFFFFFFFUL << MXC_F_GCR_ECCADDR_ECCERRAD_POS)) 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78000_INCLUDE_GCR_REGS_H_