spi.h

 
/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78002_SPI_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78002_SPI_H_
 
/***** includes *******/
#include <stdbool.h>
#include "mxc_assert.h"
#include "mxc_device.h"
#include "mxc_lock.h"
#include "mxc_pins.h"
#include "mxc_sys.h"
#include "gpio.h"
#include "spi_regs.h"
#include "dma_regs.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
/***** Definitions *****/
 
// clang-format off
 
typedef enum {
    MXC_SPI_TYPE_SLAVE = 0,
    MXC_SPI_TYPE_TARGET = 0,
    MXC_SPI_TYPE_MASTER = 1,
    MXC_SPI_TYPE_CONTROLLER = 1
} mxc_spi_type_t;
 
typedef enum {
    MXC_SPI_TSCONTROL_HW_AUTO = 0, // Automatically by hardware
    MXC_SPI_TSCONTROL_SW_APP = 1   // Through software in the application
} mxc_spi_tscontrol_t;
 
typedef enum {
    MXC_SPI_STATE_READY = 0, // Ready for transaction
    MXC_SPI_STATE_BUSY = 1   // Busy transferring
} mxc_spi_state_t;
 
typedef enum {
    MXC_SPI_INTERFACE_STANDARD = 0,
    MXC_SPI_INTERFACE_4WIRE = 0,
    MXC_SPI_INTERFACE_QUAD = 1,
    MXC_SPI_INTERFACE_3WIRE = 2,
    MXC_SPI_INTERFACE_DUAL = 3
} mxc_spi_interface_t;
 
typedef enum {
    MXC_SPI_CLKMODE_0 = 0, // CPOL: 0    CPHA: 0
    MXC_SPI_CLKMODE_1 = 1, // CPOL: 0    CPHA: 1
    MXC_SPI_CLKMODE_2 = 2, // CPOL: 1    CPHA: 0
    MXC_SPI_CLKMODE_3 = 3  // CPOL: 1    CPHA: 1
} mxc_spi_clkmode_t;
 
 
typedef enum {
    SPI_WIDTH_3WIRE,    
    SPI_WIDTH_STANDARD, 
    SPI_WIDTH_DUAL,     
    SPI_WIDTH_QUAD,     
} mxc_spi_width_t;
 
typedef enum {
    SPI_MODE_0, 
    SPI_MODE_1, 
    SPI_MODE_2, 
    SPI_MODE_3, 
} mxc_spi_mode_t;
 
typedef struct _mxc_spi_req_t mxc_spi_req_t;
 
typedef void (*mxc_spi_callback_t)(void *, int result);
typedef mxc_spi_callback_t spi_complete_cb_t; // Support SPI v1 name.
 
typedef struct _mxc_spi_pins_t mxc_spi_pins_t;
struct _mxc_spi_pins_t {
    bool ss0;                   
    bool ss1;                   
    bool ss2;                   
 
    bool vddioh;                
 
    bool clock;                 
    bool miso;                  
    bool mosi;                  
    bool sdio2;                 
    bool sdio3;                 
 
    mxc_gpio_drvstr_t drvstr;   
};
 
typedef struct {
    // SPI Settings.
    mxc_spi_regs_t *spi;                // Selected SPI Instance
    mxc_spi_clkmode_t clk_mode;         // Clock modes
    uint8_t frame_size;                 // Number of bits per character sent
 
    // DMA Settings.
    bool use_dma_tx;                    // Enable DMA TX.
    bool use_dma_rx;                    // Enable DMA RX. (use_dma_tx must be true to use DMA RX).
    mxc_dma_regs_t *dma;                // Select DMA instance for SPI DMA.
} mxc_spi_cfg_t;
 
// Suppport names for backwards compatibility.
struct _mxc_spi_req_t {
    mxc_spi_regs_t *spi;     // Pointer to SPI registers
    int ssIdx;
    int ssDeassert;
    uint8_t *txData;
    uint8_t *rxData;
    uint32_t txLen; // Number of frames to be stored in txData
    uint32_t rxLen; // Number of frames to be stored in rxData
    uint32_t txCnt; // Number of bytes transmitted from txData (Unused for SPI v2)
    uint32_t rxCnt; // Number of bytes stored in rxData (Unused for SPI v2)
    mxc_spi_callback_t completeCB; // completeCB
    uint16_t txDummyValue; // Value of dummy bytes to be sent
};
// clang-format on
 
/* ************************************************************************* */
/* Control/Configuration functions                                           */
/* ************************************************************************* */
 
int MXC_SPI_Init(mxc_spi_regs_t *spi, mxc_spi_type_t controller_target, mxc_spi_interface_t if_mode,
                 int numTargets, uint8_t ts_active_pol_mask, uint32_t freq, mxc_spi_pins_t pins);
 
int MXC_SPI_Config(mxc_spi_cfg_t *cfg);
 
int MXC_SPI_ConfigStruct(mxc_spi_cfg_t *cfg, bool use_dma_tx, bool use_dma_rx);
 
int MXC_SPI_Shutdown(mxc_spi_regs_t *spi);
 
unsigned int MXC_SPI_GetFlags(mxc_spi_regs_t *spi);
 
void MXC_SPI_ClearFlags(mxc_spi_regs_t *spi);
 
void MXC_SPI_EnableInt(mxc_spi_regs_t *spi, unsigned int intEn);
 
void MXC_SPI_DisableInt(mxc_spi_regs_t *spi, unsigned int intDis);
 
int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t *spi);
 
int MXC_SPI_SetTSControl(mxc_spi_regs_t *spi, mxc_spi_tscontrol_t ts_control);
 
int MXC_SPI_SetFrequency(mxc_spi_regs_t *spi, unsigned int hz);
 
unsigned int MXC_SPI_GetFrequency(mxc_spi_regs_t *spi);
 
int MXC_SPI_SetFrameSize(mxc_spi_regs_t *spi, int frame_size);
 
int MXC_SPI_GetFrameSize(mxc_spi_regs_t *spi);
 
int MXC_SPI_SetInterface(mxc_spi_regs_t *spi, mxc_spi_interface_t if_mode);
 
mxc_spi_interface_t MXC_SPI_GetInterface(mxc_spi_regs_t *spi);
 
int MXC_SPI_SetClkMode(mxc_spi_regs_t *spi, mxc_spi_clkmode_t clk_mode);
 
mxc_spi_clkmode_t MXC_SPI_GetClkMode(mxc_spi_regs_t *spi);
 
int MXC_SPI_SetCallback(mxc_spi_regs_t *spi, mxc_spi_callback_t callback, void *data);
 
int MXC_SPI_GetActive(mxc_spi_regs_t *spi);
 
int MXC_SPI_ReadyForSleep(mxc_spi_regs_t *spi);
 
int MXC_SPI_StartTransmission(mxc_spi_regs_t *spi);
 
int MXC_SPI_AbortTransmission(mxc_spi_regs_t *spi);
 
void MXC_SPI_AbortAsync(mxc_spi_regs_t *spi);
 
unsigned int MXC_SPI_GetTXFIFOAvailable(mxc_spi_regs_t *spi);
 
unsigned int MXC_SPI_GetRXFIFOAvailable(mxc_spi_regs_t *spi);
 
void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi);
 
void MXC_SPI_ClearRXFIFO(mxc_spi_regs_t *spi);
 
int MXC_SPI_SetTXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes);
 
int MXC_SPI_SetRXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes);
 
unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi);
 
unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi);
 
 
int MXC_SPI_SetDataSize(mxc_spi_regs_t *spi, int dataSize);
 
int MXC_SPI_GetDataSize(mxc_spi_regs_t *spi);
 
int MXC_SPI_SetWidth(mxc_spi_regs_t *spi, mxc_spi_width_t spiWidth);
 
mxc_spi_width_t MXC_SPI_GetWidth(mxc_spi_regs_t *spi);
 
int MXC_SPI_SetSlave(mxc_spi_regs_t *spi, int ssIdx);
 
int MXC_SPI_GetSlave(mxc_spi_regs_t *spi);
 
int MXC_SPI_SetMode(mxc_spi_regs_t *spi, mxc_spi_mode_t spiMode);
 
mxc_spi_mode_t MXC_SPI_GetMode(mxc_spi_regs_t *spi);
 
unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len);
 
unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len);
 
int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t *spi, unsigned int defaultTXData);
 
void MXC_SPI_HWSSControl(mxc_spi_regs_t *spi, int state);
 
/* ** DMA Functions ** */
 
int MXC_SPI_DMA_Init(mxc_spi_regs_t *spi, mxc_dma_regs_t *dma, bool use_dma_tx, bool use_dma_rx);
 
bool MXC_SPI_DMA_GetInitialized(mxc_spi_regs_t *spi);
 
int MXC_SPI_DMA_GetTXChannel(mxc_spi_regs_t *spi);
 
int MXC_SPI_DMA_GetRXChannel(mxc_spi_regs_t *spi);
 
int MXC_SPI_DMA_SetRequestSelect(mxc_spi_regs_t *spi, bool use_dma_tx, bool use_dma_rx);
 
/* ** Transaction Functions ** */
 
int MXC_SPI_MasterTransaction(mxc_spi_req_t *req);
 
int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t *req);
 
int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req);
 
int MXC_SPI_ControllerTransaction(mxc_spi_req_t *req);
 
int MXC_SPI_ControllerTransactionAsync(mxc_spi_req_t *req);
 
int MXC_SPI_ControllerTransactionDMA(mxc_spi_req_t *req);
 
int MXC_SPI_ControllerTransactionDMAB(mxc_spi_req_t *req);
 
int MXC_SPI_SlaveTransaction(mxc_spi_req_t *req);
 
int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t *req);
 
int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req);
 
int MXC_SPI_TargetTransaction(mxc_spi_req_t *req);
 
int MXC_SPI_TargetTransactionAsync(mxc_spi_req_t *req);
 
int MXC_SPI_TargetTransactionDMA(mxc_spi_req_t *req);
 
/* ** Handler Functions ** */
 
void MXC_SPI_AsyncHandler(mxc_spi_regs_t *spi);
 
void MXC_SPI_Handler(mxc_spi_regs_t *spi);
 
void MXC_SPI_DMA_TX_Handler(mxc_spi_regs_t *spi);
 
void MXC_SPI_DMA_RX_Handler(mxc_spi_regs_t *spi);
 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78002_SPI_H_