trimsir_regs.h

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/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_TRIMSIR_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_TRIMSIR_REGS_H_
 
/* **** Includes **** */
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined (__ICCARM__)
  #pragma system_include
#endif
 
#if defined (__CC_ARM)
  #pragma anon_unions
#endif
/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif
#ifndef __R
#define __R  volatile const
#endif
 
/* **** Definitions **** */
 
typedef struct {
    __R  uint32_t rsv_0x0_0x7[2];
    __IO uint32_t rtc;                  
    __R  uint32_t rsv_0xc_0x33[10];
    __I  uint32_t simo;                 
    __R  uint32_t rsv_0x38;
    __I  uint32_t ipolo;                
    __IO uint32_t ctrl;                 
    __IO uint32_t inro;                 
} mxc_trimsir_regs_t;
 
/* Register offsets for module TRIMSIR */
#define MXC_R_TRIMSIR_RTC                  ((uint32_t)0x00000008UL) 
#define MXC_R_TRIMSIR_SIMO                 ((uint32_t)0x00000034UL) 
#define MXC_R_TRIMSIR_IPOLO                ((uint32_t)0x0000003CUL) 
#define MXC_R_TRIMSIR_CTRL                 ((uint32_t)0x00000040UL) 
#define MXC_R_TRIMSIR_INRO                 ((uint32_t)0x00000044UL) 
#define MXC_F_TRIMSIR_RTC_X1TRIM_POS                   16 
#define MXC_F_TRIMSIR_RTC_X1TRIM                       ((uint32_t)(0x1FUL << MXC_F_TRIMSIR_RTC_X1TRIM_POS)) 
#define MXC_F_TRIMSIR_RTC_X2TRIM_POS                   21 
#define MXC_F_TRIMSIR_RTC_X2TRIM                       ((uint32_t)(0x1FUL << MXC_F_TRIMSIR_RTC_X2TRIM_POS)) 
#define MXC_F_TRIMSIR_RTC_LOCK_POS                     31 
#define MXC_F_TRIMSIR_RTC_LOCK                         ((uint32_t)(0x1UL << MXC_F_TRIMSIR_RTC_LOCK_POS)) 
#define MXC_F_TRIMSIR_SIMO_CLKDIV_POS                  0 
#define MXC_F_TRIMSIR_SIMO_CLKDIV                      ((uint32_t)(0x7UL << MXC_F_TRIMSIR_SIMO_CLKDIV_POS)) 
#define MXC_V_TRIMSIR_SIMO_CLKDIV_DIV1                 ((uint32_t)0x0UL) 
#define MXC_S_TRIMSIR_SIMO_CLKDIV_DIV1                 (MXC_V_TRIMSIR_SIMO_CLKDIV_DIV1 << MXC_F_TRIMSIR_SIMO_CLKDIV_POS) 
#define MXC_V_TRIMSIR_SIMO_CLKDIV_DIV16                ((uint32_t)0x1UL) 
#define MXC_S_TRIMSIR_SIMO_CLKDIV_DIV16                (MXC_V_TRIMSIR_SIMO_CLKDIV_DIV16 << MXC_F_TRIMSIR_SIMO_CLKDIV_POS) 
#define MXC_V_TRIMSIR_SIMO_CLKDIV_DIV32                ((uint32_t)0x3UL) 
#define MXC_S_TRIMSIR_SIMO_CLKDIV_DIV32                (MXC_V_TRIMSIR_SIMO_CLKDIV_DIV32 << MXC_F_TRIMSIR_SIMO_CLKDIV_POS) 
#define MXC_V_TRIMSIR_SIMO_CLKDIV_DIV64                ((uint32_t)0x5UL) 
#define MXC_S_TRIMSIR_SIMO_CLKDIV_DIV64                (MXC_V_TRIMSIR_SIMO_CLKDIV_DIV64 << MXC_F_TRIMSIR_SIMO_CLKDIV_POS) 
#define MXC_V_TRIMSIR_SIMO_CLKDIV_DIV128               ((uint32_t)0x7UL) 
#define MXC_S_TRIMSIR_SIMO_CLKDIV_DIV128               (MXC_V_TRIMSIR_SIMO_CLKDIV_DIV128 << MXC_F_TRIMSIR_SIMO_CLKDIV_POS) 
#define MXC_F_TRIMSIR_IPOLO_IPO_LIMITLO_POS            0 
#define MXC_F_TRIMSIR_IPOLO_IPO_LIMITLO                ((uint32_t)(0xFFUL << MXC_F_TRIMSIR_IPOLO_IPO_LIMITLO_POS)) 
#define MXC_F_TRIMSIR_CTRL_VDDA_LIMITLO_POS            0 
#define MXC_F_TRIMSIR_CTRL_VDDA_LIMITLO                ((uint32_t)(0x7FUL << MXC_F_TRIMSIR_CTRL_VDDA_LIMITLO_POS)) 
#define MXC_F_TRIMSIR_CTRL_VDDA_LIMITHI_POS            8 
#define MXC_F_TRIMSIR_CTRL_VDDA_LIMITHI                ((uint32_t)(0x7FUL << MXC_F_TRIMSIR_CTRL_VDDA_LIMITHI_POS)) 
#define MXC_F_TRIMSIR_CTRL_IPO_LIMITHI_POS             15 
#define MXC_F_TRIMSIR_CTRL_IPO_LIMITHI                 ((uint32_t)(0x1FFUL << MXC_F_TRIMSIR_CTRL_IPO_LIMITHI_POS)) 
#define MXC_F_TRIMSIR_CTRL_INRO_SEL_POS                24 
#define MXC_F_TRIMSIR_CTRL_INRO_SEL                    ((uint32_t)(0x3UL << MXC_F_TRIMSIR_CTRL_INRO_SEL_POS)) 
#define MXC_V_TRIMSIR_CTRL_INRO_SEL_8KHZ               ((uint32_t)0x0UL) 
#define MXC_S_TRIMSIR_CTRL_INRO_SEL_8KHZ               (MXC_V_TRIMSIR_CTRL_INRO_SEL_8KHZ << MXC_F_TRIMSIR_CTRL_INRO_SEL_POS) 
#define MXC_V_TRIMSIR_CTRL_INRO_SEL_16KHZ              ((uint32_t)0x1UL) 
#define MXC_S_TRIMSIR_CTRL_INRO_SEL_16KHZ              (MXC_V_TRIMSIR_CTRL_INRO_SEL_16KHZ << MXC_F_TRIMSIR_CTRL_INRO_SEL_POS) 
#define MXC_V_TRIMSIR_CTRL_INRO_SEL_30KHZ              ((uint32_t)0x2UL) 
#define MXC_S_TRIMSIR_CTRL_INRO_SEL_30KHZ              (MXC_V_TRIMSIR_CTRL_INRO_SEL_30KHZ << MXC_F_TRIMSIR_CTRL_INRO_SEL_POS) 
#define MXC_F_TRIMSIR_CTRL_INRO_TRIM_POS               29 
#define MXC_F_TRIMSIR_CTRL_INRO_TRIM                   ((uint32_t)(0x7UL << MXC_F_TRIMSIR_CTRL_INRO_TRIM_POS)) 
#define MXC_F_TRIMSIR_INRO_TRIM16K_POS                 0 
#define MXC_F_TRIMSIR_INRO_TRIM16K                     ((uint32_t)(0x7UL << MXC_F_TRIMSIR_INRO_TRIM16K_POS)) 
#define MXC_F_TRIMSIR_INRO_TRIM30K_POS                 3 
#define MXC_F_TRIMSIR_INRO_TRIM30K                     ((uint32_t)(0x7UL << MXC_F_TRIMSIR_INRO_TRIM30K_POS)) 
#define MXC_F_TRIMSIR_INRO_LPCLKSEL_POS                6 
#define MXC_F_TRIMSIR_INRO_LPCLKSEL                    ((uint32_t)(0x3UL << MXC_F_TRIMSIR_INRO_LPCLKSEL_POS)) 
#define MXC_V_TRIMSIR_INRO_LPCLKSEL_8KHZ               ((uint32_t)0x0UL) 
#define MXC_S_TRIMSIR_INRO_LPCLKSEL_8KHZ               (MXC_V_TRIMSIR_INRO_LPCLKSEL_8KHZ << MXC_F_TRIMSIR_INRO_LPCLKSEL_POS) 
#define MXC_V_TRIMSIR_INRO_LPCLKSEL_16KHZ              ((uint32_t)0x1UL) 
#define MXC_S_TRIMSIR_INRO_LPCLKSEL_16KHZ              (MXC_V_TRIMSIR_INRO_LPCLKSEL_16KHZ << MXC_F_TRIMSIR_INRO_LPCLKSEL_POS) 
#define MXC_V_TRIMSIR_INRO_LPCLKSEL_30KHZ              ((uint32_t)0x2UL) 
#define MXC_S_TRIMSIR_INRO_LPCLKSEL_30KHZ              (MXC_V_TRIMSIR_INRO_LPCLKSEL_30KHZ << MXC_F_TRIMSIR_INRO_LPCLKSEL_POS) 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_TRIMSIR_REGS_H_