35#ifndef __PARAMETERS_H__
36#define __PARAMETERS_H__
39#include <xparameters.h>
48#define AD463x_DMA_BASEADDR XPAR_AXI_AD463X_DMA_BASEADDR
49#define AD463x_SPI_ENGINE_BASEADDR XPAR_SPI_AD463X_SPI_AD463X_AXI_REGMAP_BASEADDR
50#define RX_CLKGEN_BASEADDR XPAR_SPI_CLKGEN_BASEADDR
51#define AXI_PWMGEN_BASEADDR XPAR_CNV_GENERATOR_BASEADDR
53#define AD463x_SPI_CS 0
56#define GPIO_RESETN_1 GPIO_OFFSET + 32
57#define GPIO_PGIA_0 GPIO_OFFSET + 33
58#define GPIO_PGIA_1 GPIO_OFFSET + 34
59#define GPIO_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
61#define UART_BAUDRATE 115200
62#define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID
63#define UART_IRQ_ID XPAR_XUARTPS_1_INTR
65#ifdef _XPARAMETERS_PS_H_
66#define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID
68#ifdef XPS_BOARD_ZCU102
69#define UART_IRQ_ID XPAR_XUARTPS_0_INTR
71#define UART_IRQ_ID XPAR_XUARTPS_1_INTR
75#define UART_DEVICE_ID XPAR_AXI_UART_DEVICE_ID
76#define UART_IRQ_ID XPAR_AXI_INTC_AXI_UART_INTERRUPT_INTR
80#define UART_BAUDRATE 115200
81#define UART_EXTRA &uart_extra_ip
82#define UART_OPS &xil_uart_ops
84#define DCACHE_INVALIDATE Xil_DCacheInvalidateRange
86#define DMA_BASEADDR XPAR_AXI_AD463X_DMA_BASEADDR
87#define SPI_ENGINE_BASEADDR XPAR_SPI_AD463X_SPI_AD463X_AXI_REGMAP_BASEADDR
88#define RX_CLKGEN_BASEADDR XPAR_SPI_CLKGEN_BASEADDR
89#define AXI_PWMGEN_BASEADDR XPAR_CNV_GENERATOR_BASEADDR
91#define SAMPLES_PER_CHANNEL_PLATFORM 100000
92#define MAX_SIZE_BASE_ADDR (SAMPLES_PER_CHANNEL_PLATFORM * 2 * sizeof(uint32_t))
94#define SPI_ENG_REF_CLK_FREQ_HZ XPAR_PS7_SPI_0_SPI_CLK_FREQ_HZ
96#define REFCLK_RATE 160000000
98#define SPI_DEVICE_ID 0
99#define SPI_OPS &spi_eng_platform_ops
100#define SPI_EXTRA &spi_eng_init_param
102#define SPI_BAUDRATE 80000000
104#define NO_OS_PWM_ID 0
105#define PWM_OPS &axi_pwm_ops
106#define PWM_EXTRA &ad4630_axi_pwm_init
107#define TRIGGER_PERIOD_NS 500
108#define TRIGGER_DUTY_NS 10
110#define AD400X_ADC_REF_VOLTAGE 5000
112#define GPIO_OPS &xil_gpio_ops
113#define GPIO_EXTRA &gpio_extra_param
114#define GPIO_OFFSET 54
115#define GPIO_RESETN_1 GPIO_OFFSET + 32
116#define GPIO_RESETN_PORT 0
118#define GPIO_PGIA_0 GPIO_OFFSET + 33
119#define GPIO_PGIA_0_PORT 0
120#define GPIO_PGIA_1 GPIO_OFFSET + 34
121#define GPIO_PGIA_1_PORT 0
123#define GPIO_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
Structure holding the initialization parameters for axi PWM.
Definition axi_pwm_extra.h:44
Structure containing the init parameters needed by the SPI engine.
Definition spi_engine.h:71
Structure holding the initialization parameters for Xilinx platform specific GPIO parameters.
Definition xilinx_gpio.h:56
Structure holding the initialization parameters for Xilinx platform specific UART parameters.
Definition xilinx_uart.h:56