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40 #ifndef __PARAMETERS_H__
41 #define __PARAMETERS_H__
46 #include <xparameters.h>
47 #include <xil_cache.h>
56 #define DCACHE_INVALIDATE Xil_DCacheInvalidateRange
58 #define DMA_BASEADDR XPAR_AXI_AD469X_DMA_BASEADDR
59 #define SPI_ENGINE_BASEADDR XPAR_SPI_AD469X_SPI_AD469X_AXI_REGMAP_BASEADDR
60 #define RX_CLKGEN_BASEADDR XPAR_SPI_CLKGEN_BASEADDR
61 #define AXI_PWMGEN_BASEADDR XPAR_AD469X_TRIGGER_GEN_BASEADDR
62 #define SPI_ENG_REF_CLK_FREQ_HZ XPAR_PS7_SPI_0_SPI_CLK_FREQ_HZ
64 #define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
66 #define NUM_SAMPLES 2000
67 #define BYTES_PER_SAMPLE 4
68 #define MAX_CHANNELS 17
69 #define ADC_DDR_BASEADDR XPAR_DDR_MEM_BASEADDR + 0x800000
70 #define MAX_SIZE_BASE_ADDR (NUM_SAMPLES * BYTES_PER_SAMPLE * MAX_CHANNELS)
73 #define UART_EXTRA &uart_extra_ip
74 #define UART_OPS &xil_uart_ops
75 #define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID
76 #define UART_IRQ_ID XPAR_XUARTPS_1_INTR
77 #define UART_BAUDRATE 115200
80 #define PWM_OPS &axi_pwm_ops
81 #define PWM_EXTRA &pwm_extra_ip
82 #define PWM_PERIOD 1000
86 #define GPIO_OPS &xil_gpio_ops
87 #define GPIO_EXTRA &gpio_extra_ip
88 #define GPIO_OFFSET 54
89 #define GPIO_RESETN_1 GPIO_OFFSET + 32
90 #define GPIO_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
93 #define SPI_DEVICE_ID 0
94 #define SPI_OPS &spi_eng_platform_ops
95 #define SPI_EXTRA &spi_eng_extra_ip
97 #define SPI_BAUDRATE 80000000
Structure holding the initialization parameters for Xilinx platform specific UART parameters.
Definition: xilinx_uart.h:73
Structure holding the initialization parameters for axi PWM.
Definition: axi_pwm_extra.h:56
Structure containing the init parameters needed by the SPI engine.
Definition: spi_engine.h:89
Structure holding the initialization parameters for Xilinx platform specific GPIO parameters.
Definition: xilinx_gpio.h:70