no-OS/doxygen/ad6673_8h_source.html

/***************************************************************************/

#ifndef __AD6673_H__

#define __AD6673_H__


/******************************************************************************/

/***************************** Include Files **********************************/

/******************************************************************************/

#include <stdint.h>

#include "no_os_spi.h"

#include "no_os_error.h"


/******************************************************************************/

/*********************************** AD6673 ***********************************/

/******************************************************************************/


/* Registers */


#define AD6673_READ                         (1 << 15)

#define AD6673_WRITE                        (0 << 15)

#define AD6673_CNT(x)                       ((((x) & 0x3) - 1) << 13)

#define AD6673_ADDR(x)                      ((x) & 0xFF)


#define AD6673_R1B                          (1 << 8)

#define AD6673_R2B                          (2 << 8)

#define AD6673_R3B                          (3 << 8)

#define AD6673_TRANSF_LEN(x)                (((x) >> 8) & 0xFF)

#define SHADOW(x)                           ((x) << 16)


/* Chip configuration registers */

#define AD6673_REG_SPI_CFG                  (AD6673_R1B | 0x00)

#define AD6673_REG_CHIP_ID                  (AD6673_R1B | 0x01)

#define AD6673_REG_CHIP_INFO                (AD6673_R1B | 0x02)


/* Channel index and transfer registers */

#define AD6673_REG_CH_INDEX                 (AD6673_R1B | 0x05)

#define AD6673_REG_DEVICE_UPDATE            (AD6673_R1B | 0xFF)


/* Program register map */

#define AD6673_REG_PDWN                     (AD6673_R1B | 0x08)

#define AD6673_REG_CLOCK                    (AD6673_R1B | 0x09 | SHADOW(1))

#define AD6673_REG_PLL_STAT                 (AD6673_R1B | 0x0A)

#define AD6673_REG_CLOCK_DIV                (AD6673_R1B | 0x0B | SHADOW(2))

#define AD6673_REG_TEST                     (AD6673_R1B | 0x0D | SHADOW(3))

#define AD6673_REG_BIST                     (AD6673_R1B | 0x0E | SHADOW(4))

#define AD6673_REG_OFFSET                   (AD6673_R1B | 0x10 | SHADOW(5))

#define AD6673_REG_OUT_MODE                 (AD6673_R1B | 0x14 | SHADOW(6))

#define AD6673_REG_CML                      (AD6673_R1B | 0x15)

#define AD6673_REG_VREF                     (AD6673_R1B | 0x18 | SHADOW(7))

#define AD6673_REG_USER_TEST1               (AD6673_R2B | 0x1A)

#define AD6673_REG_USER_TEST2               (AD6673_R2B | 0x1C)

#define AD6673_REG_USER_TEST3               (AD6673_R2B | 0x1E)

#define AD6673_REG_USER_TEST4               (AD6673_R2B | 0x20)

#define AD6673_REG_PLL_ENCODE               (AD6673_R1B | 0x21)

#define AD6673_REG_BIST_MISR                (AD6673_R2B | 0x25)

#define AD6673_REG_SYS_CTRL                 (AD6673_R1B | 0x3A | SHADOW(8))

#define AD6673_REG_NSR_CTRL                 (AD6673_R1B | 0x3C | SHADOW(9))

#define AD6673_REG_NSR_TUNING               (AD6673_R1B | 0x3E | SHADOW(10))

#define AD6673_REG_DCC_CTRL                 (AD6673_R1B | 0x40 | SHADOW(11))

#define AD6673_REG_DCC_VAL                  (AD6673_R2B | 0x42 | SHADOW(12))

#define AD6673_REG_FAST_DETECT              (AD6673_R1B | 0x45 | SHADOW(13))

#define AD6673_REG_FD_UPPER_THD             (AD6673_R2B | 0x48 | SHADOW(14))

#define AD6673_REG_FD_LOWER_THD             (AD6673_R2B | 0x4A | SHADOW(15))

#define AD6673_REG_FD_DWELL_TIME            (AD6673_R2B | 0x4C | SHADOW(16))

#define AD6673_REG_204B_QUICK_CFG           (AD6673_R1B | 0x5E)

#define AD6673_REG_204B_CTRL1               (AD6673_R1B | 0x5F)

#define AD6673_REG_204B_CTRL2               (AD6673_R1B | 0x60)

#define AD6673_REG_204B_CTRL3               (AD6673_R1B | 0x61)

#define AD6673_REG_204B_DID_CFG             (AD6673_R1B | 0x64)

#define AD6673_REG_204B_BID_CFG             (AD6673_R1B | 0x65)

#define AD6673_REG_204B_LID_CFG1            (AD6673_R1B | 0x67)

#define AD6673_REG_204B_LID_CFG2            (AD6673_R1B | 0x68)

#define AD6673_REG_204B_PARAM_SCR_L         (AD6673_R1B | 0x6E)

#define AD6673_REG_204B_PARAM_F             (AD6673_R1B | 0x6F)

#define AD6673_REG_204B_PARAM_K             (AD6673_R1B | 0x70)

#define AD6673_REG_204B_PARAM_M             (AD6673_R1B | 0x71)

#define AD6673_REG_204B_PARAM_CS_N          (AD6673_R1B | 0x72)

#define AD6673_REG_204B_PARAM_NP            (AD6673_R1B | 0x73)

#define AD6673_REG_204B_PARAM_S             (AD6673_R1B | 0x74)

#define AD6673_REG_204B_PARAM_HD_CF         (AD6673_R1B | 0x75)

#define AD6673_REG_204B_RESV1               (AD6673_R1B | 0x76)

#define AD6673_REG_204B_RESV2               (AD6673_R1B | 0x77)

#define AD6673_REG_204B_CHKSUM0             (AD6673_R1B | 0x79)

#define AD6673_REG_204B_CHKSUM1             (AD6673_R1B | 0x7A)

#define AD6673_REG_204B_LANE_ASSGN1         (AD6673_R1B | 0x82)

#define AD6673_REG_204B_LANE_ASSGN2         (AD6673_R1B | 0x83)

#define AD6673_REG_204B_LMFC_OFFSET         (AD6673_R1B | 0x8B)

#define AD6673_REG_204B_PRE_EMPHASIS        (AD6673_R1B | 0xA8)


/* AD6673_REG_SPI_CFG */

#define AD6673_SPI_CFG_LSB_FIRST            ((1 << 6) | (1 << 1))

#define AD6673_SPI_CFG_SOFT_RST             ((1 << 5) | (1 << 2))


/* AD6673_REG_CH_INDEX */

#define AD6673_CH_INDEX_ADC_A               (1 << 0)

#define AD6673_CH_INDEX_ADC_B               (1 << 1)


/* AD6673_REG_DEVICE_UPDATE */

#define AD6673_DEVICE_UPDATE_SW             (1 << 0)


/* AD6673_REG_PDWN */

#define AD6673_PDWN_EXTERN                  (1 << 5)

#define AD6673_PDWN_JTX                     (1 << 4)

#define AD6673_PDWN_JESD204B(x)             (((x) & 0x3) << 2)

#define AD6673_PDWN_CHIP(x)                 (((x) & 0x3) << 0)


/* AD6673_REG_CLOCK */

#define AD6673_CLOCK_SELECTION(x)           (((x) & 0x3) << 4)

#define AD6673_CLOCK_DUTY_CYCLE             (1 << 0)


/* AD6673_REG_PLL_STAT */

#define AD6673_PLL_STAT_LOCKED              (1 << 7)

#define AD6673_PLL_STAT_204B_LINK_RDY       (1 << 0)


/* AD6673_REG_CLOCK_DIV */

#define AD6673_CLOCK_DIV_PHASE(x)           (((x) & 0x7) << 3)

#define AD6673_CLOCK_DIV_RATIO(x)           (((x) & 0x7) << 0)


/* AD6673_REG_TEST */

#define AD6673_TEST_USER_TEST_MODE(x)       (((x) & 0x3) << 6)

#define AD6673_TEST_RST_PN_LONG             (1 << 5)

#define AD6673_TEST_RST_PN_SHOR             (1 << 4)

#define AD6673_TEST_OUTPUT_TEST(x)          (((x) & 0xF) << 0)


/* AD6673_REG_BIST */

#define AD6673_BIST_RESET                   (1 << 2)

#define AD6673_BIST_ENABLE                  (1 << 0)


/* AD6673_REG_OFFSET */

#define AD6673_REG_OFFSET_ADJUST(x)             (((x) & 0x3F) << 0)


/* AD6673_REG_OUT_MODE */

#define AD6673_OUT_MODE_JTX_BIT_ASSIGN(x)       (((x) & 0x7) << 5)

#define AD6673_OUT_MODE_DISABLE                 (1 << 4)

#define AD6673_OUT_MODE_INVERT_DATA             (1 << 3)

#define AD6673_OUT_MODE_DATA_FORMAT(x)          (((x) & 0x1) << 0)


/* AD6673_REG_CML */

#define AD6673_CML_DIFF_OUT_LEVEL(x)            (((x) & 0x7) << 0)


/* AD6673_REG_VREF */

#define AD6673_VREF_FS_ADJUST(x)                (((x) & 0x1F) << 0)


/* AD6673_REG_PLL_ENCODE */

#define AD6673_PLL_ENCODE(x)                    (((x) & 0x3) << 3)


/* AD6673_REG_SYS_CTRL */

#define AD6673_SYS_CTRL_REALIGN_ON_SYNCINB      (1 << 4)

#define AD6673_SYS_CTRL_REALIGN_ON_SYSREF       (1 << 3)

#define AD6673_SYS_CTRL_SYSREF_MODE             (1 << 2)

#define AD6673_SYS_CTRL_SYSREF_EN               (1 << 1)

#define AD6673_SYS_CTRL_SYNCINB_EN              (1 << 0)


/* AD6673_REG_NSR_CTRL */

#define AD6673_NSR_CTRL_BW_MODE                 (1 << 1)

#define AD6673_NSR_CTRL_ENABLE                  (1 << 0)


/* AD6673_REG_NSR_TUNING */

#define AD6673_NSR_TUNING(x)                    (((x) & 0x3F) << 0)


/* AD6673_REG_DCC_CTRL */

#define AD6673_DCC_CTRL_FREEZE_DCC              (1 << 6)

#define AD6673_DCC_CTRL_DCC_BW(x)               (((x) & 0xF) << 2)

#define AD6673_DCC_CTRL_DCC_EN                  (1 << 1)


/* AD6673_REG_FAST_DETECT */

#define AD6673_FAST_DETECT_PIN_FCT              (1 << 4)

#define AD6673_FAST_DETECT_FORCE_FDA_FDB_PIN    (1 << 3)

#define AD6673_FAST_DETECT_FORCE_FDA_FDB_VAL    (1 << 2)

#define AD6673_FAST_DETECT_OUTPUT_ENABLE        (1 << 0)


/* AD6673_REG_204B_QUICK_CFG */

#define AD6673_204B_QUICK_CFG(x)                (((x) & 0xFF) << 0)


/* AD6673_REG_204B_CTRL1 */

#define AD6673_204B_CTRL1_TAIL_BITS             (1 << 6)

#define AD6673_204B_CTRL1_TEST_SAMPLE_EN        (1 << 5)

#define AD6673_204B_CTRL1_ILAS_MODE(x)          (((x) & 0x3) << 2)

#define AD6673_204B_CTRL1_POWER_DOWN            (1 << 0)


/* AD6673_REG_204B_CTRL2 */

#define AD6673_204B_CTRL2_INVERT_JESD_BITS      (1 << 1)


/* AD6673_REG_204B_CTRL3 */

#define AD6673_204B_CTRL3_TEST_DATA_INJ_PT(x)   (((x) & 0x3) << 4)

#define AD6673_204B_CTRL3_JESD_TEST_MODE(x)     (((x) & 0xF) << 0)


/* AD6673_REG_204B_PARAM_SCR_L */

#define AD6673_204B_PARAM_SCR_L_SCRAMBLING      (1 << 7)

#define AD6673_204B_PARAM_SCR_L_LANES           (1 << 0)


/* AD6673_REG_204B_PARAM_CS_N */

#define AD6673_204B_PARAM_CS_N_NR_CTRL_BITS(x)      (((x) & 0x3) << 6)

#define AD6673_204B_PARAM_CS_N_ADC_RESOLUTION(x)    (((x) & 0xF) << 0)


/* AD6673_REG_204B_PARAM_NP */

#define AD6673_204B_PARAM_NP_JESD_SUBCLASS(x)       (((x) & 0x3) << 5)

#define AD6673_204B_PARAM_NP_JESD_N_VAL(x)          (((x) & 0xF) << 0)


/* AD6673_REG_204B_PARAM_S */

#define AD6673_204B_PARAM_S(x)                  (((x) << 0x1F) << 0)


/* AD6673_REG_204B_PARAM_HD_CF */

#define AD6673_204B_PARAM_HD_CF_HD_VAL          (1 << 7)

#define AD6673_204B_PARAM_HD_CF_CF_VAL(x)       (((x) & 0x1F) << 0)


/* AD6673_REG_204B_LANE_ASSGN1 */

#define AD6673_204B_LANE_ASSGN1(x)              (((x) & 0x3) << 4)


/* AD6673_REG_204B_LANE_ASSGN2 */

#define AD6673_204B_LANE_ASSGN2(x)              (((x) &0x3) << 0)


/* AD6673_REG_204B_LMFC_OFFSET */

#define AD6673_204B_LMFC_OFFSET(x)              (((x) & 0x1F) << 0)


/*****************************************************************************/

/************************** Types Declarations *******************************/

/*****************************************************************************/


struct ad6673_platform_data {

    int8_t extrn_pdwnmode;

    int8_t en_clk_dcs;

    int8_t clk_selection;

    int8_t clk_div_ratio;

    int8_t clk_div_phase;

    int8_t adc_vref;

    int8_t pll_low_encode;

    int8_t  name[16];

};


struct ad6673_jesd204b_cfg {

    int8_t jtx_in_standby;

    int8_t cml_level;

    int8_t quick_cfg_option;

    int8_t subclass;

    int8_t ctrl_bits_no;

    int8_t ctrl_bits_assign;

    int8_t tail_bits_mode;

    int8_t did;

    int8_t bid;

    int8_t lid0;

    int8_t lid1;

    int8_t k;

    int8_t scrambling;

    int8_t ilas_mode;

    int8_t en_ilas_test;

    int8_t invert_logic_bits;

    int8_t en_sys_ref;

    int8_t en_sync_in_b;

    int8_t sys_ref_mode;

    int8_t align_sync_in_b;

    int8_t align_sys_ref;

    int8_t lane0_assign;

    /* Option to remap converter and lane assignments.

     * 0 = assign Logical Lane 1 to Physical Lane A

     * 1 = assign Logical Lane 1 to Physical Lane B [default]

     */

    int8_t lane1_assign;

};


struct ad6673_fast_detect_cfg {

    int8_t  en_fd;

    int8_t  pin_function;

    int8_t  force_pins;

    int8_t  pin_force_value;

    int16_t fd_upper_tresh;

    int16_t fd_lower_tresh;

    int16_t df_dwell_time;

};


struct ad6673_type_band {

    int32_t f0;

    int32_t f_center;

    int32_t f1;

};


struct ad6673_state {

    struct ad6673_platform_data   *pdata;

    struct ad6673_jesd204b_cfg    *p_jesd204b;

    struct ad6673_fast_detect_cfg *p_fd;

};


enum shadow_registers {

    AD6673_SHD_REG_CLOCK = 1,

    AD6673_SHD_REG_CLOCK_DIV,

    AD6673_SHD_REG_TEST,

    AD6673_SHD_REG_BIST,

    AD6673_SHD_REG_OFFSET,

    AD6673_SHD_REG_OUT_MODE,

    AD6673_SHD_REG_VREF,

    AD6673_SHD_REG_SYS_CTRL,

    AD6673_REG_SHD_NSR_CTRL,

    AD6673_REG_SHD_NSR_TUNING,

    AD6673_SHD_REG_DCC_CTRL,

    AD6673_SHD_REG_DCC_VAL,

    AD6673_SHD_REG_FAST_DETECT,

    AD6673_SHD_REG_FD_UPPER_THD,

    AD6673_SHD_REG_FD_LOWER_THD,

    AD6673_SHD_REG_FD_DWELL_TIME,

    SHADOW_REGISTER_COUNT

};


struct ad6673_dev {

    /* SPI */

    struct no_os_spi_desc       *spi_desc;

    /* Device Settings */

    struct ad6673_state ad6673_st;

    int32_t shadow_regs[SHADOW_REGISTER_COUNT];

};


struct ad6673_init_param {

    /* SPI */

    struct no_os_spi_init_param spi_init;

};


/******************************************************************************/

/************************ Functions Declarations ******************************/

/******************************************************************************/


int32_t ad6673_setup(struct ad6673_dev **device,

             struct ad6673_init_param init_param);

int32_t ad6673_remove(struct ad6673_dev *dev);

int32_t ad6673_read(struct ad6673_dev *dev,

            int32_t register_address);

int32_t ad6673_write(struct ad6673_dev *dev,

             int32_t register_address,

             int32_t register_value);

int32_t ad6673_transfer(struct ad6673_dev *dev);

int32_t ad6673_soft_reset(struct ad6673_dev *dev);

int32_t ad6673_chip_pwr_mode(struct ad6673_dev *dev,

                 int32_t mode);

int32_t ad6673_select_channel_for_config(struct ad6673_dev *dev,

        int32_t channel);

int32_t ad6673_test_mode(struct ad6673_dev *dev,

             int32_t mode);

int32_t ad6673_offset_adj(struct ad6673_dev *dev,

              int32_t adj);

int32_t ad6673_output_disable(struct ad6673_dev *dev,

                  int32_t en);

int32_t ad6673_output_invert(struct ad6673_dev *dev,

                 int32_t invert);

int32_t ad6673_output_format(struct ad6673_dev *dev,

                 int32_t format);

int32_t ad6673_reset_pn9(struct ad6673_dev *dev,

             int32_t rst);

int32_t ad6673_reset_pn23(struct ad6673_dev *dev,

              int32_t rst);

int32_t ad6673_set_user_pattern(struct ad6673_dev *dev,

                int32_t pattern_no,

                int32_t user_pattern);

int32_t ad6673_bist_enable(struct ad6673_dev *dev,

               int32_t enable);

int32_t ad6673_bist_reset(struct ad6673_dev *dev,

              int32_t reset);

int32_t ad6673_jesd204b_setup(struct ad6673_dev *dev);

int32_t ad6673_jesd204b_pwr_mode(struct ad6673_dev *dev,

                 int32_t mode);

int32_t ad6673_jesd204b_select_test_injection_point(struct ad6673_dev *dev,

        int32_t inj_point);

int32_t ad6673_jesd204b_test_mode(struct ad6673_dev *dev,

                  int32_t test_mode);

int32_t ad6673_jesd204b_invert_logic(struct ad6673_dev *dev,

                     int32_t invert);

int32_t ad6673_fast_detect_setup(struct ad6673_dev *dev);

int32_t ad6673_dcc_enable(struct ad6673_dev *dev,

              int32_t enable);

int32_t ad6673_dcc_bandwidth(struct ad6673_dev *dev,

                 int32_t bw);

int32_t ad6673_dcc_freeze(struct ad6673_dev *dev,

              int32_t freeze);

int32_t ad6673_nsr_enable(struct ad6673_dev *dev,

              int32_t enable);

int32_t ad6673_nsr_bandwidth_mode(struct ad6673_dev *dev,

                  int32_t mode);

int32_t ad6673_nsr_tuning_freq(int64_t tune_freq,

                   int64_t f_adc,

                   struct ad6673_type_band *p_band);


#endif /* __AD6673_H__ */