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40 #ifndef SRC_AD77681_H_
41 #define SRC_AD77681_H_
48 #define AD77681_REG_CHIP_TYPE 0x3
49 #define AD77681_REG_PROD_ID_L 0x4
50 #define AD77681_REG_PROD_ID_H 0x5
51 #define AD77681_REG_CHIP_GRADE 0x6
52 #define AD77681_REG_SCRATCH_PAD 0x0A
53 #define AD77681_REG_VENDOR_L 0x0C
54 #define AD77681_REG_VENDOR_H 0x0D
55 #define AD77681_REG_INTERFACE_FORMAT 0x14
56 #define AD77681_REG_POWER_CLOCK 0x15
57 #define AD77681_REG_ANALOG 0x16
58 #define AD77681_REG_ANALOG2 0x17
59 #define AD77681_REG_CONVERSION 0x18
60 #define AD77681_REG_DIGITAL_FILTER 0x19
61 #define AD77681_REG_SINC3_DEC_RATE_MSB 0x1A
62 #define AD77681_REG_SINC3_DEC_RATE_LSB 0x1B
63 #define AD77681_REG_DUTY_CYCLE_RATIO 0x1C
64 #define AD77681_REG_SYNC_RESET 0x1D
65 #define AD77681_REG_GPIO_CONTROL 0x1E
66 #define AD77681_REG_GPIO_WRITE 0x1F
67 #define AD77681_REG_GPIO_READ 0x20
68 #define AD77681_REG_OFFSET_HI 0x21
69 #define AD77681_REG_OFFSET_MID 0x22
70 #define AD77681_REG_OFFSET_LO 0x23
71 #define AD77681_REG_GAIN_HI 0x24
72 #define AD77681_REG_GAIN_MID 0x25
73 #define AD77681_REG_GAIN_LO 0x26
74 #define AD77681_REG_SPI_DIAG_ENABLE 0x28
75 #define AD77681_REG_ADC_DIAG_ENABLE 0x29
76 #define AD77681_REG_DIG_DIAG_ENABLE 0x2A
77 #define AD77681_REG_ADC_DATA 0x2C
78 #define AD77681_REG_MASTER_STATUS 0x2D
79 #define AD77681_REG_SPI_DIAG_STATUS 0x2E
80 #define AD77681_REG_ADC_DIAG_STATUS 0x2F
81 #define AD77681_REG_DIG_DIAG_STATUS 0x30
82 #define AD77681_REG_MCLK_COUNTER 0x31
85 #define AD77681_INTERFACE_CRC_EN_MSK (0x1 << 6)
86 #define AD77681_INTERFACE_CRC_EN(x) (((x) & 0x1) << 6)
87 #define AD77681_INTERFACE_CRC_TYPE_MSK (0x1 << 5)
88 #define AD77681_INTERFACE_CRC_TYPE(x) (((x) & 0x1) << 5)
89 #define AD77681_INTERFACE_STATUS_EN_MSK (0x1 << 4)
90 #define AD77681_INTERFACE_STATUS_EN(x) (((x) & 0x1) << 4)
91 #define AD77681_INTERFACE_CONVLEN_MSK (0x1 << 3)
92 #define AD77681_INTERFACE_CONVLEN(x) (((x) & 0x1) << 3)
93 #define AD77681_INTERFACE_RDY_EN_MSK (0x1 << 2)
94 #define AD77681_INTERFACE_RDY_EN(x) (((x) & 0x1) << 3)
95 #define AD77681_INTERFACE_CONT_READ_MSK (0x1 << 0)
96 #define AD77681_INTERFACE_CONT_READ_EN(x) (((x) & 0x1) << 0)
97 #define AD77681_REG_COEFF_CONTROL 0x32
98 #define AD77681_REG_COEFF_DATA 0x33
99 #define AD77681_REG_ACCESS_KEY 0x34
102 #define AD77681_SCRATCHPAD_MSK (0xFF << 0)
103 #define AD77681_SCRATCHPAD(x) (((x) & 0xFF) << 0)
106 #define AD77681_POWER_CLK_PWRMODE_MSK 0x3
107 #define AD77681_POWER_CLK_PWRMODE(x) (((x) & 0x3) << 0)
108 #define AD77681_POWER_CLK_MOD_OUT_MSK (0x1 << 2)
109 #define AD77681_POWER_CLK_MOD_OUT(x) (((x) & 0x1) << 2)
110 #define AD77681_POWER_CLK_POWER_DOWN 0x08
111 #define AD77681_POWER_CLK_MCLK_DIV_MSK (0x3 << 4)
112 #define AD77681_POWER_CLK_MCLK_DIV(x) (((x) & 0x3) << 4)
113 #define AD77681_POWER_CLK_CLOCK_SEL_MSK (0x3 << 6)
114 #define AD77681_POWER_CLK_CLOCK_SEL(x) (((x) & 0x3) << 6)
117 #define AD77681_CONVERSION_DIAG_MUX_MSK (0xF << 4)
118 #define AD77681_CONVERSION_DIAG_MUX_SEL(x) (((x) & 0xF) << 4)
119 #define AD77681_CONVERSION_DIAG_SEL_MSK (0x1 << 3)
120 #define AD77681_CONVERSION_DIAG_SEL(x) (((x) & 0x1) << 3)
121 #define AD77681_CONVERSION_MODE_MSK (0x7 << 0)
122 #define AD77681_CONVERSION_MODE(x) (((x) & 0x7) << 0)
125 #define AD77681_ANALOG_REF_BUF_POS_MSK (0x3 << 6)
126 #define AD77681_ANALOG_REF_BUF_POS(x) (((x) & 0x3) << 6)
127 #define AD77681_ANALOG_REF_BUF_NEG_MSK (0x3 << 4)
128 #define AD77681_ANALOG_REF_BUF_NEG(x) (((x) & 0x3) << 4)
129 #define AD77681_ANALOG_AIN_BUF_POS_OFF_MSK (0x1 << 1)
130 #define AD77681_ANALOG_AIN_BUF_POS_OFF(x) (((x) & 0x1) << 1)
131 #define AD77681_ANALOG_AIN_BUF_NEG_OFF_MSK (0x1 << 0)
132 #define AD77681_ANALOG_AIN_BUF_NEG_OFF(x) (((x) & 0x1) << 0)
135 #define AD77681_ANALOG2_VCM_MSK (0x7 << 0)
136 #define AD77681_ANALOG2_VCM(x) (((x) & 0x7) << 0)
139 #define AD77681_DIGI_FILTER_60HZ_REJ_EN_MSK (0x1 << 7)
140 #define AD77681_DIGI_FILTER_60HZ_REJ_EN(x) (((x) & 0x1) << 7)
141 #define AD77681_DIGI_FILTER_FILTER_MSK (0x7 << 4)
142 #define AD77681_DIGI_FILTER_FILTER(x) (((x) & 0x7) << 4)
143 #define AD77681_DIGI_FILTER_DEC_RATE_MSK (0x7 << 0)
144 #define AD77681_DIGI_FILTER_DEC_RATE(x) (((x) & 0x7) << 0)
147 #define AD77681_SINC3_DEC_RATE_MSB_MSK (0x0F << 0)
148 #define AD77681_SINC3_DEC_RATE_MSB(x) (((x) & 0x0F) << 0)
151 #define AD77681_SINC3_DEC_RATE_LSB_MSK (0xFF << 0)
152 #define AD77681_SINC3_DEC_RATE_LSB(x) (((x) & 0xFF) << 0)
155 #define AD77681_DC_RATIO_IDLE_TIME_MSK (0xFF << 0)
156 #define AD77681_DC_RATIO_IDLE_TIME(x) (((x) & 0xFF) << 0)
159 #define AD77681_SYNC_RST_SPI_STARTB_MSK (0x1 << 7)
160 #define AD77681_SYNC_RST_SPI_STARTB(x) (((x) & 0x1) << 7)
161 #define AD77681_SYNC_RST_SYNCOUT_EDGE_MSK (0x1 << 6)
162 #define AD77681_SYNC_RST_SYNCOUT_EDGE(x) (((x) & 0x1) << 6)
163 #define AD77681_SYNC_RST_GPIO_START_EN_MSK (0x1 << 3)
164 #define AD77681_SYNC_RST_GPIO_START_EN(x) (((x) & 0x1) << 3)
165 #define AD77681_SYNC_RST_SPI_RESET_MSK (0x3 << 0)
166 #define AD77681_SYNC_RST_SPI_RESET(x) (((x) & 0x3) << 0)
169 #define AD77681_GPIO_CNTRL_UGPIO_EN_MSK (0x1 << 7)
170 #define AD77681_GPIO_CNTRL_UGPIO_EN(x) (((x) & 0x1) << 7)
171 #define AD77681_GPIO_CNTRL_GPIO2_OD_EN_MSK (0x1 << 6)
172 #define AD77681_GPIO_CNTRL_GPIO2_OD_EN(x) (((x) & 0x1) << 6)
173 #define AD77681_GPIO_CNTRL_GPIO1_OD_EN_MSK (0x1 << 5)
174 #define AD77681_GPIO_CNTRL_GPIO1_OD_EN(x) (((x) & 0x1) << 5)
175 #define AD77681_GPIO_CNTRL_GPIO0_OD_EN_MSK (0x1 << 4)
176 #define AD77681_GPIO_CNTRL_GPIO0_OD_EN(x) (((x) & 0x1) << 4)
177 #define AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN_MSK (0x7 << 4)
178 #define AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN(x) (((x) & 0x7) << 4)
179 #define AD77681_GPIO_CNTRL_GPIO3_OP_EN_MSK (0x1 << 3)
180 #define AD77681_GPIO_CNTRL_GPIO3_OP_EN(x) (((x) & 0x1) << 3)
181 #define AD77681_GPIO_CNTRL_GPIO2_OP_EN_MSK (0x1 << 2)
182 #define AD77681_GPIO_CNTRL_GPIO2_OP_EN(x) (((x) & 0x1) << 2)
183 #define AD77681_GPIO_CNTRL_GPIO1_OP_EN_MSK (0x1 << 1)
184 #define AD77681_GPIO_CNTRL_GPIO1_OP_EN(x) (((x) & 0x1) << 1)
185 #define AD77681_GPIO_CNTRL_GPIO0_OP_EN_MSK (0x1 << 0)
186 #define AD77681_GPIO_CNTRL_GPIO0_OP_EN(x) (((x) & 0x1) << 0)
187 #define AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN_MSK (0xF << 0)
188 #define AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN(x) (((x) & 0xF) << 0)
191 #define AD77681_GPIO_WRITE_3_MSK (0x1 << 3)
192 #define AD77681_GPIO_WRITE_3(x) (((x) & 0x1) << 3)
193 #define AD77681_GPIO_WRITE_2_MSK (0x1 << 2)
194 #define AD77681_GPIO_WRITE_2(x) (((x) & 0x1) << 2)
195 #define AD77681_GPIO_WRITE_1_MSK (0x1 << 1)
196 #define AD77681_GPIO_WRITE_1(x) (((x) & 0x1) << 1)
197 #define AD77681_GPIO_WRITE_0_MSK (0x1 << 0)
198 #define AD77681_GPIO_WRITE_0(x) (((x) & 0x1) << 0)
199 #define AD77681_GPIO_WRITE_ALL_MSK (0xF << 0)
200 #define AD77681_GPIO_WRITE_ALL(x) (((x) & 0xF))
203 #define AD77681_GPIO_READ_3_MSK (0x1 << 3)
204 #define AD77681_GPIO_READ_2_MSK (0x1 << 2)
205 #define AD77681_GPIO_READ_1_MSK (0x1 << 1)
206 #define AD77681_GPIO_READ_0_MSK (0x1 << 0)
207 #define AD77681_GPIO_READ_ALL_MSK (0xF << 0)
210 #define AD77681_OFFSET_HI_MSK (0xFF << 0)
211 #define AD77681_OFFSET_HI(x) (((x) & 0xFF) << 0)
214 #define AD77681_OFFSET_MID_MSK (0xFF << 0)
215 #define AD77681_OFFSET_MID(x) (((x) & 0xFF) << 0)
218 #define AD77681_OFFSET_LO_MSK (0xFF << 0)
219 #define AD77681_OFFSET_LO(x) (((x) & 0xFF) << 0)
222 #define AD77681_GAIN_HI_MSK (0xFF << 0)
223 #define AD77681_GAIN_HI(x) (((x) & 0xFF) << 0)
226 #define AD77681_GAIN_MID_MSK (0xFF << 0)
227 #define AD77681_GAIN_MID(x) (((x) & 0xFF) << 0)
230 #define AD77681_GAIN_LOW_MSK (0xFF << 0)
231 #define AD77681_GAIN_LOW(x) (((x) & 0xFF) << 0)
234 #define AD77681_SPI_DIAG_ERR_SPI_IGNORE_MSK (0x1 << 4)
235 #define AD77681_SPI_DIAG_ERR_SPI_IGNORE(x) (((x) & 0x1) << 4)
236 #define AD77681_SPI_DIAG_ERR_SPI_CLK_CNT_MSK (0x1 << 3)
237 #define AD77681_SPI_DIAG_ERR_SPI_CLK_CNT(x) (((x) & 0x1) << 3)
238 #define AD77681_SPI_DIAG_ERR_SPI_RD_MSK (0x1 << 2)
239 #define AD77681_SPI_DIAG_ERR_SPI_RD(x) (((x) & 0x1) << 2)
240 #define AD77681_SPI_DIAG_ERR_SPI_WR_MSK (0x1 << 1)
241 #define AD77681_SPI_DIAG_ERR_SPI_WR(x) (((x) & 0x1) << 1)
244 #define AD77681_ADC_DIAG_ERR_DLDO_PSM_MSK (0x1 << 5)
245 #define AD77681_ADC_DIAG_ERR_DLDO_PSM(x) (((x) & 0x1) << 5)
246 #define AD77681_ADC_DIAG_ERR_ALDO_PSM_MSK (0x1 << 4)
247 #define AD77681_ADC_DIAG_ERR_ALDO_PSM(x) (((x) & 0x1) << 4)
248 #define AD77681_ADC_DIAG_ERR_FILT_SAT_MSK (0x1 << 2)
249 #define AD77681_ADC_DIAG_ERR_FILT_SAT(x) (((x) & 0x1) << 2)
250 #define AD77681_ADC_DIAG_ERR_FILT_NOT_SET_MSK (0x1 << 1)
251 #define AD77681_ADC_DIAG_ERR_FILT_NOT_SET(x) (((x) & 0x1) << 1)
252 #define AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL_MSK (0x1 << 0)
253 #define AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL(x) (((x) & 0x1) << 0)
256 #define AD77681_DIG_DIAG_ERR_MEMMAP_CRC_MSK (0x1 << 4)
257 #define AD77681_DIG_DIAG_ERR_MEMMAP_CRC(x) (((x) & 0x1) << 4)
258 #define AD77681_DIG_DIAG_ERR_RAM_CRC_MSK (0x1 << 3)
259 #define AD77681_DIG_DIAG_ERR_RAM_CRC(x) (((x) & 0x1) << 3)
260 #define AD77681_DIG_DIAG_ERR_FUSE_CRC_MSK (0x1 << 2)
261 #define AD77681_DIG_DIAG_ERR_FUSE_CRC(x) (((x) & 0x1) << 2)
262 #define AD77681_DIG_DIAG_FREQ_COUNT_EN_MSK (0x1 << 0)
263 #define AD77681_DIG_DIAG_FREQ_COUNT_EN(x) (((x) & 0x1) << 0)
266 #define AD77681_MASTER_ERROR_MSK (0x1 << 7)
267 #define AD77681_MASTER_ADC_ERROR_MSK (0x1 << 6)
268 #define AD77681_MASTER_DIG_ERROR_MSK (0x1 << 5)
269 #define AD77681_MASTER_DIG_ERR_EXT_CLK_MSK (0x1 << 4)
270 #define AD77681_MASTER_FILT_SAT_MSK (0x1 << 3)
271 #define AD77681_MASTER_FILT_NOT_SET_MSK (0x1 << 2)
272 #define AD77681_MASTER_SPI_ERROR_MSK (0x1 << 1)
273 #define AD77681_MASTER_POR_FLAG_MSK (0x1 << 0)
276 #define AD77681_SPI_IGNORE_ERROR_MSK (0x1 << 4)
277 #define AD77681_SPI_IGNORE_ERROR_CLR(x) (((x) & 0x1) << 4)
278 #define AD77681_SPI_CLK_CNT_ERROR_MSK (0x1 << 3)
279 #define AD77681_SPI_READ_ERROR_MSK (0x1 << 2)
280 #define AD77681_SPI_READ_ERROR_CLR(x) (((x) & 0x1) << 2)
281 #define AD77681_SPI_WRITE_ERROR_MSK (0x1 << 1)
282 #define AD77681_SPI_WRITE_ERROR_CLR(x) (((x) & 0x1) << 1)
283 #define AD77681_SPI_CRC_ERROR_MSK (0x1 << 0)
284 #define AD77681_SPI_CRC_ERROR_CLR(x) (((x) & 0x1) << 0)
287 #define AD77681_ADC_DLDO_PSM_ERROR_MSK (0x1 << 5)
288 #define AD77681_ADC_ALDO_PSM_ERROR_MSK (0x1 << 4)
289 #define AD77681_ADC_REF_DET_ERROR_MSK (0x1 << 3)
290 #define AD77681_ADC_FILT_SAT_MSK (0x1 << 2)
291 #define AD77681_ADC_FILT_NOT_SET_MSK (0x1 << 1)
292 #define AD77681_ADC_DIG_ERR_EXT_CLK_MSK (0x1 << 0)
295 #define AD77681_DIG_MEMMAP_CRC_ERROR_MSK (0x1 << 4)
296 #define AD77681_DIG_RAM_CRC_ERROR_MSK (0x1 << 3)
297 #define AD77681_DIG_FUS_CRC_ERROR_MSK (0x1 << 2)
300 #define AD77681_MCLK_COUNTER_MSK (0xFF << 0)
301 #define AD77681_MCLK_COUNTER(x) (((x) & 0xFF) << 0)
304 #define AD77681_COEF_CONTROL_COEFFACCESSEN_MSK (0x1 << 7)
305 #define AD77681_COEF_CONTROL_COEFFACCESSEN(x) (((x) & 0x1) << 7)
306 #define AD77681_COEF_CONTROL_COEFFWRITEEN_MSK (0x1 << 6)
307 #define AD77681_COEF_CONTROL_COEFFWRITEEN(x) (((x) & 0x1) << 6)
308 #define AD77681_COEF_CONTROL_COEFFADDR_MSK (0x3F << 5)
309 #define AD77681_COEF_CONTROL_COEFFADDR(x) (((x) & 0x3F) << 5)
312 #define AD77681_COEFF_DATA_USERCOEFFEN_MSK (0x1 << 23)
313 #define AD77681_COEFF_DATA_USERCOEFFEN(x) (((x) & 0x1) << 23)
314 #define AD77681_COEFF_DATA_COEFFDATA_MSK (0x7FFFFF << 22)
315 #define AD77681_COEFF_DATA_COEFFDATA(x) (((x) & 0x7FFFFF) << 22)
318 #define AD77681_ACCESS_KEY_MSK (0xFF << 0)
319 #define AD77681_ACCESS_KEY(x) (((x) & 0xFF) << 0)
320 #define AD77681_ACCESS_KEY_CHECK_MSK (0x1 << 0)
322 #define AD77681_REG_READ(x) ( (1 << 6) | (x & 0xFF) ) // Read from register x
323 #define AD77681_REG_WRITE(x) ( (~(1 << 6)) & (x & 0xFF) ) // Write to register x
326 #define AD77681_CRC8_POLY 0x07 // x^8 + x^2 + x^1 + x^0
329 #define INITIAL_CRC_CRC8 0x03
330 #define INITIAL_CRC_XOR 0x6C
331 #define INITIAL_CRC 0x00
337 #define EXIT_CONT_READ 0x6C
339 #define AD7768_N_BITS 24
341 #define AD7768_FULL_SCALE (1 << AD7768_N_BITS)
343 #define AD7768_HALF_SCALE (1 << (AD7768_N_BITS - 1))
643 uint16_t *data_buffer);
677 uint16_t *sinc3_dec_reg,
#define AD77681_SCRATCHPAD_MSK
Definition: ad77681.h:102
@ AD77681_FIR
Definition: ad77681.h:401
int32_t ad77681_data_to_voltage(struct ad77681_dev *dev, uint32_t *raw_code, double *voltage)
Definition: ad77681.c:412
int32_t ad77681_clear_error_flags(struct ad77681_dev *dev)
Definition: ad77681.c:1587
#define AD77681_DIG_DIAG_ERR_MEMMAP_CRC_MSK
Definition: ad77681.h:256
Definition: ad77681.h:496
#define AD77681_GAIN_MID(x)
Definition: ad77681.h:227
Definition: ad77681.h:528
bool adc_filt_not_settled
Definition: ad77681.h:509
#define AD77681_GPIO_WRITE_ALL_MSK
Definition: ad77681.h:199
#define AD77681_ANALOG_REF_BUF_NEG_MSK
Definition: ad77681.h:127
@ AD77681_GLOBAL_GPIO_DISABLE
Definition: ad77681.h:466
#define AD7768_FULL_SCALE
Definition: ad77681.h:341
#define AD77681_REG_COEFF_DATA
Definition: ad77681.h:98
#define AD77681_GPIO_WRITE_2_MSK
Definition: ad77681.h:193
#define AD77681_DIG_DIAG_FREQ_COUNT_EN_MSK
Definition: ad77681.h:262
#define AD77681_REG_DIG_DIAG_STATUS
Definition: ad77681.h:81
int32_t ad77681_initiate_sync(struct ad77681_dev *dev)
Definition: ad77681.c:1063
int32_t ad77681_gpio_write(struct ad77681_dev *dev, uint8_t value, enum ad77681_gpios gpio_number)
Definition: ad77681.c:1377
int32_t ad77681_error_flags_enabe(struct ad77681_dev *dev)
Definition: ad77681.c:1620
int32_t ad77681_setup(struct ad77681_dev **device, struct ad77681_init_param init_param, struct ad77681_status_registers **status)
Definition: ad77681.c:1752
@ AD77681_SOFT_RESET
Definition: ad77681.h:422
#define AD77681_GPIO_CNTRL_GPIO2_OP_EN(x)
Definition: ad77681.h:182
#define AD77681_MASTER_FILT_NOT_SET_MSK
Definition: ad77681.h:271
bool fuse_crc_error
Definition: ad77681.h:525
int32_t ad77681_power_down(struct ad77681_dev *dev, enum ad77681_sleep_wake sleep_wake)
Definition: ad77681.c:872
#define AD77681_MASTER_ERROR_MSK
Definition: ad77681.h:266
int32_t ad77681_spi_reg_write(struct ad77681_dev *dev, uint8_t reg_addr, uint8_t reg_data)
Definition: ad77681.c:163
#define AD77681_MASTER_POR_FLAG_MSK
Definition: ad77681.h:273
#define AD77681_ACCESS_KEY_CHECK_MSK
Definition: ad77681.h:320
int32_t no_os_spi_write_and_read(struct no_os_spi_desc *desc, uint8_t *data, uint16_t bytes_number)
Write and read data to/from SPI.
Definition: no_os_spi.c:165
#define AD77681_CONVERSION_DIAG_SEL(x)
Definition: ad77681.h:120
int32_t ad77681_initiate_sync(struct ad77681_dev *dev)
Definition: ad77681.c:1063
#define AD77681_SYNC_RST_SPI_STARTB(x)
Definition: ad77681.h:160
bool spi_ignore
Definition: ad77681.h:512
#define AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN_MSK
Definition: ad77681.h:187
#define AD77681_OFFSET_MID_MSK
Definition: ad77681.h:214
Definition: ad77681.h:503
int32_t ad77681_setup(struct ad77681_dev **device, struct ad77681_init_param init_param, struct ad77681_status_registers **status)
Definition: ad77681.c:1752
int32_t ad77681_set_crc_sel(struct ad77681_dev *dev, enum ad77681_crc_sel crc_sel)
Definition: ad77681.c:978
int32_t ad77681_spi_read_adc_data(struct ad77681_dev *dev, uint8_t *adc_data, enum ad77681_data_read_mode mode)
Definition: ad77681.c:280
@ AD77681_BUFn_FULL_BUFFER_ON
Definition: ad77681.h:441
#define AD77681_GPIO_CNTRL_GPIO2_OP_EN_MSK
Definition: ad77681.h:181
Header file of SPI Interface.
#define AD77681_OFFSET_LO_MSK
Definition: ad77681.h:218
@ AD77681_TEMP_SENSOR
Definition: ad77681.h:383
#define AD77681_GAIN_LOW_MSK
Definition: ad77681.h:230
ad77681_filter_type
Definition: ad77681.h:396
@ AD77681_AINn_DISABLED
Definition: ad77681.h:428
int32_t ad77681_data_to_voltage(struct ad77681_dev *dev, uint32_t *raw_code, double *voltage)
Definition: ad77681.c:412
#define AD77681_DIG_DIAG_ERR_MEMMAP_CRC(x)
Definition: ad77681.h:257
#define AD77681_GPIO_READ_0_MSK
Definition: ad77681.h:206
#define AD77681_REG_ADC_DIAG_STATUS
Definition: ad77681.h:80
#define AD77681_GPIO_WRITE_1(x)
Definition: ad77681.h:196
int32_t ad77681_scratchpad(struct ad77681_dev *dev, uint8_t *sequence)
Definition: ad77681.c:1506
#define AD77681_REG_GAIN_LO
Definition: ad77681.h:73
@ AD77681_CONTINUOUS_READ_DISABLE
Definition: ad77681.h:486
#define AD77681_REG_GAIN_MID
Definition: ad77681.h:72
@ AD77681_SINC3
Definition: ad77681.h:400
#define AD77681_SPI_DIAG_ERR_SPI_IGNORE(x)
Definition: ad77681.h:235
@ AD77681_SINC5_FIR_DECx512
Definition: ad77681.h:410
#define AD77681_GPIO_CNTRL_GPIO0_OD_EN(x)
Definition: ad77681.h:176
#define AD77681_DIG_DIAG_FREQ_COUNT_EN(x)
Definition: ad77681.h:263
@ AD77681_BUFp_DISABLED
Definition: ad77681.h:447
#define AD77681_REG_GPIO_WRITE
Definition: ad77681.h:66
#define AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL(x)
Definition: ad77681.h:253
#define AD77681_SPI_DIAG_ERR_SPI_IGNORE_MSK
Definition: ad77681.h:234
int32_t ad77681_set_REFn_buffer(struct ad77681_dev *dev, enum ad77681_REFn_buffer REFn)
Definition: ad77681.c:692
#define AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL_MSK
Definition: ad77681.h:252
@ AD77681_FAST
Definition: ad77681.h:354
enum ad77681_crc_sel crc_sel
Definition: ad77681.h:538
#define AD77681_DIGI_FILTER_FILTER_MSK
Definition: ad77681.h:141
#define AD77681_GPIO_WRITE_3(x)
Definition: ad77681.h:192
int32_t ad77681_spi_reg_read(struct ad77681_dev *dev, uint8_t reg_addr, uint8_t *reg_data)
Definition: ad77681.c:113
int32_t ad77681_set_REFp_buffer(struct ad77681_dev *dev, enum ad77681_REFp_buffer REFp)
Definition: ad77681.c:717
ad77681_sinc5_fir_decimate
Definition: ad77681.h:405
Header file of Delay functions.
int32_t ad77681_CRC_status_handling(struct ad77681_dev *dev, uint16_t *data_buffer)
Definition: ad77681.c:338
#define AD77681_MASTER_DIG_ERROR_MSK
Definition: ad77681.h:268
ad77681_AINp_precharge
Definition: ad77681.h:432
enum ad77681_conv_mode conv_mode
Definition: ad77681.h:560
@ AD77681_BUFn_ENABLED
Definition: ad77681.h:439
int32_t ad77681_error_flags_enabe(struct ad77681_dev *dev)
Definition: ad77681.c:1620
#define AD77681_REG_COEFF_CONTROL
Definition: ad77681.h:97
#define AD77681_ANALOG_REF_BUF_NEG(x)
Definition: ad77681.h:128
#define AD77681_CONVERSION_MODE(x)
Definition: ad77681.h:122
#define AD77681_OFFSET_HI_MSK
Definition: ad77681.h:210
#define AD77681_DIGI_FILTER_60HZ_REJ_EN(x)
Definition: ad77681.h:140
bool adc_err_ext_clk_qual
Definition: ad77681.h:507
@ AD77681_AINp_DISABLED
Definition: ad77681.h:434
#define AD77681_ADC_DIAG_ERR_DLDO_PSM_MSK
Definition: ad77681.h:244
int32_t ad77681_set_REFn_buffer(struct ad77681_dev *dev, enum ad77681_REFn_buffer REFn)
Definition: ad77681.c:692
@ AD77681_GPIO1
Definition: ad77681.h:472
#define AD77681_DIG_DIAG_ERR_FUSE_CRC_MSK
Definition: ad77681.h:260
#define AD77681_SYNC_RST_SPI_RESET_MSK
Definition: ad77681.h:165
enum no_os_spi_mode mode
Definition: no_os_spi.h:139
enum ad77681_filter_type filter
Definition: ad77681.h:571
#define ENABLE
Definition: ad77681.h:345
#define AD77681_REG_SPI_DIAG_ENABLE
Definition: ad77681.h:74
#define AD77681_COEF_CONTROL_COEFFWRITEEN(x)
Definition: ad77681.h:307
@ AD77681_VCM_1_9V
Definition: ad77681.h:456
Definition: ad9361_util.h:75
int32_t ad77681_gpio_open_drain(struct ad77681_dev *dev, enum ad77681_gpios gpio_number, enum ad77681_gpio_output_type output_type)
Definition: ad77681.c:1544
int32_t ad77681_gpio_inout(struct ad77681_dev *dev, uint8_t direction, enum ad77681_gpios gpio_number)
Definition: ad77681.c:1436
enum ad77681_AINn_precharge AINn
Definition: ad77681.h:567
#define AD77681_SPI_DIAG_ERR_SPI_RD_MSK
Definition: ad77681.h:238
#define AD77681_GPIO_CNTRL_GPIO2_OD_EN_MSK
Definition: ad77681.h:171
#define AD77681_GPIO_CNTRL_GPIO0_OD_EN_MSK
Definition: ad77681.h:175
#define AD77681_REG_WRITE(x)
Definition: ad77681.h:323
int32_t ad77681_status(struct ad77681_dev *dev, struct ad77681_status_registers *status)
Definition: ad77681.c:1704
@ AD77681_WAKE
Definition: ad77681.h:417
int32_t ad77681_set_50HZ_rejection(struct ad77681_dev *dev, uint8_t enable)
Definition: ad77681.c:823
int32_t ad77681_set_crc_sel(struct ad77681_dev *dev, enum ad77681_crc_sel crc_sel)
Definition: ad77681.c:978
#define AD77681_REG_DIGITAL_FILTER
Definition: ad77681.h:60
enum ad77681_AINn_precharge AINn
Definition: ad77681.h:541
#define AD77681_REG_CONVERSION
Definition: ad77681.h:59
@ AD77681_POSITIVE_FS
Definition: ad77681.h:385
ad77681_power_mode
Definition: ad77681.h:351
enum ad77681_AINp_precharge AINp
Definition: ad77681.h:568
@ AD77681_SINC5_FIR_DECx128
Definition: ad77681.h:408
@ AD77681_ECO
Definition: ad77681.h:352
int32_t ad77681_set_AINn_buffer(struct ad77681_dev *dev, enum ad77681_AINn_precharge AINn)
Definition: ad77681.c:643
#define AD77681_REG_POWER_CLOCK
Definition: ad77681.h:56
#define AD77681_REG_SPI_DIAG_STATUS
Definition: ad77681.h:79
@ AD77681_CONTINUOUS_DATA_READ
Definition: ad77681.h:492
#define AD77681_GPIO_WRITE_1_MSK
Definition: ad77681.h:195
#define AD77681_MASTER_FILT_SAT_MSK
Definition: ad77681.h:270
uint8_t ad77681_compute_xor(uint8_t *data, uint8_t data_size, uint8_t init_val)
Definition: ad77681.c:90
int32_t ad77681_gpio_open_drain(struct ad77681_dev *dev, enum ad77681_gpios gpio_number, enum ad77681_gpio_output_type output_type)
Definition: ad77681.c:1544
#define AD77681_REG_ANALOG
Definition: ad77681.h:57
int32_t ad77681_gpio_inout(struct ad77681_dev *dev, uint8_t direction, enum ad77681_gpios gpio_number)
Definition: ad77681.c:1436
@ AD77681_CONV_CONTINUOUS
Definition: ad77681.h:365
@ AD77681_NEGATIVE_FS
Definition: ad77681.h:386
#define AD77681_POWER_CLK_POWER_DOWN
Definition: ad77681.h:110
int32_t ad77681_set_filter_type(struct ad77681_dev *dev, enum ad77681_sinc5_fir_decimate decimate, enum ad77681_filter_type filter, uint16_t sinc3_osr)
Definition: ad77681.c:756
@ AD77681_VCM_2_05V
Definition: ad77681.h:455
#define AD77681_REG_ADC_DIAG_ENABLE
Definition: ad77681.h:75
#define AD77681_GPIO_WRITE_3_MSK
Definition: ad77681.h:191
@ AD77681_AIN_SHORT
Definition: ad77681.h:384
ad77681_rdy_dout
Definition: ad77681.h:377
@ AD77681_SINC5_FIR_DECx64
Definition: ad77681.h:407
#define AD77681_GPIO_WRITE_0_MSK
Definition: ad77681.h:197
int32_t ad77681_set_convlen(struct ad77681_dev *dev, enum ad77681_conv_len conv_len)
Definition: ad77681.c:950
#define AD77681_INTERFACE_CONT_READ_MSK
Definition: ad77681.h:95
int32_t ad77681_set_REFp_buffer(struct ad77681_dev *dev, enum ad77681_REFp_buffer REFp)
Definition: ad77681.c:717
int32_t ad77681_set_AINp_buffer(struct ad77681_dev *dev, enum ad77681_AINp_precharge AINp)
Definition: ad77681.c:667
bool ref_det_error
Definition: ad77681.h:519
#define AD77681_REG_MASTER_STATUS
Definition: ad77681.h:78
@ AD77681_GLOBAL_GPIO_ENABLE
Definition: ad77681.h:465
int32_t ad77681_CRC_status_handling(struct ad77681_dev *dev, uint16_t *data_buffer)
Definition: ad77681.c:338
enum ad77681_REFp_buffer REFp
Definition: ad77681.h:570
#define AD77681_REG_INTERFACE_FORMAT
Definition: ad77681.h:55
#define AD77681_REG_OFFSET_LO
Definition: ad77681.h:70
int32_t ad77681_spi_read_mask(struct ad77681_dev *dev, uint8_t reg_addr, uint8_t mask, uint8_t *data)
Definition: ad77681.c:189
#define AD77681_ADC_DIAG_ERR_FILT_NOT_SET_MSK
Definition: ad77681.h:250
int32_t ad77681_set_mclk_div(struct ad77681_dev *dev, enum ad77681_mclk_div clk_div)
Definition: ad77681.c:589
bool conv_diag_sel
Definition: ad77681.h:536
int32_t ad77681_programmable_filter(struct ad77681_dev *dev, const float *coeffs, uint8_t num_coeffs)
Definition: ad77681.c:1146
int32_t ad77681_set_status_bit(struct ad77681_dev *dev, bool status_bit)
Definition: ad77681.c:1016
int32_t ad77681_set_convlen(struct ad77681_dev *dev, enum ad77681_conv_len conv_len)
Definition: ad77681.c:950
#define AD77681_GPIO_CNTRL_UGPIO_EN_MSK
Definition: ad77681.h:169
int32_t ad77681_set_continuos_read(struct ad77681_dev *dev, enum ad77681_continuous_read continuous_enable)
Definition: ad77681.c:844
int32_t ad77681_set_AINp_buffer(struct ad77681_dev *dev, enum ad77681_AINp_precharge AINp)
Definition: ad77681.c:667
enum ad77681_mclk_div mclk_div
Definition: ad77681.h:533
#define AD77681_REG_OFFSET_HI
Definition: ad77681.h:68
#define AD77681_INTERFACE_STATUS_EN_MSK
Definition: ad77681.h:89
#define AD77681_ANALOG_AIN_BUF_POS_OFF_MSK
Definition: ad77681.h:129
@ AD77681_SINC5_DECx16
Definition: ad77681.h:399
#define AD77681_REG_SINC3_DEC_RATE_LSB
Definition: ad77681.h:62
ad77681_conv_mode
Definition: ad77681.h:364
#define AD77681_POWER_CLK_PWRMODE(x)
Definition: ad77681.h:107
uint16_t vref
Definition: ad77681.h:574
#define AD77681_SPI_DIAG_ERR_SPI_WR(x)
Definition: ad77681.h:241
int32_t ad77681_set_50HZ_rejection(struct ad77681_dev *dev, uint8_t enable)
Definition: ad77681.c:823
enum ad77681_conv_diag_mux diag_mux_sel
Definition: ad77681.h:535
enum ad77681_mclk_div mclk_div
Definition: ad77681.h:559
int32_t ad77681_spi_read_mask(struct ad77681_dev *dev, uint8_t reg_addr, uint8_t mask, uint8_t *data)
Definition: ad77681.c:189
enum ad77681_conv_len conv_len
Definition: ad77681.h:537
#define AD77681_GPIO_WRITE_ALL(x)
Definition: ad77681.h:200
@ AD77681_AINn_ENABLED
Definition: ad77681.h:427
int32_t ad77681_set_mclk_div(struct ad77681_dev *dev, enum ad77681_mclk_div clk_div)
Definition: ad77681.c:589
enum ad77681_AINp_precharge AINp
Definition: ad77681.h:542
#define AD77681_REG_GAIN_HI
Definition: ad77681.h:71
#define AD77681_OFFSET_LO(x)
Definition: ad77681.h:219
enum ad77681_VCM_out VCM_out
Definition: ad77681.h:566
Header file of the AD7768-1 Driver.
#define AD77681_REG_GPIO_CONTROL
Definition: ad77681.h:65
@ AD77681_VCM_1_1V
Definition: ad77681.h:458
ad77681_gobal_gpio_enable
Definition: ad77681.h:464
enum ad77681_crc_sel crc_sel
Definition: ad77681.h:564
#define AD77681_DIGI_FILTER_DEC_RATE(x)
Definition: ad77681.h:144
bool spi_crc_error
Definition: ad77681.h:516
@ AD77681_RDY_DOUT_DIS
Definition: ad77681.h:379
#define AD77681_REG_ACCESS_KEY
Definition: ad77681.h:99
int32_t ad77681_gpio_read(struct ad77681_dev *dev, uint8_t *value, enum ad77681_gpios gpio_number)
Definition: ad77681.c:1318
bool memoy_map_crc_error
Definition: ad77681.h:523
@ AD77681_VCM_0_9V
Definition: ad77681.h:459
#define AD77681_ACCESS_KEY_MSK
Definition: ad77681.h:318
#define AD77681_INTERFACE_CRC_EN_MSK
Definition: ad77681.h:85
enum ad77681_conv_mode conv_mode
Definition: ad77681.h:534
@ AD77681_BUFp_ENABLED
Definition: ad77681.h:446
#define AD77681_GPIO_CNTRL_GPIO0_OP_EN(x)
Definition: ad77681.h:186
@ AD77681_CONTINUOUS_READ_ENABLE
Definition: ad77681.h:485
uint32_t raw_data[4096]
Definition: ad77681.h:500
@ AD77681_SINC5_FIR_DECx256
Definition: ad77681.h:409
int32_t ad77681_apply_offset(struct ad77681_dev *dev, uint32_t value)
Definition: ad77681.c:1077
uint16_t count
Definition: ad77681.h:498
@ AD77681_GPIO3
Definition: ad77681.h:474
#define AD77681_POWER_CLK_PWRMODE_MSK
Definition: ad77681.h:106
enum ad77681_power_mode power_mode
Definition: ad77681.h:532
int32_t ad77681_set_VCM_output(struct ad77681_dev *dev, enum ad77681_VCM_out VCM_out)
Definition: ad77681.c:619
@ AD77681_GPIO_OPEN_DRAIN
Definition: ad77681.h:480
int32_t ad77681_set_power_mode(struct ad77681_dev *dev, enum ad77681_power_mode mode)
Definition: ad77681.c:563
@ AD77681_VCM_HALF_VCC
Definition: ad77681.h:453
#define AD77681_MASTER_ADC_ERROR_MSK
Definition: ad77681.h:267
ad77681_conv_diag_mux
Definition: ad77681.h:382
@ AD77681_CONV_24BIT
Definition: ad77681.h:373
@ AD77681_HARD_RESET
Definition: ad77681.h:423
@ AD77681_RDY_DOUT_EN
Definition: ad77681.h:378
Definition: ad77681.h:554
ad77681_crc_sel
Definition: ad77681.h:389
int32_t ad77681_apply_gain(struct ad77681_dev *dev, uint32_t value)
Definition: ad77681.c:1111
#define AD77681_REG_SINC3_DEC_RATE_MSB
Definition: ad77681.h:61
enum ad77681_filter_type filter
Definition: ad77681.h:545
#define AD77681_REG_OFFSET_MID
Definition: ad77681.h:69
#define AD77681_GPIO_CNTRL_GPIO0_OP_EN_MSK
Definition: ad77681.h:185
#define AD77681_GPIO_CNTRL_GPIO1_OP_EN(x)
Definition: ad77681.h:184
enum ad77681_sinc5_fir_decimate decimate
Definition: ad77681.h:572
bool conv_diag_sel
Definition: ad77681.h:562
bool spi_read_error
Definition: ad77681.h:514
Structure holding SPI descriptor.
Definition: no_os_spi.h:177
int32_t ad77681_set_conv_mode(struct ad77681_dev *dev, enum ad77681_conv_mode conv_mode, enum ad77681_conv_diag_mux diag_mux_sel, bool conv_diag_sel)
Definition: ad77681.c:911
#define AD77681_SYNC_RST_SPI_STARTB_MSK
Definition: ad77681.h:159
bool spi_error
Definition: ad77681.h:510
#define AD77681_ADC_DIAG_ERR_FILT_NOT_SET(x)
Definition: ad77681.h:251
uint32_t sample_rate
Definition: ad77681.h:576
int32_t ad77681_gpio_write(struct ad77681_dev *dev, uint8_t value, enum ad77681_gpios gpio_number)
Definition: ad77681.c:1377
#define AD77681_COEF_CONTROL_COEFFACCESSEN(x)
Definition: ad77681.h:305
@ AD77681_MCLK_DIV_2
Definition: ad77681.h:361
bool dldo_psm_error
Definition: ad77681.h:517
bool por_flag
Definition: ad77681.h:511
enum ad77681_REFp_buffer REFp
Definition: ad77681.h:544
#define AD77681_DIG_MEMMAP_CRC_ERROR_MSK
Definition: ad77681.h:295
@ AD77681_SLEEP
Definition: ad77681.h:416
#define AD77681_SPI_READ_ERROR_CLR(x)
Definition: ad77681.h:280
#define AD77681_ADC_FILT_NOT_SET_MSK
Definition: ad77681.h:291
#define AD77681_ANALOG_AIN_BUF_POS_OFF(x)
Definition: ad77681.h:130
bool ext_clk_qual_error
Definition: ad77681.h:522
#define AD77681_ANALOG_REF_BUF_POS_MSK
Definition: ad77681.h:125
int32_t ad77681_apply_gain(struct ad77681_dev *dev, uint32_t value)
Definition: ad77681.c:1111
int32_t ad77681_power_down(struct ad77681_dev *dev, enum ad77681_sleep_wake sleep_wake)
Definition: ad77681.c:872
int32_t ad77681_spi_reg_write(struct ad77681_dev *dev, uint8_t reg_addr, uint8_t reg_data)
Definition: ad77681.c:163
#define AD77681_SPI_CLK_CNT_ERROR_MSK
Definition: ad77681.h:278
#define AD77681_COEF_CONTROL_COEFFWRITEEN_MSK
Definition: ad77681.h:306
#define AD77681_MASTER_DIG_ERR_EXT_CLK_MSK
Definition: ad77681.h:269
#define AD77681_DIGI_FILTER_FILTER(x)
Definition: ad77681.h:142
#define AD77681_SPI_WRITE_ERROR_CLR(x)
Definition: ad77681.h:282
@ AD77681_CONV_PERIODIC
Definition: ad77681.h:368
ad77681_gpios
Definition: ad77681.h:470
#define AD77681_POWER_CLK_MCLK_DIV(x)
Definition: ad77681.h:112
ad77681_gpio_output_type
Definition: ad77681.h:478
enum ad77681_power_mode power_mode
Definition: ad77681.h:558
@ AD77681_VCM_OFF
Definition: ad77681.h:460
@ AD77681_GPIO0
Definition: ad77681.h:471
ad77681_VCM_out
Definition: ad77681.h:452
#define AD77681_SINC3_DEC_RATE_LSB_MSK
Definition: ad77681.h:151
int32_t ad77681_set_filter_type(struct ad77681_dev *dev, enum ad77681_sinc5_fir_decimate decimate, enum ad77681_filter_type filter, uint16_t sinc3_osr)
Definition: ad77681.c:756
#define AD77681_ANALOG_AIN_BUF_NEG_OFF_MSK
Definition: ad77681.h:131
uint16_t mclk
Definition: ad77681.h:549
#define INITIAL_CRC
Definition: ad77681.h:331
#define AD77681_GPIO_CNTRL_GPIO3_OP_EN(x)
Definition: ad77681.h:180
@ AD77681_BUFp_FULL_BUFFER_ON
Definition: ad77681.h:448
int32_t ad77681_set_power_mode(struct ad77681_dev *dev, enum ad77681_power_mode mode)
Definition: ad77681.c:563
uint16_t mclk
Definition: ad77681.h:575
#define AD77681_SINC3_DEC_RATE_LSB(x)
Definition: ad77681.h:152
#define AD77681_SPI_READ_ERROR_MSK
Definition: ad77681.h:279
ad7761_reset_option
Definition: ad77681.h:421
#define AD77681_REG_READ(x)
Definition: ad77681.h:322
#define AD77681_SINC3_DEC_RATE_MSB_MSK
Definition: ad77681.h:147
#define AD77681_GPIO_WRITE_2(x)
Definition: ad77681.h:194
#define AD77681_INTERFACE_CRC_TYPE_MSK
Definition: ad77681.h:87
#define AD77681_GPIO_READ_3_MSK
Definition: ad77681.h:203
#define AD77681_GPIO_READ_1_MSK
Definition: ad77681.h:205
int32_t ad77681_scratchpad(struct ad77681_dev *dev, uint8_t *sequence)
Definition: ad77681.c:1506
#define AD77681_DIG_DIAG_ERR_FUSE_CRC(x)
Definition: ad77681.h:261
void * no_os_malloc(size_t size)
Allocate memory and return a pointer to it.
Definition: chibios_alloc.c:49
#define AD77681_ADC_DIG_ERR_EXT_CLK_MSK
Definition: ad77681.h:292
@ AD77681_MEDIAN
Definition: ad77681.h:353
@ AD77681_REGISTER_DATA_READ
Definition: ad77681.h:491
int32_t ad77681_soft_reset(struct ad77681_dev *dev)
Definition: ad77681.c:1040
uint8_t ad77681_get_frame_byte(struct ad77681_dev *dev)
Definition: ad77681.c:253
#define AD77681_DIG_RAM_CRC_ERROR_MSK
Definition: ad77681.h:296
#define INITIAL_CRC_CRC8
Definition: ad77681.h:329
#define AD77681_POWER_CLK_MCLK_DIV_MSK
Definition: ad77681.h:111
#define AD77681_ANALOG2_VCM(x)
Definition: ad77681.h:136
#define AD77681_INTERFACE_CONT_READ_EN(x)
Definition: ad77681.h:96
int32_t ad77681_spi_reg_read(struct ad77681_dev *dev, uint8_t reg_addr, uint8_t *reg_data)
Definition: ad77681.c:113
ad77681_AINn_precharge
Definition: ad77681.h:426
uint16_t sinc3_osr
Definition: ad77681.h:573
@ AD77681_CRC
Definition: ad77681.h:390
#define AD77681_SPI_DIAG_ERR_SPI_CLK_CNT(x)
Definition: ad77681.h:237
int32_t ad77681_set_conv_mode(struct ad77681_dev *dev, enum ad77681_conv_mode conv_mode, enum ad77681_conv_diag_mux diag_mux_sel, bool conv_diag_sel)
Definition: ad77681.c:911
bool master_error
Definition: ad77681.h:504
#define AD77681_ADC_DIAG_ERR_FILT_SAT_MSK
Definition: ad77681.h:248
#define AD77681_ADC_FILT_SAT_MSK
Definition: ad77681.h:290
@ AD77681_MCLK_DIV_16
Definition: ad77681.h:358
#define AD77681_GPIO_CNTRL_GPIO1_OD_EN(x)
Definition: ad77681.h:174
@ AD77681_ALL_GPIOS
Definition: ad77681.h:475
void no_os_free(void *ptr)
Deallocate memory previously allocated by a call to no_os_calloc or no_os_malloc.
Definition: chibios_alloc.c:75
#define AD77681_ADC_DIAG_ERR_ALDO_PSM(x)
Definition: ad77681.h:247
#define AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN(x)
Definition: ad77681.h:188
#define AD77681_GPIO_READ_ALL_MSK
Definition: ad77681.h:207
ad77681_sleep_wake
Definition: ad77681.h:415
enum ad77681_REFn_buffer REFn
Definition: ad77681.h:543
#define AD77681_ADC_ALDO_PSM_ERROR_MSK
Definition: ad77681.h:288
@ AD77681_VCM_1_65V
Definition: ad77681.h:457
#define AD77681_DIG_DIAG_ERR_RAM_CRC(x)
Definition: ad77681.h:259
#define AD77681_REG_SCRATCH_PAD
Definition: ad77681.h:52
#define AD77681_CONVERSION_DIAG_SEL_MSK
Definition: ad77681.h:119
#define AD77681_OFFSET_HI(x)
Definition: ad77681.h:211
void no_os_udelay(uint32_t usecs)
Wait until usecs microseconds passed.
Definition: aducm3029_delay.c:120
uint8_t ad77681_get_rx_buf_len(struct ad77681_dev *dev)
Definition: ad77681.c:232
#define AD77681_SPI_CRC_ERROR_CLR(x)
Definition: ad77681.h:284
#define AD77681_ADC_REF_DET_ERROR_MSK
Definition: ad77681.h:289
#define AD77681_COEF_CONTROL_COEFFACCESSEN_MSK
Definition: ad77681.h:304
#define AD77681_CONVERSION_DIAG_MUX_SEL(x)
Definition: ad77681.h:118
@ AD77681_NO_CRC
Definition: ad77681.h:392
#define AD77681_SPI_DIAG_ERR_SPI_CLK_CNT_MSK
Definition: ad77681.h:236
ad77681_REFn_buffer
Definition: ad77681.h:438
#define AD77681_SYNC_RST_SPI_RESET(x)
Definition: ad77681.h:166
#define AD77681_DIGI_FILTER_60HZ_REJ_EN_MSK
Definition: ad77681.h:139
#define AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN_MSK
Definition: ad77681.h:177
@ AD77681_SINC5_DECx8
Definition: ad77681.h:398
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:119
#define AD77681_GPIO_CNTRL_GPIO1_OD_EN_MSK
Definition: ad77681.h:173
#define AD77681_ADC_DIAG_ERR_ALDO_PSM_MSK
Definition: ad77681.h:246
#define AD77681_REG_GPIO_READ
Definition: ad77681.h:67
@ AD77681_VCM_2_5V
Definition: ad77681.h:454
bool dig_error
Definition: ad77681.h:506
enum ad77681_conv_len conv_len
Definition: ad77681.h:563
#define AD77681_CRC8_POLY
Definition: ad77681.h:326
#define AD77681_DIG_FUS_CRC_ERROR_MSK
Definition: ad77681.h:297
enum ad77681_sinc5_fir_decimate decimate
Definition: ad77681.h:546
@ AD77681_CONV_ONE_SHOT
Definition: ad77681.h:366
#define AD77681_DIGI_FILTER_DEC_RATE_MSK
Definition: ad77681.h:143
#define AD77681_GPIO_READ_2_MSK
Definition: ad77681.h:204
bool ram_crc_error
Definition: ad77681.h:524
@ AD77681_SINC5_FIR_DECx1024
Definition: ad77681.h:411
int32_t ad77681_update_sample_rate(struct ad77681_dev *dev)
Definition: ad77681.c:435
@ AD77681_MCLK_DIV_4
Definition: ad77681.h:360
int32_t ad77681_global_gpio(struct ad77681_dev *dev, enum ad77681_gobal_gpio_enable gpio_enable)
Definition: ad77681.c:1489
@ AD77681_SINC5_FIR_DECx32
Definition: ad77681.h:406
#define AD77681_SPI_IGNORE_ERROR_CLR(x)
Definition: ad77681.h:277
@ AD77681_CONV_SINGLE
Definition: ad77681.h:367
int32_t ad77681_spi_read_adc_data(struct ad77681_dev *dev, uint8_t *adc_data, enum ad77681_data_read_mode mode)
Definition: ad77681.c:280
#define AD77681_ANALOG_AIN_BUF_NEG_OFF(x)
Definition: ad77681.h:132
#define AD77681_ANALOG_REF_BUF_POS(x)
Definition: ad77681.h:126
uint8_t data_frame_byte
Definition: ad77681.h:551
#define AD77681_GPIO_WRITE_0(x)
Definition: ad77681.h:198
#define AD77681_ADC_DIAG_ERR_FILT_SAT(x)
Definition: ad77681.h:249
uint8_t ad77681_compute_crc8(uint8_t *data, uint8_t data_size, uint8_t init_val)
Definition: ad77681.c:62
#define AD77681_SPI_CRC_ERROR_MSK
Definition: ad77681.h:283
#define AD77681_GAIN_LOW(x)
Definition: ad77681.h:231
#define AD77681_SINC3_DEC_RATE_MSB(x)
Definition: ad77681.h:148
#define AD77681_ANALOG2_VCM_MSK
Definition: ad77681.h:135
#define AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN(x)
Definition: ad77681.h:178
uint16_t samples
Definition: ad77681.h:499
uint8_t data_frame_byte
Definition: ad77681.h:577
#define AD77681_SPI_DIAG_ERR_SPI_WR_MSK
Definition: ad77681.h:240
#define AD77681_SPI_WRITE_ERROR_MSK
Definition: ad77681.h:281
int32_t ad77681_SINC3_ODR(struct ad77681_dev *dev, uint16_t *sinc3_dec_reg, float sinc3_odr)
Definition: ad77681.c:516
struct no_os_spi_desc * spi_desc
Definition: ad77681.h:530
#define AD77681_GAIN_MID_MSK
Definition: ad77681.h:226
#define AD77681_ADC_DIAG_ERR_DLDO_PSM(x)
Definition: ad77681.h:245
enum ad77681_REFn_buffer REFn
Definition: ad77681.h:569
#define AD77681_GPIO_CNTRL_GPIO1_OP_EN_MSK
Definition: ad77681.h:183
@ AD77681_CONV_16BIT
Definition: ad77681.h:374
#define AD77681_REG_ADC_DATA
Definition: ad77681.h:77
int32_t ad77681_spi_write_mask(struct ad77681_dev *dev, uint8_t reg_addr, uint8_t mask, uint8_t data)
Definition: ad77681.c:211
int32_t ad77681_programmable_filter(struct ad77681_dev *dev, const float *coeffs, uint8_t num_coeffs)
Definition: ad77681.c:1146
#define AD77681_ACCESS_KEY(x)
Definition: ad77681.h:319
@ AD77681_CONV_STANDBY
Definition: ad77681.h:369
int32_t ad77681_set_status_bit(struct ad77681_dev *dev, bool status_bit)
Definition: ad77681.c:1016
uint8_t ad77681_compute_crc8(uint8_t *data, uint8_t data_size, uint8_t init_val)
Definition: ad77681.c:62
#define AD77681_CONVERSION_MODE_MSK
Definition: ad77681.h:121
int32_t no_os_spi_init(struct no_os_spi_desc **desc, const struct no_os_spi_init_param *param)
Initialize the SPI communication peripheral.
Definition: no_os_spi.c:58
int32_t ad77681_set_continuos_read(struct ad77681_dev *dev, enum ad77681_continuous_read continuous_enable)
Definition: ad77681.c:844
ad77681_conv_len
Definition: ad77681.h:372
bool filt_not_set_error
Definition: ad77681.h:521
@ AD77681_SINC5
Definition: ad77681.h:397
@ AD77681_GPIO_STRONG_DRIVER
Definition: ad77681.h:479
ad77681_continuous_read
Definition: ad77681.h:484
#define AD77681_MASTER_SPI_ERROR_MSK
Definition: ad77681.h:272
uint8_t status_bit
Definition: ad77681.h:539
#define AD77681_INTERFACE_CRC_EN(x)
Definition: ad77681.h:86
#define AD77681_ADC_DLDO_PSM_ERROR_MSK
Definition: ad77681.h:287
@ AD77681_XOR
Definition: ad77681.h:391
#define AD77681_GAIN_HI_MSK
Definition: ad77681.h:222
bool adc_error
Definition: ad77681.h:505
enum ad77681_conv_diag_mux diag_mux_sel
Definition: ad77681.h:561
uint16_t sinc3_osr
Definition: ad77681.h:547
#define AD77681_REG_SYNC_RESET
Definition: ad77681.h:64
#define AD77681_INTERFACE_CONVLEN_MSK
Definition: ad77681.h:91
int32_t ad77681_spi_write_mask(struct ad77681_dev *dev, uint8_t reg_addr, uint8_t mask, uint8_t data)
Definition: ad77681.c:211
#define AD77681_GPIO_CNTRL_GPIO2_OD_EN(x)
Definition: ad77681.h:172
int32_t ad77681_global_gpio(struct ad77681_dev *devices, enum ad77681_gobal_gpio_enable gpio_enable)
Definition: ad77681.c:1489
@ AD77681_GPIO2
Definition: ad77681.h:473
#define AD77681_GAIN_HI(x)
Definition: ad77681.h:223
enum no_os_spi_mode mode
Definition: no_os_spi.h:187
#define AD77681_GPIO_CNTRL_UGPIO_EN(x)
Definition: ad77681.h:170
bool finish
Definition: ad77681.h:497
int32_t ad77681_update_sample_rate(struct ad77681_dev *dev)
Definition: ad77681.c:435
#define AD77681_SCRATCHPAD(x)
Definition: ad77681.h:103
bool adc_filt_saturated
Definition: ad77681.h:508
int32_t ad77681_status(struct ad77681_dev *dev, struct ad77681_status_registers *status)
Definition: ad77681.c:1704
enum ad77681_VCM_out VCM_out
Definition: ad77681.h:540
uint32_t sample_rate
Definition: ad77681.h:550
#define INITIAL_CRC_XOR
Definition: ad77681.h:330
bool aldo_psm_error
Definition: ad77681.h:518
#define AD77681_SPI_DIAG_ERR_SPI_RD(x)
Definition: ad77681.h:239
#define AD77681_SPI_IGNORE_ERROR_MSK
Definition: ad77681.h:276
#define EXIT_CONT_READ
Definition: ad77681.h:337
@ AD77681_MCLK_DIV_8
Definition: ad77681.h:359
#define AD77681_INTERFACE_STATUS_EN(x)
Definition: ad77681.h:90
bool spi_clock_count
Definition: ad77681.h:513
int32_t ad77681_gpio_read(struct ad77681_dev *dev, uint8_t *value, enum ad77681_gpios gpio_number)
Definition: ad77681.c:1318
#define AD77681_OFFSET_MID(x)
Definition: ad77681.h:215
bool spi_write_error
Definition: ad77681.h:515
#define AD77681_INTERFACE_CONVLEN(x)
Definition: ad77681.h:92
int32_t ad77681_set_AINn_buffer(struct ad77681_dev *dev, enum ad77681_AINn_precharge AINn)
Definition: ad77681.c:643
struct no_os_spi_init_param spi_eng_dev_init
Definition: ad77681.h:556
int32_t ad77681_clear_error_flags(struct ad77681_dev *dev)
Definition: ad77681.c:1587
uint8_t ad77681_compute_xor(uint8_t *data, uint8_t data_size, uint8_t init_val)
Definition: ad77681.c:90
#define AD77681_CONVERSION_DIAG_MUX_MSK
Definition: ad77681.h:117
@ AD77681_AINp_ENABLED
Definition: ad77681.h:433
uint16_t vref
Definition: ad77681.h:548
#define AD77681_DIG_DIAG_ERR_RAM_CRC_MSK
Definition: ad77681.h:258
ad77681_REFp_buffer
Definition: ad77681.h:445
@ AD77681_BUFn_DISABLED
Definition: ad77681.h:440
ad77681_data_read_mode
Definition: ad77681.h:490
int32_t ad77681_soft_reset(struct ad77681_dev *dev)
Definition: ad77681.c:1040
bool filt_sat_error
Definition: ad77681.h:520
#define AD77681_REG_DIG_DIAG_ENABLE
Definition: ad77681.h:76
int32_t ad77681_apply_offset(struct ad77681_dev *dev, uint32_t value)
Definition: ad77681.c:1077
int32_t ad77681_SINC3_ODR(struct ad77681_dev *dev, uint16_t *sinc3_dec_reg, float sinc3_odr)
Definition: ad77681.c:516
ad77681_mclk_div
Definition: ad77681.h:357
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:131
#define AD77681_INTERFACE_CRC_TYPE(x)
Definition: ad77681.h:88
#define AD77681_GPIO_CNTRL_GPIO3_OP_EN_MSK
Definition: ad77681.h:179
int32_t ad77681_set_VCM_output(struct ad77681_dev *dev, enum ad77681_VCM_out VCM_out)
Definition: ad77681.c:619
#define AD77681_REG_ANALOG2
Definition: ad77681.h:58
uint8_t status_bit
Definition: ad77681.h:565