no-OS
app_clocking.h
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1 /***************************************************************************/
33 #ifndef __APP_CLOCKING_H
34 #define __APP_CLOCKING_H
35 
36 #include <stdint.h>
37 #include "ad9528.h"
38 
44  /* Settings selection */
45  uint8_t uc;
46  /* jesd receive clock */
47  uint32_t lmfc_rate_hz;
48 };
49 
54 struct app_clocking {
55  /* Structure holding a clock device descriptor */
57 };
58 
59 /* @brief Application clocking setup. */
60 int32_t app_clocking_init(struct app_clocking **app,
62 
63 /* @brief Application clocking remove. */
64 int32_t app_clocking_remove(struct app_clocking *app);
65 
66 #endif /* __APP_CLOCKING_H */
axi_clkgen_init::name
const char * name
Definition: clk_axi_clkgen.h:51
SYSREF_SRC_INTERNAL
#define SYSREF_SRC_INTERNAL
Definition: ad9528.h:275
app_clocking_init::uc
uint8_t uc
Definition: app_clocking.h:45
axi_clkgen::name
const char * name
Definition: clk_axi_clkgen.h:45
no_os_alloc.h
RX_CLKGEN_BASEADDR
#define RX_CLKGEN_BASEADDR
Definition: parameters.h:97
no_os_gpio_init_param
Structure holding the parameters for GPIO initialization.
Definition: no_os_gpio.h:79
app_talise.h
Talise initialization and control routines.
app_config.h
Config file for ADRV9009 project.
SYSREF_NSHOT_4_PULSES
#define SYSREF_NSHOT_4_PULSES
Definition: ad9528.h:287
clocking_init
adiHalErr_t clocking_init(uint32_t rx_div40_rate_hz, uint32_t tx_div40_rate_hz, uint32_t rx_os_div40_rate_hz, uint32_t device_clock_khz, uint32_t lmfc_rate_hz)
Definition: app_clocking.c:95
altera_a10_fpll_enable
int32_t altera_a10_fpll_enable(struct altera_a10_fpll *fpll)
altera_a10_fpll_enable
Definition: clk_altera_a10_fpll.c:448
DRIVER_MODE_HSTL
#define DRIVER_MODE_HSTL
Definition: ad9528.h:255
GPIO_PS
@ GPIO_PS
Definition: xilinx_gpio.h:56
SPI_PS
@ SPI_PS
Definition: xilinx_spi.h:62
rx_clkgen
struct axi_clkgen * rx_clkgen
Definition: app_clocking.c:90
no_os_spi.h
Header file of SPI Interface.
app_clocking
Structure holding clocking app descriptor.
Definition: app_clocking.h:54
RPOLE2_900_OHM
@ RPOLE2_900_OHM
Definition: ad9523.h:336
parameters.h
Parameters Definitions.
ad9528_platform_data::pll2_charge_pump_current_nA
uint32_t pll2_charge_pump_current_nA
Definition: ad9528.h:418
ad9528_channel_spec
Output channel configuration.
Definition: ad9528.h:330
ad9528_spi_param
const struct no_os_spi_init_param ad9528_spi_param
Definition: common_data.c:45
hmc7044.h
Header file of HMC7044, HMC7043 Driver.
altera_gpio.h
clk_axi_clkgen.h
Driver for the Analog Devices AXI CLKGEN.
ADC_SYSREF_CLK
#define ADC_SYSREF_CLK
Definition: app_clocking.c:60
ad9528_platform_data::pll2_bypass_en
bool pll2_bypass_en
Definition: ad9528.h:432
pr_err
#define pr_err(fmt, args...)
Definition: no_os_print_log.h:88
ad9528_platform_data::num_channels
uint32_t num_channels
Definition: ad9528.h:446
clocking_deinit
void clocking_deinit(void)
Definition: app_clocking.c:728
no_os_delay.h
Header file of Delay functions.
xil_gpio_ops
const struct no_os_gpio_platform_ops xil_gpio_ops
Xilinx platform specific GPIO platform ops structure.
Definition: xilinx_gpio.c:450
uc_settings
Definition: uc_settings.h:41
ad9528_clk_set_rate
int32_t ad9528_clk_set_rate(struct ad9528_dev *dev, uint32_t chan, uint32_t rate)
Set channel rate.
Definition: ad9528.c:1222
axi_clkgen_init
Definition: clk_axi_clkgen.h:50
ad9528_platform_data::refa_en
uint8_t refa_en
Definition: ad9528.h:361
hmc7044_init
int32_t hmc7044_init(struct hmc7044_dev **device, const struct hmc7044_init_param *init_param)
Definition: hmc7044.c:1466
axi_clkgen_set_rate
int32_t axi_clkgen_set_rate(struct axi_clkgen *clkgen, uint32_t rate)
axi_clkgen_set_rate
Definition: clk_axi_clkgen.c:414
ad9528_platform_data::pll2_r1_div
uint8_t pll2_r1_div
Definition: ad9528.h:426
NIOS_II_SPI
@ NIOS_II_SPI
Definition: altera_spi.h:48
app_clocking.h
Clock setup and initialization routines.
ad9528_platform_data::spi3wire
uint8_t spi3wire
Definition: ad9528.h:358
ad9528_init_param
Definition: ad9528.h:497
FPGA_REF_CLK
#define FPGA_REF_CLK
Definition: app_clocking.c:59
no_os_gpio_init_param::number
int32_t number
Definition: no_os_gpio.h:83
no_os_print_log.h
Print messages helpers.
altera_a10_fpll_init::name
const char * name
Definition: clk_altera_a10_fpll.h:52
TX_CLKGEN_BASEADDR
#define TX_CLKGEN_BASEADDR
Definition: parameters.h:95
FMC_SYSREF
#define FMC_SYSREF
Definition: app_clocking.h:61
axi_clkgen_init
int32_t axi_clkgen_init(struct axi_clkgen **clk, const struct axi_clkgen_init *init)
axi_clkgen_init
Definition: clk_axi_clkgen.c:520
ad9528_platform_data::rpole2
uint8_t rpole2
Definition: ad9528.h:436
axi_clkgen
Definition: clk_axi_clkgen.h:44
no_os_calloc
void * no_os_calloc(size_t nitems, size_t size)
Allocate memory and return a pointer to it, set memory to 0.
Definition: chibios_alloc.c:54
ad9528_clk_round_rate
uint32_t ad9528_clk_round_rate(struct ad9528_dev *dev, uint32_t chan, uint32_t rate)
Calculate closest possible rate.
Definition: ad9528.c:1186
DRIVER_MODE_LVDS
#define DRIVER_MODE_LVDS
Definition: ad9528.h:253
SYSREF_NSHOT_1_PULSE
#define SYSREF_NSHOT_1_PULSE
Definition: ad9528.h:285
CPOLE1_16_PF
@ CPOLE1_16_PF
Definition: ad9523.h:356
uc_settings::clk_hz
uint64_t(* clk_hz)[3]
Definition: uc_settings.h:43
altera_a10_fpll_set_rate
int32_t altera_a10_fpll_set_rate(struct altera_a10_fpll *fpll, uint32_t rate)
altera_a10_fpll_set_rate
Definition: clk_altera_a10_fpll.c:340
NIOS_II_GPIO
@ NIOS_II_GPIO
Definition: altera_gpio.h:53
ad9528_platform_data::sysref_req_en
bool sysref_req_en
Definition: ad9528.h:411
adi_hal.h
Contains Talise ADI HAL function prototypes type definitions for adi_hal.c.
app_ad9083_check_sysref_rate
bool app_ad9083_check_sysref_rate(uint32_t lmfc, uint32_t sysref)
Check sysref is submultiple of lmfc.
Definition: app_ad9083.c:62
ad9528_platform_data::sysref_req_trigger_mode
uint8_t sysref_req_trigger_mode
Definition: ad9528.h:409
xil_spi_param
struct xil_spi_init_param xil_spi_param
Definition: parameters.c:51
ADC_REF_CLK
#define ADC_REF_CLK
Definition: app_clocking.c:61
altera_a10_fpll_remove
int32_t altera_a10_fpll_remove(struct altera_a10_fpll *fpll)
altera_a10_fpll_remove
Definition: clk_altera_a10_fpll.c:487
altera_spi_ops
const struct no_os_spi_platform_ops altera_spi_ops
Altera platform specific SPI platform ops structure.
Definition: altera_spi.c:158
no_os_spi_init_param::device_id
uint32_t device_id
Definition: no_os_spi.h:142
RX_OS_CLKGEN_BASEADDR
#define RX_OS_CLKGEN_BASEADDR
Definition: parameters.h:122
app_clocking::clkchip_device
struct ad9528_dev * clkchip_device
Definition: app_clocking.h:56
app_clocking.h
Clock setup and initialization routines.
SPI_CS_DECODE
#define SPI_CS_DECODE
Definition: xilinx_spi.h:47
SYSREF_PATTERN_NSHOT
#define SYSREF_PATTERN_NSHOT
Definition: ad9528.h:278
hmc7044_chan_spec
Definition: hmc7044.h:47
ad9528_platform_data::vcxo_freq
uint32_t vcxo_freq
Definition: ad9528.h:356
get_uc_settings
struct uc_settings * get_uc_settings()
Get use case settings.
Definition: uc_settings.c:196
ad9528_platform_data::pll2_vco_div_m1
uint8_t pll2_vco_div_m1
Definition: ad9528.h:430
ad9528_platform_data::osc_in_cmos_neg_inp_en
uint8_t osc_in_cmos_neg_inp_en
Definition: ad9528.h:381
hmc7044_clk_set_rate
int32_t hmc7044_clk_set_rate(struct hmc7044_dev *dev, uint32_t chan_num, uint64_t rate)
Definition: hmc7044.c:452
no_os_error.h
Error codes definition.
ad9528_platform_data::sysref_nshot_mode
uint8_t sysref_nshot_mode
Definition: ad9528.h:407
uc_settings.h
Use Case Settings of AD9083 project.
DEV_SYSREF
#define DEV_SYSREF
Definition: app_clocking.h:60
hmc7044_remove
int32_t hmc7044_remove(struct hmc7044_dev *device)
Definition: hmc7044.c:1632
app_clocking_init::lmfc_rate_hz
uint32_t lmfc_rate_hz
Definition: app_clocking.h:47
clk_hz
uint64_t clk_hz[][3]
Definition: uc_settings.c:22
clkchip_gpio_init_param
const struct no_os_gpio_init_param clkchip_gpio_init_param
Definition: common_data.c:55
FPGA_SYSREF_CLK
#define FPGA_SYSREF_CLK
Definition: app_clocking.c:57
altera_spi_init_param
Structure holding the initialization parameters for Altera platform specific SPI parameters.
Definition: altera_spi.h:56
ad9528_init_param::gpio_resetb
struct no_os_gpio_init_param * gpio_resetb
Definition: ad9528.h:501
clkchip_device
struct ad9528_dev * clkchip_device
Definition: app_clocking.c:82
hmc7044_chan_spec::disable
bool disable
Definition: hmc7044.h:49
ad9528_platform_data::pll1_feedback_src_vcxo
uint8_t pll1_feedback_src_vcxo
Definition: ad9528.h:391
SPI_PL
@ SPI_PL
Definition: xilinx_spi.h:60
xil_gpio_param
struct xil_gpio_init_param xil_gpio_param
Definition: parameters.c:46
tx_clkgen
struct axi_clkgen * tx_clkgen
Definition: app_clocking.c:91
ad9528_platform_data
platform specific information
Definition: ad9528.h:354
hmc7044_init_param
Definition: hmc7044.h:102
hmc7044_init_param::spi_init
struct no_os_spi_init_param * spi_init
Definition: hmc7044.h:103
altera_gpio_init_param::type
enum gpio_type type
Definition: altera_gpio.h:63
adrv9009_check_sysref_rate
bool adrv9009_check_sysref_rate(uint32_t lmfc, uint32_t sysref)
Definition: app_talise.c:70
GPIO_DEVICE_ID
#define GPIO_DEVICE_ID
Definition: parameters.h:87
SYSREF_PATTERN_CONTINUOUS
#define SYSREF_PATTERN_CONTINUOUS
Definition: ad9528.h:279
ad9528_platform_data::rzero
uint8_t rzero
Definition: ad9528.h:438
CLK_RESETB_GPIO
#define CLK_RESETB_GPIO
Definition: parameters.h:178
xilinx_gpio.h
ADIHAL_OK
@ ADIHAL_OK
Definition: adi_hal.h:43
ad9528_platform_data::sysref_pattern_mode
uint8_t sysref_pattern_mode
Definition: ad9528.h:403
ad9528_init_param::spi_init
struct no_os_spi_init_param spi_init
Definition: ad9528.h:499
xil_spi_init_param::type
enum xil_spi_type type
Definition: xilinx_spi.h:74
clk_altera_a10_fpll.h
Driver for the Altera FPLL.
altera_a10_fpll::name
const char * name
Definition: clk_altera_a10_fpll.h:45
CLK_AD9258_CS
#define CLK_AD9258_CS
Definition: parameters.h:47
app_ad9083.h
FPGA_GLBL_CLK
#define FPGA_GLBL_CLK
Definition: app_clocking.c:58
hmc7044_init_param::pll2_freq
uint32_t pll2_freq
Definition: hmc7044.h:113
xil_spi_init_param
Structure holding the initialization parameters for Xilinx platform specific SPI parameters when usin...
Definition: xilinx_spi.h:72
ad9528_platform_data::cpole1
uint8_t cpole1
Definition: ad9528.h:440
ad9528_platform_data::pll2_n2_div
uint8_t pll2_n2_div
Definition: ad9528.h:428
hmc7044_dev
Definition: hmc7044.h:64
app_clocking_init
int32_t app_clocking_init(struct app_clocking **app, struct app_clocking_init *init_param)
Initialize the clocking app.
Definition: app_clocking.c:74
SOURCE_VCO
#define SOURCE_VCO
Definition: ad9528.h:258
altera_gpio_init_param
Structure holding the initialization parameters for Altera platform specific GPIO parameters.
Definition: altera_gpio.h:61
app_clocking_init
Structure holding the parameters for clocking app initialization.
Definition: app_clocking.h:43
ad9528_platform_data::refa_r_div
uint16_t refa_r_div
Definition: ad9528.h:385
altera_a10_fpll_init
Definition: clk_altera_a10_fpll.h:51
rx_os_clkgen
struct axi_clkgen * rx_os_clkgen
Definition: app_clocking.c:92
no_os_free
void no_os_free(void *ptr)
Deallocate memory previously allocated by a call to no_os_calloc or no_os_malloc.
Definition: chibios_alloc.c:69
ad9528_dev
Definition: ad9528.h:480
ad9528_remove
int32_t ad9528_remove(struct ad9528_dev *dev)
Free the resources allocated by ad9528_setup().
Definition: ad9528.c:1123
ad9528_channel_spec::divider_phase
uint8_t divider_phase
Definition: ad9528.h:343
ad9528_channel_spec::driver_mode
uint8_t driver_mode
Definition: ad9528.h:338
hmc7044_chan_spec::divider
unsigned int divider
Definition: hmc7044.h:56
FMC_CLK
#define FMC_CLK
Definition: app_clocking.h:59
NULL
#define NULL
Definition: wrapper.h:64
ad9528_platform_data::sysref_src
uint8_t sysref_src
Definition: ad9528.h:401
xil_spi_ops
const struct no_os_spi_platform_ops xil_spi_ops
Spi engine platform specific SPI platform ops structure.
Definition: xilinx_spi.c:453
app_clocking_remove
int32_t app_clocking_remove(struct app_clocking *app)
Free the resources allocated by app_clocking_init().
Definition: app_clocking.c:255
init_param
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:113
CLK_CS
#define CLK_CS
Definition: parameters.h:161
altera_a10_fpll
Definition: clk_altera_a10_fpll.h:44
SOURCE_SYSREF_VCO
#define SOURCE_SYSREF_VCO
Definition: ad9528.h:260
hmc7044_init_param::channels
struct hmc7044_chan_spec * channels
Definition: hmc7044.h:133
altera_a10_fpll_init
int32_t altera_a10_fpll_init(struct altera_a10_fpll **a10_fpll, const struct altera_a10_fpll_init *init)
altera_a10_fpll_init
Definition: clk_altera_a10_fpll.c:466
ad9528_platform_data::pll1_feedback_div
uint16_t pll1_feedback_div
Definition: ad9528.h:389
ad9528_init_param::pdata
struct ad9528_platform_data * pdata
Definition: ad9528.h:503
hmc7044_clk_round_rate
int32_t hmc7044_clk_round_rate(struct hmc7044_dev *dev, uint32_t rate, uint64_t *rounded_rate)
Definition: hmc7044.c:435
altera_a10_fpll_disable
void altera_a10_fpll_disable(struct altera_a10_fpll *fpll)
altera_a10_fpll_disable
Definition: clk_altera_a10_fpll.c:458
altera_spi.h
ad9528_init
int32_t ad9528_init(struct ad9528_init_param *init_param)
Initializes the AD9528.
Definition: ad9528.c:299
xil_gpio_init_param
Structure holding the initialization parameters for Xilinx platform specific GPIO parameters.
Definition: xilinx_gpio.h:64
ad9528_platform_data::stat0_pin_func_sel
uint8_t stat0_pin_func_sel
Definition: ad9528.h:451
ad9528_platform_data::refa_diff_rcv_en
uint8_t refa_diff_rcv_en
Definition: ad9528.h:366
ad9528_platform_data::channels
struct ad9528_channel_spec * channels
Definition: ad9528.h:448
ad9528_platform_data::stat1_pin_func_sel
uint8_t stat1_pin_func_sel
Definition: ad9528.h:453
ADIHAL_ERR
@ ADIHAL_ERR
Definition: adi_hal.h:50
no_os_gpio.h
Header file of GPIO Interface.
ad9528_channel_spec::output_dis
uint8_t output_dis
Definition: ad9528.h:336
GPIO_PL
@ GPIO_PL
Definition: xilinx_gpio.h:54
axi_clkgen_remove
int32_t axi_clkgen_remove(struct axi_clkgen *clkgen)
axi_clkgen_remove
Definition: clk_axi_clkgen.c:541
app_clocking_init
int32_t app_clocking_init(struct app_clocking **app, struct app_clocking_init *init_param)
Initialize the clocking app.
Definition: app_clocking.c:74
no_os_util.h
Header file of utility functions.
SYSREF_LEVEL_HIGH
#define SYSREF_LEVEL_HIGH
Definition: ad9528.h:293
ad9528_channel_spec::signal_source
uint8_t signal_source
Definition: ad9528.h:339
ad9528_platform_data::pll1_charge_pump_current_nA
uint16_t pll1_charge_pump_current_nA
Definition: ad9528.h:393
ad9528_platform_data::pll1_bypass_en
uint8_t pll1_bypass_en
Definition: ad9528.h:395
NO_OS_SPI_MODE_0
@ NO_OS_SPI_MODE_0
Definition: no_os_spi.h:61
xilinx_spi.h
DEV_CLK
#define DEV_CLK
Definition: app_clocking.h:58
ad9528_channel_spec::channel_num
uint8_t channel_num
Definition: ad9528.h:332
xil_gpio_init_param::type
enum xil_gpio_type type
Definition: xilinx_gpio.h:66
ad9528_setup
int32_t ad9528_setup(struct ad9528_dev **device, struct ad9528_init_param init_param)
Initializes the AD9528.
Definition: ad9528.c:702
RZERO_1850_OHM
@ RZERO_1850_OHM
Definition: ad9523.h:350
app_clocking_remove
int32_t app_clocking_remove(struct app_clocking *app)
Free the resources allocated by app_clocking_init().
Definition: app_clocking.c:255
no_os_spi_init_param
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:140
adiHalErr_t
adiHalErr_t
Enum of possible Errors Detected by HAL layer to be communicated to ADI APIs.
Definition: adi_hal.h:42