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33 #ifndef __APP_CLOCKING_H
34 #define __APP_CLOCKING_H
const char * name
Definition: clk_axi_clkgen.h:51
#define SYSREF_SRC_INTERNAL
Definition: ad9528.h:275
uint8_t uc
Definition: app_clocking.h:45
const char * name
Definition: clk_axi_clkgen.h:45
Structure holding the parameters for GPIO initialization.
Definition: no_os_gpio.h:79
Talise initialization and control routines.
Config file for ADRV9009 project.
#define SYSREF_NSHOT_4_PULSES
Definition: ad9528.h:287
#define TX_CLKGEN_BASEADDR
Definition: parameters.h:121
adiHalErr_t clocking_init(uint32_t rx_div40_rate_hz, uint32_t tx_div40_rate_hz, uint32_t rx_os_div40_rate_hz, uint32_t device_clock_khz, uint32_t lmfc_rate_hz)
Definition: app_clocking.c:95
int32_t altera_a10_fpll_enable(struct altera_a10_fpll *fpll)
altera_a10_fpll_enable
Definition: clk_altera_a10_fpll.c:448
#define DRIVER_MODE_HSTL
Definition: ad9528.h:255
@ GPIO_PS
Definition: xilinx_gpio.h:56
@ SPI_PS
Definition: xilinx_spi.h:62
struct axi_clkgen * rx_clkgen
Definition: app_clocking.c:90
Header file of SPI Interface.
Structure holding clocking app descriptor.
Definition: app_clocking.h:54
@ RPOLE2_900_OHM
Definition: ad9523.h:336
Output channel configuration.
Definition: ad9528.h:330
const struct no_os_spi_init_param ad9528_spi_param
Definition: common_data.c:45
Header file of HMC7044, HMC7043 Driver.
Driver for the Analog Devices AXI CLKGEN.
#define ADC_SYSREF_CLK
Definition: app_clocking.c:60
#define pr_err(fmt, args...)
Definition: no_os_print_log.h:88
void clocking_deinit(void)
Definition: app_clocking.c:728
Header file of Delay functions.
const struct no_os_gpio_platform_ops xil_gpio_ops
Xilinx platform specific GPIO platform ops structure.
Definition: xilinx_gpio.c:450
Definition: uc_settings.h:41
int32_t ad9528_clk_set_rate(struct ad9528_dev *dev, uint32_t chan, uint32_t rate)
Set channel rate.
Definition: ad9528.c:1222
Definition: clk_axi_clkgen.h:50
int32_t hmc7044_init(struct hmc7044_dev **device, const struct hmc7044_init_param *init_param)
Definition: hmc7044.c:1466
int32_t axi_clkgen_set_rate(struct axi_clkgen *clkgen, uint32_t rate)
axi_clkgen_set_rate
Definition: clk_axi_clkgen.c:414
struct xil_gpio_init_param xil_gpio_param
Definition: ad7616_sdz.c:103
@ NIOS_II_SPI
Definition: altera_spi.h:48
Clock setup and initialization routines.
#define FPGA_REF_CLK
Definition: app_clocking.c:59
int32_t number
Definition: no_os_gpio.h:83
const char * name
Definition: clk_altera_a10_fpll.h:52
#define FMC_SYSREF
Definition: app_clocking.h:61
int32_t axi_clkgen_init(struct axi_clkgen **clk, const struct axi_clkgen_init *init)
axi_clkgen_init
Definition: clk_axi_clkgen.c:520
Definition: clk_axi_clkgen.h:44
void * no_os_calloc(size_t nitems, size_t size)
Allocate memory and return a pointer to it, set memory to 0.
Definition: chibios_alloc.c:54
uint32_t ad9528_clk_round_rate(struct ad9528_dev *dev, uint32_t chan, uint32_t rate)
Calculate closest possible rate.
Definition: ad9528.c:1186
#define DRIVER_MODE_LVDS
Definition: ad9528.h:253
#define SYSREF_NSHOT_1_PULSE
Definition: ad9528.h:285
@ CPOLE1_16_PF
Definition: ad9523.h:356
uint64_t(* clk_hz)[3]
Definition: uc_settings.h:43
int32_t altera_a10_fpll_set_rate(struct altera_a10_fpll *fpll, uint32_t rate)
altera_a10_fpll_set_rate
Definition: clk_altera_a10_fpll.c:340
@ NIOS_II_GPIO
Definition: altera_gpio.h:53
Contains Talise ADI HAL function prototypes type definitions for adi_hal.c.
bool app_ad9083_check_sysref_rate(uint32_t lmfc, uint32_t sysref)
Check sysref is submultiple of lmfc.
Definition: app_ad9083.c:62
#define ADC_REF_CLK
Definition: app_clocking.c:61
int32_t altera_a10_fpll_remove(struct altera_a10_fpll *fpll)
altera_a10_fpll_remove
Definition: clk_altera_a10_fpll.c:487
const struct no_os_spi_platform_ops altera_spi_ops
Altera platform specific SPI platform ops structure.
Definition: altera_spi.c:158
uint32_t device_id
Definition: no_os_spi.h:127
#define RX_OS_CLKGEN_BASEADDR
Definition: parameters.h:122
struct ad9528_dev * clkchip_device
Definition: app_clocking.h:56
Clock setup and initialization routines.
#define SPI_CS_DECODE
Definition: xilinx_spi.h:47
#define SYSREF_PATTERN_NSHOT
Definition: ad9528.h:278
struct uc_settings * get_uc_settings()
Get use case settings.
Definition: uc_settings.c:196
int32_t hmc7044_clk_set_rate(struct hmc7044_dev *dev, uint32_t chan_num, uint64_t rate)
Definition: hmc7044.c:452
Use Case Settings of AD9083 project.
#define DEV_SYSREF
Definition: app_clocking.h:60
int32_t hmc7044_remove(struct hmc7044_dev *device)
Definition: hmc7044.c:1632
uint32_t lmfc_rate_hz
Definition: app_clocking.h:47
uint64_t clk_hz[][3]
Definition: uc_settings.c:22
const struct no_os_gpio_init_param clkchip_gpio_init_param
Definition: common_data.c:55
#define FPGA_SYSREF_CLK
Definition: app_clocking.c:57
Structure holding the initialization parameters for Altera platform specific SPI parameters.
Definition: altera_spi.h:56
struct no_os_gpio_init_param * gpio_resetb
Definition: ad9528.h:501
struct ad9528_dev * clkchip_device
Definition: app_clocking.c:82
bool disable
Definition: hmc7044.h:49
@ SPI_PL
Definition: xilinx_spi.h:60
struct axi_clkgen * tx_clkgen
Definition: app_clocking.c:91
Definition: hmc7044.h:102
struct no_os_spi_init_param * spi_init
Definition: hmc7044.h:103
enum gpio_type type
Definition: altera_gpio.h:63
bool adrv9009_check_sysref_rate(uint32_t lmfc, uint32_t sysref)
Definition: app_talise.c:70
#define SYSREF_PATTERN_CONTINUOUS
Definition: ad9528.h:279
#define CLK_RESETB_GPIO
Definition: parameters.h:168
@ ADIHAL_OK
Definition: adi_hal.h:43
struct no_os_spi_init_param spi_init
Definition: ad9528.h:499
enum xil_spi_type type
Definition: xilinx_spi.h:74
Driver for the Altera FPLL.
const char * name
Definition: clk_altera_a10_fpll.h:45
#define CLK_AD9258_CS
Definition: parameters.h:47
#define FPGA_GLBL_CLK
Definition: app_clocking.c:58
uint32_t pll2_freq
Definition: hmc7044.h:113
Structure holding the initialization parameters for Xilinx platform specific SPI parameters when usin...
Definition: xilinx_spi.h:72
int32_t app_clocking_init(struct app_clocking **app, struct app_clocking_init *init_param)
Initialize the clocking app.
Definition: app_clocking.c:74
#define SOURCE_VCO
Definition: ad9528.h:258
Structure holding the initialization parameters for Altera platform specific GPIO parameters.
Definition: altera_gpio.h:61
Structure holding the parameters for clocking app initialization.
Definition: app_clocking.h:43
Definition: clk_altera_a10_fpll.h:51
struct axi_clkgen * rx_os_clkgen
Definition: app_clocking.c:92
void no_os_free(void *ptr)
Deallocate memory previously allocated by a call to no_os_calloc or no_os_malloc.
Definition: chibios_alloc.c:69
int32_t ad9528_remove(struct ad9528_dev *dev)
Free the resources allocated by ad9528_setup().
Definition: ad9528.c:1123
uint8_t divider_phase
Definition: ad9528.h:343
uint8_t driver_mode
Definition: ad9528.h:338
unsigned int divider
Definition: hmc7044.h:56
#define FMC_CLK
Definition: app_clocking.h:59
#define NULL
Definition: wrapper.h:64
const struct no_os_spi_platform_ops xil_spi_ops
Spi engine platform specific SPI platform ops structure.
Definition: xilinx_spi.c:453
int32_t app_clocking_remove(struct app_clocking *app)
Free the resources allocated by app_clocking_init().
Definition: app_clocking.c:255
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:113
#define CLK_CS
Definition: parameters.h:157
Definition: clk_altera_a10_fpll.h:44
#define SOURCE_SYSREF_VCO
Definition: ad9528.h:260
struct hmc7044_chan_spec * channels
Definition: hmc7044.h:133
int32_t altera_a10_fpll_init(struct altera_a10_fpll **a10_fpll, const struct altera_a10_fpll_init *init)
altera_a10_fpll_init
Definition: clk_altera_a10_fpll.c:466
struct ad9528_platform_data * pdata
Definition: ad9528.h:503
#define GPIO_DEVICE_ID
Definition: parameters.h:83
int32_t hmc7044_clk_round_rate(struct hmc7044_dev *dev, uint32_t rate, uint64_t *rounded_rate)
Definition: hmc7044.c:435
void altera_a10_fpll_disable(struct altera_a10_fpll *fpll)
altera_a10_fpll_disable
Definition: clk_altera_a10_fpll.c:458
int32_t ad9528_init(struct ad9528_init_param *init_param)
Initializes the AD9528.
Definition: ad9528.c:299
Structure holding the initialization parameters for Xilinx platform specific GPIO parameters.
Definition: xilinx_gpio.h:64
@ ADIHAL_ERR
Definition: adi_hal.h:50
Header file of GPIO Interface.
uint8_t output_dis
Definition: ad9528.h:336
@ GPIO_PL
Definition: xilinx_gpio.h:54
int32_t axi_clkgen_remove(struct axi_clkgen *clkgen)
axi_clkgen_remove
Definition: clk_axi_clkgen.c:541
int32_t app_clocking_init(struct app_clocking **app, struct app_clocking_init *init_param)
Initialize the clocking app.
Definition: app_clocking.c:74
Header file of utility functions.
#define SYSREF_LEVEL_HIGH
Definition: ad9528.h:293
uint8_t signal_source
Definition: ad9528.h:339
@ NO_OS_SPI_MODE_0
Definition: no_os_spi.h:61
#define DEV_CLK
Definition: app_clocking.h:58
uint8_t channel_num
Definition: ad9528.h:332
enum xil_gpio_type type
Definition: xilinx_gpio.h:66
int32_t ad9528_setup(struct ad9528_dev **device, struct ad9528_init_param init_param)
Initializes the AD9528.
Definition: ad9528.c:702
@ RZERO_1850_OHM
Definition: ad9523.h:350
int32_t app_clocking_remove(struct app_clocking *app)
Free the resources allocated by app_clocking_init().
Definition: app_clocking.c:255
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:125
adiHalErr_t
Enum of possible Errors Detected by HAL layer to be communicated to ADI APIs.
Definition: adi_hal.h:42
