45#include "xparameters.h"
47#include "app_config.h"
54#ifdef _XPARAMETERS_PS_H_
55#ifdef XPS_BOARD_ZCU102
58#define GPIO_DEVICE_ID XPAR_PSU_GPIO_0_DEVICE_ID
59#define SPI_DEVICE_ID XPAR_PSU_SPI_0_DEVICE_ID
60#define UART_DEVICE_ID XPAR_PSU_UART_0_DEVICE_ID
61#define UART_IRQ_ID XPAR_XUARTPS_0_INTR
66#define DDR_MEM_BASEADDR XPAR_DDR_MEM_BASEADDR
70#define GPIO_DEVICE_ID XPAR_GPIO_0_DEVICE_ID
71#define SPI_DEVICE_ID XPAR_SPI_0_DEVICE_ID
72#define UART_IRQ_ID XPAR_AXI_INTC_AXI_UART_INTERRUPT_INTR
74#define DDR_MEM_BASEADDR XPAR_AXI_DDR_CNTRL_BASEADDR
77#define RX_JESD_BASEADDR XPAR_AXI_JESD204_RX_0_BASEADDR
78#define TX_JESD_BASEADDR XPAR_AXI_JESD204_TX_0_BASEADDR
81#define RX_XCVR_BASEADDR XPAR_AXI_ADRV904X_RX_XCVR_BASEADDR
82#define TX_XCVR_BASEADDR XPAR_AXI_ADRV904X_TX_XCVR_BASEADDR
85#define RX_CORE_BASEADDR XPAR_AD_IP_JESD204_TPL_ADC_0_BASEADDR
86#define TX_CORE_BASEADDR XPAR_AD_IP_JESD204_TPL_DAC_0_BASEADDR
89#define RX_DMA_BASEADDR XPAR_AXI_ADRV904X_RX_DMA_BASEADDR
90#define TX_DMA_BASEADDR XPAR_AXI_ADRV904X_TX_DMA_BASEADDR
93#define RX_CLKGEN_BASEADDR XPAR_AXI_ADRV904X_RX_CLKGEN_BASEADDR
94#define TX_CLKGEN_BASEADDR XPAR_AXI_ADRV904X_TX_CLKGEN_BASEADDR
95#ifdef XPAR_AXI_ADRV904X_RX_OS_CLKGEN_BASEADDR
96#define ORX_CLKGEN_BASEADDR XPAR_AXI_ADRV904X_RX_OS_CLKGEN_BASEADDR
99#if defined(DMA_EXAMPLE) || defined(IIO_EXAMPLE)
100#define DAC_BUFFER_SAMPLES 8192
101#define ADC_BUFFER_SAMPLES 32768
102#define ADC_CHANNELS 8
108#define DAC_GPIO_PLDDR_BYPASS (GPIO_OFFSET + 70)
109#define AD9528_RESET_B (GPIO_OFFSET + 69)
110#define AD9528_SYSREF_REQ (GPIO_OFFSET + 68)
111#define ADRV9040_RESET_B (GPIO_OFFSET + 56)
const struct xil_spi_init_param spi_extra
Definition ad5758_sdz.c:49
Structure holding the initialization parameters for Xilinx platform specific GPIO parameters.
Definition xilinx_gpio.h:56
Structure holding the initialization parameters for Xilinx platform specific SPI parameters when usin...
Definition xilinx_spi.h:60