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xilinx_compat.h
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1/***************************************************************************/
33#ifndef _XILINX_COMPAT_H_
34#define _XILINX_COMPAT_H_
35
36/*
37 * Vitis 2025+ removed XPAR_*_DEVICE_ID defines from xparameters.h and renamed
38 * some interrupt and parameter macros. Provide fallback defines so existing
39 * code builds with both old and new BSPs.
40 *
41 * This header is automatically appended to the BSP-generated xparameters.h
42 * during create_project (util.py), so all projects get these defines without
43 * needing per-project changes.
44 */
45
46/* CPU clock frequency renames: Vitis 2025+ generates the universal
47 * XPAR_CPU_CORE_CLOCK_FREQ_HZ instead of the per-core
48 * XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ. The BSP's xparameters_ps.h
49 * unconditionally references the old name at the expansion of
50 * XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ, so we must provide it before
51 * bspconfig.h pulls in xparameters_ps.h. */
52#if !defined(XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ) && defined(XPAR_CPU_CORE_CLOCK_FREQ_HZ)
53#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ XPAR_CPU_CORE_CLOCK_FREQ_HZ
54#endif
55
56/* Pull in bspconfig.h to get PLATFORM_ZYNQ / PLATFORM_ZYNQMP / PLATFORM_MB
57 * macros. In Vitis 2025+ these are no longer reachable through xparameters.h
58 * alone; bspconfig.h also brings xparameters_ps.h on PS designs. */
59#include "bspconfig.h"
60
61/* Zynq PS7 */
62#ifndef XPAR_PS7_SPI_0_DEVICE_ID
63#define XPAR_PS7_SPI_0_DEVICE_ID 0
64#endif
65#ifndef XPAR_PS7_SPI_1_DEVICE_ID
66#define XPAR_PS7_SPI_1_DEVICE_ID 1
67#endif
68#ifndef XPAR_PS7_GPIO_0_DEVICE_ID
69#define XPAR_PS7_GPIO_0_DEVICE_ID 0
70#endif
71#ifndef XPAR_XUARTPS_0_DEVICE_ID
72#define XPAR_XUARTPS_0_DEVICE_ID 0
73#endif
74
75/* GIC — xparameters_ps.h defines this as 0U for PS designs; use 0U here
76 * to match so that GCC does not warn on identical redefinition. */
77#ifndef XPAR_SCUGIC_SINGLE_DEVICE_ID
78#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
79#endif
80
81/* ZynqMP PSU */
82#ifndef XPAR_PSU_GPIO_0_DEVICE_ID
83#define XPAR_PSU_GPIO_0_DEVICE_ID 0
84#endif
85#ifndef XPAR_PSU_SPI_0_DEVICE_ID
86#define XPAR_PSU_SPI_0_DEVICE_ID 0
87#endif
88#ifndef XPAR_PSU_SPI_1_DEVICE_ID
89#define XPAR_PSU_SPI_1_DEVICE_ID 1
90#endif
91#ifndef XPAR_PSU_UART_0_DEVICE_ID
92#define XPAR_PSU_UART_0_DEVICE_ID 0
93#endif
94
95/* Versal PSV */
96#ifndef XPAR_XUARTPSV_0_DEVICE_ID
97#define XPAR_XUARTPSV_0_DEVICE_ID 0
98#endif
99
100/* AXI / PL (Microblaze) — both canonical (XPAR_<DRIVER>_<N>_DEVICE_ID)
101 * and instance-name (XPAR_<BLOCK_DESIGN_NAME>_DEVICE_ID) forms. */
102#ifndef XPAR_GPIO_0_DEVICE_ID
103#define XPAR_GPIO_0_DEVICE_ID 0
104#endif
105#ifndef XPAR_AXI_GPIO_DEVICE_ID
106#define XPAR_AXI_GPIO_DEVICE_ID 0
107#endif
108#ifndef XPAR_SPI_0_DEVICE_ID
109#define XPAR_SPI_0_DEVICE_ID 0
110#endif
111#ifndef XPAR_AXI_SPI_DEVICE_ID
112#define XPAR_AXI_SPI_DEVICE_ID 0
113#endif
114#ifndef XPAR_AXI_UART_DEVICE_ID
115#define XPAR_AXI_UART_DEVICE_ID 0
116#endif
117#ifndef XPAR_INTC_SINGLE_DEVICE_ID
118#define XPAR_INTC_SINGLE_DEVICE_ID 0
119#endif
120
121/* AXI Interrupt Controller renames: Vitis 2025+ changed the INTC array
122 * size macro and the interrupt ID naming convention. */
123#if !defined(XPAR_INTC_MAX_NUM_INTR_INPUTS) && defined(XPAR_XINTC_0_NUM_INTR_INPUTS)
124#define XPAR_INTC_MAX_NUM_INTR_INPUTS XPAR_XINTC_0_NUM_INTR_INPUTS
125#endif
126
127/* Interrupt ID renames: old XPAR_AXI_INTC_<periph>_INTERRUPT_INTR
128 * became XPAR_FABRIC_<periph>_INTR in Vitis 2025+. */
129#if !defined(XPAR_AXI_INTC_AXI_TIMER_INTERRUPT_INTR) && defined(XPAR_FABRIC_AXI_TIMER_INTR)
130#define XPAR_AXI_INTC_AXI_TIMER_INTERRUPT_INTR XPAR_FABRIC_AXI_TIMER_INTR
131#endif
132#if !defined(XPAR_AXI_INTC_AXI_UART_INTERRUPT_INTR) && defined(XPAR_FABRIC_AXI_UART_INTR)
133#define XPAR_AXI_INTC_AXI_UART_INTERRUPT_INTR XPAR_FABRIC_AXI_UART_INTR
134#endif
135
136/* SPI device ID and clock frequency renames: Vitis 2025+ uses XPAR_XSPIPS_*
137 * instead of the platform-specific XPAR_PS7_SPI_* / XPAR_PSU_SPI_* names,
138 * and removed _DEVICE_ID macros entirely.
139 * Define both device 0 and device 1 — xilinx_spi.c token-pastes the device
140 * index, so all instances the BSP provides must be covered. */
141#ifndef XPAR_XSPIPS_0_DEVICE_ID
142#define XPAR_XSPIPS_0_DEVICE_ID 0
143#endif
144#ifndef XPAR_XSPIPS_1_DEVICE_ID
145#define XPAR_XSPIPS_1_DEVICE_ID 1
146#endif
147#if !defined(XPAR_PS7_SPI_0_SPI_CLK_FREQ_HZ) && defined(XPAR_XSPIPS_0_SPI_CLK_FREQ_HZ)
148#define XPAR_PS7_SPI_0_SPI_CLK_FREQ_HZ XPAR_XSPIPS_0_SPI_CLK_FREQ_HZ
149#endif
150#if !defined(XPAR_PS7_SPI_1_SPI_CLK_FREQ_HZ) && defined(XPAR_XSPIPS_1_SPI_CLK_FREQ_HZ)
151#define XPAR_PS7_SPI_1_SPI_CLK_FREQ_HZ XPAR_XSPIPS_1_SPI_CLK_FREQ_HZ
152#endif
153#if !defined(XPAR_PSU_SPI_0_SPI_CLK_FREQ_HZ) && defined(XPAR_XSPIPS_0_SPI_CLK_FREQ_HZ)
154#define XPAR_PSU_SPI_0_SPI_CLK_FREQ_HZ XPAR_XSPIPS_0_SPI_CLK_FREQ_HZ
155#endif
156#if !defined(XPAR_PSU_SPI_1_SPI_CLK_FREQ_HZ) && defined(XPAR_XSPIPS_1_SPI_CLK_FREQ_HZ)
157#define XPAR_PSU_SPI_1_SPI_CLK_FREQ_HZ XPAR_XSPIPS_1_SPI_CLK_FREQ_HZ
158#endif
159
160#endif /* _XILINX_COMPAT_H_ */