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ad77681.h
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1/***************************************************************************/
40#ifndef SRC_AD77681_H_
41#define SRC_AD77681_H_
42
43#include "no_os_spi.h"
44#include <stdbool.h>
45
46/******************************************************************************/
47/********************** Macros and Constants Definitions **********************/
48/******************************************************************************/
49#define AD77681_REG_CHIP_TYPE 0x3
50#define AD77681_REG_PROD_ID_L 0x4
51#define AD77681_REG_PROD_ID_H 0x5
52#define AD77681_REG_CHIP_GRADE 0x6
53#define AD77681_REG_SCRATCH_PAD 0x0A
54#define AD77681_REG_VENDOR_L 0x0C
55#define AD77681_REG_VENDOR_H 0x0D
56#define AD77681_REG_INTERFACE_FORMAT 0x14
57#define AD77681_REG_POWER_CLOCK 0x15
58#define AD77681_REG_ANALOG 0x16
59#define AD77681_REG_ANALOG2 0x17
60#define AD77681_REG_CONVERSION 0x18
61#define AD77681_REG_DIGITAL_FILTER 0x19
62#define AD77681_REG_SINC3_DEC_RATE_MSB 0x1A
63#define AD77681_REG_SINC3_DEC_RATE_LSB 0x1B
64#define AD77681_REG_DUTY_CYCLE_RATIO 0x1C
65#define AD77681_REG_SYNC_RESET 0x1D
66#define AD77681_REG_GPIO_CONTROL 0x1E
67#define AD77681_REG_GPIO_WRITE 0x1F
68#define AD77681_REG_GPIO_READ 0x20
69#define AD77681_REG_OFFSET_HI 0x21
70#define AD77681_REG_OFFSET_MID 0x22
71#define AD77681_REG_OFFSET_LO 0x23
72#define AD77681_REG_GAIN_HI 0x24
73#define AD77681_REG_GAIN_MID 0x25
74#define AD77681_REG_GAIN_LO 0x26
75#define AD77681_REG_SPI_DIAG_ENABLE 0x28
76#define AD77681_REG_ADC_DIAG_ENABLE 0x29
77#define AD77681_REG_DIG_DIAG_ENABLE 0x2A
78#define AD77681_REG_ADC_DATA 0x2C
79#define AD77681_REG_MASTER_STATUS 0x2D
80#define AD77681_REG_SPI_DIAG_STATUS 0x2E
81#define AD77681_REG_ADC_DIAG_STATUS 0x2F
82#define AD77681_REG_DIG_DIAG_STATUS 0x30
83#define AD77681_REG_MCLK_COUNTER 0x31
84
85/* AD77681_REG_INTERFACE_FORMAT */
86#define AD77681_INTERFACE_CRC_EN_MSK (0x1 << 6)
87#define AD77681_INTERFACE_CRC_EN(x) (((x) & 0x1) << 6)
88#define AD77681_INTERFACE_CRC_TYPE_MSK (0x1 << 5)
89#define AD77681_INTERFACE_CRC_TYPE(x) (((x) & 0x1) << 5)
90#define AD77681_INTERFACE_STATUS_EN_MSK (0x1 << 4)
91#define AD77681_INTERFACE_STATUS_EN(x) (((x) & 0x1) << 4)
92#define AD77681_INTERFACE_CONVLEN_MSK (0x1 << 3)
93#define AD77681_INTERFACE_CONVLEN(x) (((x) & 0x1) << 3)
94#define AD77681_INTERFACE_RDY_EN_MSK (0x1 << 2)
95#define AD77681_INTERFACE_RDY_EN(x) (((x) & 0x1) << 3)
96#define AD77681_INTERFACE_CONT_READ_MSK (0x1 << 0)
97#define AD77681_INTERFACE_CONT_READ_EN(x) (((x) & 0x1) << 0)
98#define AD77681_REG_COEFF_CONTROL 0x32
99#define AD77681_REG_COEFF_DATA 0x33
100#define AD77681_REG_ACCESS_KEY 0x34
101
102/* AD77681_REG_SCRATCH_PAD*/
103#define AD77681_SCRATCHPAD_MSK (0xFF << 0)
104#define AD77681_SCRATCHPAD(x) (((x) & 0xFF) << 0)
105
106/* AD77681_REG_POWER_CLOCK */
107#define AD77681_POWER_CLK_PWRMODE_MSK 0x3
108#define AD77681_POWER_CLK_PWRMODE(x) (((x) & 0x3) << 0)
109#define AD77681_POWER_CLK_MOD_OUT_MSK (0x1 << 2)
110#define AD77681_POWER_CLK_MOD_OUT(x) (((x) & 0x1) << 2)
111#define AD77681_POWER_CLK_POWER_DOWN 0x08
112#define AD77681_POWER_CLK_MCLK_DIV_MSK (0x3 << 4)
113#define AD77681_POWER_CLK_MCLK_DIV(x) (((x) & 0x3) << 4)
114#define AD77681_POWER_CLK_CLOCK_SEL_MSK (0x3 << 6)
115#define AD77681_POWER_CLK_CLOCK_SEL(x) (((x) & 0x3) << 6)
116
117/* AD77681_CONVERSION_REG */
118#define AD77681_CONVERSION_DIAG_MUX_MSK (0xF << 4)
119#define AD77681_CONVERSION_DIAG_MUX_SEL(x) (((x) & 0xF) << 4)
120#define AD77681_CONVERSION_DIAG_SEL_MSK (0x1 << 3)
121#define AD77681_CONVERSION_DIAG_SEL(x) (((x) & 0x1) << 3)
122#define AD77681_CONVERSION_MODE_MSK (0x7 << 0)
123#define AD77681_CONVERSION_MODE(x) (((x) & 0x7) << 0)
124
125/* AD77681_REG_ANALOG */
126#define AD77681_ANALOG_REF_BUF_POS_MSK (0x3 << 6)
127#define AD77681_ANALOG_REF_BUF_POS(x) (((x) & 0x3) << 6)
128#define AD77681_ANALOG_REF_BUF_NEG_MSK (0x3 << 4)
129#define AD77681_ANALOG_REF_BUF_NEG(x) (((x) & 0x3) << 4)
130#define AD77681_ANALOG_AIN_BUF_POS_OFF_MSK (0x1 << 1)
131#define AD77681_ANALOG_AIN_BUF_POS_OFF(x) (((x) & 0x1) << 1)
132#define AD77681_ANALOG_AIN_BUF_NEG_OFF_MSK (0x1 << 0)
133#define AD77681_ANALOG_AIN_BUF_NEG_OFF(x) (((x) & 0x1) << 0)
134
135/* AD77681_REG_ANALOG2 */
136#define AD77681_ANALOG2_VCM_MSK (0x7 << 0)
137#define AD77681_ANALOG2_VCM(x) (((x) & 0x7) << 0)
138
139/* AD77681_REG_DIGITAL_FILTER */
140#define AD77681_DIGI_FILTER_60HZ_REJ_EN_MSK (0x1 << 7)
141#define AD77681_DIGI_FILTER_60HZ_REJ_EN(x) (((x) & 0x1) << 7)
142#define AD77681_DIGI_FILTER_FILTER_MSK (0x7 << 4)
143#define AD77681_DIGI_FILTER_FILTER(x) (((x) & 0x7) << 4)
144#define AD77681_DIGI_FILTER_DEC_RATE_MSK (0x7 << 0)
145#define AD77681_DIGI_FILTER_DEC_RATE(x) (((x) & 0x7) << 0)
146
147/* AD77681_REG_SINC3_DEC_RATE_MSB */
148#define AD77681_SINC3_DEC_RATE_MSB_MSK (0x0F << 0)
149#define AD77681_SINC3_DEC_RATE_MSB(x) (((x) & 0x0F) << 0)
150
151/* AD77681_REG_SINC3_DEC_RATE_LSB */
152#define AD77681_SINC3_DEC_RATE_LSB_MSK (0xFF << 0)
153#define AD77681_SINC3_DEC_RATE_LSB(x) (((x) & 0xFF) << 0)
154
155/* AD77681_REG_DUTY_CYCLE_RATIO */
156#define AD77681_DC_RATIO_IDLE_TIME_MSK (0xFF << 0)
157#define AD77681_DC_RATIO_IDLE_TIME(x) (((x) & 0xFF) << 0)
158
159/* AD77681_REG_SYNC_RESET */
160#define AD77681_SYNC_RST_SPI_STARTB_MSK (0x1 << 7)
161#define AD77681_SYNC_RST_SPI_STARTB(x) (((x) & 0x1) << 7)
162#define AD77681_SYNC_RST_SYNCOUT_EDGE_MSK (0x1 << 6)
163#define AD77681_SYNC_RST_SYNCOUT_EDGE(x) (((x) & 0x1) << 6)
164#define AD77681_SYNC_RST_GPIO_START_EN_MSK (0x1 << 3)
165#define AD77681_SYNC_RST_GPIO_START_EN(x) (((x) & 0x1) << 3)
166#define AD77681_SYNC_RST_SPI_RESET_MSK (0x3 << 0)
167#define AD77681_SYNC_RST_SPI_RESET(x) (((x) & 0x3) << 0)
168
169/* AD77681_REG_GPIO_CONTROL */
170#define AD77681_GPIO_CNTRL_UGPIO_EN_MSK (0x1 << 7)
171#define AD77681_GPIO_CNTRL_UGPIO_EN(x) (((x) & 0x1) << 7)
172#define AD77681_GPIO_CNTRL_GPIO2_OD_EN_MSK (0x1 << 6)
173#define AD77681_GPIO_CNTRL_GPIO2_OD_EN(x) (((x) & 0x1) << 6)
174#define AD77681_GPIO_CNTRL_GPIO1_OD_EN_MSK (0x1 << 5)
175#define AD77681_GPIO_CNTRL_GPIO1_OD_EN(x) (((x) & 0x1) << 5)
176#define AD77681_GPIO_CNTRL_GPIO0_OD_EN_MSK (0x1 << 4)
177#define AD77681_GPIO_CNTRL_GPIO0_OD_EN(x) (((x) & 0x1) << 4)
178#define AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN_MSK (0x7 << 4)
179#define AD77681_GPIO_CNTRL_ALL_GPIOS_OD_EN(x) (((x) & 0x7) << 4)
180#define AD77681_GPIO_CNTRL_GPIO3_OP_EN_MSK (0x1 << 3)
181#define AD77681_GPIO_CNTRL_GPIO3_OP_EN(x) (((x) & 0x1) << 3)
182#define AD77681_GPIO_CNTRL_GPIO2_OP_EN_MSK (0x1 << 2)
183#define AD77681_GPIO_CNTRL_GPIO2_OP_EN(x) (((x) & 0x1) << 2)
184#define AD77681_GPIO_CNTRL_GPIO1_OP_EN_MSK (0x1 << 1)
185#define AD77681_GPIO_CNTRL_GPIO1_OP_EN(x) (((x) & 0x1) << 1)
186#define AD77681_GPIO_CNTRL_GPIO0_OP_EN_MSK (0x1 << 0)
187#define AD77681_GPIO_CNTRL_GPIO0_OP_EN(x) (((x) & 0x1) << 0)
188#define AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN_MSK (0xF << 0)
189#define AD77681_GPIO_CNTRL_ALL_GPIOS_OP_EN(x) (((x) & 0xF) << 0)
190
191/* AD77681_REG_GPIO_WRITE */
192#define AD77681_GPIO_WRITE_3_MSK (0x1 << 3)
193#define AD77681_GPIO_WRITE_3(x) (((x) & 0x1) << 3)
194#define AD77681_GPIO_WRITE_2_MSK (0x1 << 2)
195#define AD77681_GPIO_WRITE_2(x) (((x) & 0x1) << 2)
196#define AD77681_GPIO_WRITE_1_MSK (0x1 << 1)
197#define AD77681_GPIO_WRITE_1(x) (((x) & 0x1) << 1)
198#define AD77681_GPIO_WRITE_0_MSK (0x1 << 0)
199#define AD77681_GPIO_WRITE_0(x) (((x) & 0x1) << 0)
200#define AD77681_GPIO_WRITE_ALL_MSK (0xF << 0)
201#define AD77681_GPIO_WRITE_ALL(x) (((x) & 0xF))
202
203/* AD77681_REG_GPIO_READ */
204#define AD77681_GPIO_READ_3_MSK (0x1 << 3)
205#define AD77681_GPIO_READ_2_MSK (0x1 << 2)
206#define AD77681_GPIO_READ_1_MSK (0x1 << 1)
207#define AD77681_GPIO_READ_0_MSK (0x1 << 0)
208#define AD77681_GPIO_READ_ALL_MSK (0xF << 0)
209
210/* AD77681_REG_OFFSET_HI */
211#define AD77681_OFFSET_HI_MSK (0xFF << 0)
212#define AD77681_OFFSET_HI(x) (((x) & 0xFF) << 0)
213
214/* AD77681_REG_OFFSET_MID */
215#define AD77681_OFFSET_MID_MSK (0xFF << 0)
216#define AD77681_OFFSET_MID(x) (((x) & 0xFF) << 0)
217
218/* AD77681_REG_OFFSET_LO */
219#define AD77681_OFFSET_LO_MSK (0xFF << 0)
220#define AD77681_OFFSET_LO(x) (((x) & 0xFF) << 0)
221
222/* AD77681_REG_GAIN_HI */
223#define AD77681_GAIN_HI_MSK (0xFF << 0)
224#define AD77681_GAIN_HI(x) (((x) & 0xFF) << 0)
225
226/* AD77681_REG_GAIN_MID */
227#define AD77681_GAIN_MID_MSK (0xFF << 0)
228#define AD77681_GAIN_MID(x) (((x) & 0xFF) << 0)
229
230/* AD77681_REG_GAIN_HI */
231#define AD77681_GAIN_LOW_MSK (0xFF << 0)
232#define AD77681_GAIN_LOW(x) (((x) & 0xFF) << 0)
233
234/* AD77681_REG_SPI_DIAG_ENABLE */
235#define AD77681_SPI_DIAG_ERR_SPI_IGNORE_MSK (0x1 << 4)
236#define AD77681_SPI_DIAG_ERR_SPI_IGNORE(x) (((x) & 0x1) << 4)
237#define AD77681_SPI_DIAG_ERR_SPI_CLK_CNT_MSK (0x1 << 3)
238#define AD77681_SPI_DIAG_ERR_SPI_CLK_CNT(x) (((x) & 0x1) << 3)
239#define AD77681_SPI_DIAG_ERR_SPI_RD_MSK (0x1 << 2)
240#define AD77681_SPI_DIAG_ERR_SPI_RD(x) (((x) & 0x1) << 2)
241#define AD77681_SPI_DIAG_ERR_SPI_WR_MSK (0x1 << 1)
242#define AD77681_SPI_DIAG_ERR_SPI_WR(x) (((x) & 0x1) << 1)
243
244/* AD77681_REG_ADC_DIAG_ENABLE */
245#define AD77681_ADC_DIAG_ERR_DLDO_PSM_MSK (0x1 << 5)
246#define AD77681_ADC_DIAG_ERR_DLDO_PSM(x) (((x) & 0x1) << 5)
247#define AD77681_ADC_DIAG_ERR_ALDO_PSM_MSK (0x1 << 4)
248#define AD77681_ADC_DIAG_ERR_ALDO_PSM(x) (((x) & 0x1) << 4)
249#define AD77681_ADC_DIAG_ERR_FILT_SAT_MSK (0x1 << 2)
250#define AD77681_ADC_DIAG_ERR_FILT_SAT(x) (((x) & 0x1) << 2)
251#define AD77681_ADC_DIAG_ERR_FILT_NOT_SET_MSK (0x1 << 1)
252#define AD77681_ADC_DIAG_ERR_FILT_NOT_SET(x) (((x) & 0x1) << 1)
253#define AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL_MSK (0x1 << 0)
254#define AD77681_ADC_DIAG_ERR_EXT_CLK_QUAL(x) (((x) & 0x1) << 0)
255
256/* AD77681_REG_DIG_DIAG_ENABLE */
257#define AD77681_DIG_DIAG_ERR_MEMMAP_CRC_MSK (0x1 << 4)
258#define AD77681_DIG_DIAG_ERR_MEMMAP_CRC(x) (((x) & 0x1) << 4)
259#define AD77681_DIG_DIAG_ERR_RAM_CRC_MSK (0x1 << 3)
260#define AD77681_DIG_DIAG_ERR_RAM_CRC(x) (((x) & 0x1) << 3)
261#define AD77681_DIG_DIAG_ERR_FUSE_CRC_MSK (0x1 << 2)
262#define AD77681_DIG_DIAG_ERR_FUSE_CRC(x) (((x) & 0x1) << 2)
263#define AD77681_DIG_DIAG_FREQ_COUNT_EN_MSK (0x1 << 0)
264#define AD77681_DIG_DIAG_FREQ_COUNT_EN(x) (((x) & 0x1) << 0)
265
266/* AD77681_REG_MASTER_STATUS */
267#define AD77681_MASTER_ERROR_MSK (0x1 << 7)
268#define AD77681_MASTER_ADC_ERROR_MSK (0x1 << 6)
269#define AD77681_MASTER_DIG_ERROR_MSK (0x1 << 5)
270#define AD77681_MASTER_DIG_ERR_EXT_CLK_MSK (0x1 << 4)
271#define AD77681_MASTER_FILT_SAT_MSK (0x1 << 3)
272#define AD77681_MASTER_FILT_NOT_SET_MSK (0x1 << 2)
273#define AD77681_MASTER_SPI_ERROR_MSK (0x1 << 1)
274#define AD77681_MASTER_POR_FLAG_MSK (0x1 << 0)
275
276/* AD77681_REG_SPI_DIAG_STATUS */
277#define AD77681_SPI_IGNORE_ERROR_MSK (0x1 << 4)
278#define AD77681_SPI_IGNORE_ERROR_CLR(x) (((x) & 0x1) << 4)
279#define AD77681_SPI_CLK_CNT_ERROR_MSK (0x1 << 3)
280#define AD77681_SPI_READ_ERROR_MSK (0x1 << 2)
281#define AD77681_SPI_READ_ERROR_CLR(x) (((x) & 0x1) << 2)
282#define AD77681_SPI_WRITE_ERROR_MSK (0x1 << 1)
283#define AD77681_SPI_WRITE_ERROR_CLR(x) (((x) & 0x1) << 1)
284#define AD77681_SPI_CRC_ERROR_MSK (0x1 << 0)
285#define AD77681_SPI_CRC_ERROR_CLR(x) (((x) & 0x1) << 0)
286
287/* AD77681_REG_ADC_DIAG_STATUS */
288#define AD77681_ADC_DLDO_PSM_ERROR_MSK (0x1 << 5)
289#define AD77681_ADC_ALDO_PSM_ERROR_MSK (0x1 << 4)
290#define AD77681_ADC_REF_DET_ERROR_MSK (0x1 << 3)
291#define AD77681_ADC_FILT_SAT_MSK (0x1 << 2)
292#define AD77681_ADC_FILT_NOT_SET_MSK (0x1 << 1)
293#define AD77681_ADC_DIG_ERR_EXT_CLK_MSK (0x1 << 0)
294
295/* AD77681_REG_DIG_DIAG_STATUS */
296#define AD77681_DIG_MEMMAP_CRC_ERROR_MSK (0x1 << 4)
297#define AD77681_DIG_RAM_CRC_ERROR_MSK (0x1 << 3)
298#define AD77681_DIG_FUS_CRC_ERROR_MSK (0x1 << 2)
299
300/* AD77681_REG_MCLK_COUNTER */
301#define AD77681_MCLK_COUNTER_MSK (0xFF << 0)
302#define AD77681_MCLK_COUNTER(x) (((x) & 0xFF) << 0)
303
304/* AD77681_REG_COEFF_CONTROL */
305#define AD77681_COEF_CONTROL_COEFFACCESSEN_MSK (0x1 << 7)
306#define AD77681_COEF_CONTROL_COEFFACCESSEN(x) (((x) & 0x1) << 7)
307#define AD77681_COEF_CONTROL_COEFFWRITEEN_MSK (0x1 << 6)
308#define AD77681_COEF_CONTROL_COEFFWRITEEN(x) (((x) & 0x1) << 6)
309#define AD77681_COEF_CONTROL_COEFFADDR_MSK (0x3F << 5)
310#define AD77681_COEF_CONTROL_COEFFADDR(x) (((x) & 0x3F) << 5)
311
312/* AD77681_REG_COEFF_DATA */
313#define AD77681_COEFF_DATA_USERCOEFFEN_MSK (0x1 << 23)
314#define AD77681_COEFF_DATA_USERCOEFFEN(x) (((x) & 0x1) << 23)
315#define AD77681_COEFF_DATA_COEFFDATA_MSK (0x7FFFFF << 22)
316#define AD77681_COEFF_DATA_COEFFDATA(x) (((x) & 0x7FFFFF) << 22)
317
318/* AD77681_REG_ACCESS_KEY */
319#define AD77681_ACCESS_KEY_MSK (0xFF << 0)
320#define AD77681_ACCESS_KEY(x) (((x) & 0xFF) << 0)
321#define AD77681_ACCESS_KEY_CHECK_MSK (0x1 << 0)
322
323#define AD77681_REG_READ(x) ( (1 << 6) | (x & 0xFF) ) // Read from register x
324#define AD77681_REG_WRITE(x) ( (~(1 << 6)) & (x & 0xFF) ) // Write to register x
325
326/* 8-bits wide checksum generated using the polynomial */
327#define AD77681_CRC8_POLY 0x07 // x^8 + x^2 + x^1 + x^0
328
329/* Initial CRC for continuous read mode */
330#define INITIAL_CRC_CRC8 0x03
331#define INITIAL_CRC_XOR 0x6C
332#define INITIAL_CRC 0x00
333
334#define CRC_DEBUG
335
336/* AD7768-1 */
337/* A special key for exit the contiuous read mode, taken from the AD7768-1 datasheet */
338#define EXIT_CONT_READ 0x6C
339/* Bit resolution of the AD7768-1 */
340#define AD7768_N_BITS 24
341/* Full scale of the AD7768-1 = 2^24 = 16777216 */
342#define AD7768_FULL_SCALE (1 << AD7768_N_BITS)
343/* Half scale of the AD7768-1 = 2^23 = 8388608 */
344#define AD7768_HALF_SCALE (1 << (AD7768_N_BITS - 1))
345
346#define ENABLE 1
347#define DISABLE 0
348
349/*****************************************************************************/
350/*************************** Types Declarations *******************************/
351/******************************************************************************/
357
364
372
377
382
389
395
396/* Filter tye FIR, SINC3, SINC5 */
404
405/* Dectimation ratios for SINC5 and FIR */
414
415/* Sleep / Power up */
420
421/* Reset option */
426/* AIN- precharge */
431
432/* AIN+ precharge */
437
438/* REF- buffer */
444
445/* REF+ buffer */
451
452/* VCM output voltage */
463
464/* Global GPIO enable/disable */
469
470/* ADCs GPIO numbering */
478
483
484/* Continuous ADC read */
489
490/* ADC data read mode */
495
496/* ADC data structure */
497struct adc_data {
498 bool finish;
499 uint16_t count;
500 uint16_t samples;
501 uint32_t raw_data[4096];
502};
503/* ADC status registers structure */
528
554
580
581/******************************************************************************/
582/************************ Functions Declarations ******************************/
583/******************************************************************************/
584uint8_t ad77681_compute_crc8(uint8_t *data,
585 uint8_t data_size,
586 uint8_t init_val);
587uint8_t ad77681_compute_xor(uint8_t *data,
588 uint8_t data_size,
589 uint8_t init_val);
590int32_t ad77681_setup(struct ad77681_dev **device,
591 struct ad77681_init_param init_param,
592 struct ad77681_status_registers **status);
593int32_t ad77681_spi_reg_read(struct ad77681_dev *dev,
594 uint8_t reg_addr,
595 uint8_t *reg_data);
596int32_t ad77681_spi_read_mask(struct ad77681_dev *dev,
597 uint8_t reg_addr,
598 uint8_t mask,
599 uint8_t *data);
600int32_t ad77681_spi_reg_write(struct ad77681_dev *dev,
601 uint8_t reg_addr,
602 uint8_t reg_data);
603int32_t ad77681_spi_write_mask(struct ad77681_dev *dev,
604 uint8_t reg_addr,
605 uint8_t mask,
606 uint8_t data);
607int32_t ad77681_set_power_mode(struct ad77681_dev *dev,
608 enum ad77681_power_mode mode);
609int32_t ad77681_set_mclk_div(struct ad77681_dev *dev,
610 enum ad77681_mclk_div clk_div);
611int32_t ad77681_spi_read_adc_data(struct ad77681_dev *dev,
612 uint8_t *adc_data,
613 enum ad77681_data_read_mode mode);
614int32_t ad77681_set_conv_mode(struct ad77681_dev *dev,
615 enum ad77681_conv_mode conv_mode,
616 enum ad77681_conv_diag_mux diag_mux_sel,
617 bool conv_diag_sel);
618int32_t ad77681_set_convlen(struct ad77681_dev *dev,
619 enum ad77681_conv_len conv_len);
620int32_t ad77681_soft_reset(struct ad77681_dev *dev);
621int32_t ad77681_initiate_sync(struct ad77681_dev *dev);
622int32_t ad77681_programmable_filter(struct ad77681_dev *dev,
623 const float *coeffs,
624 uint8_t num_coeffs);
625int32_t ad77681_gpio_read(struct ad77681_dev *dev,
626 uint8_t *value,
627 enum ad77681_gpios gpio_number);
628int32_t ad77681_apply_offset(struct ad77681_dev *dev,
629 uint32_t value);
630int32_t ad77681_apply_gain(struct ad77681_dev *dev,
631 uint32_t value);
632int32_t ad77681_set_crc_sel(struct ad77681_dev *dev,
633 enum ad77681_crc_sel crc_sel);
634int32_t ad77681_gpio_open_drain(struct ad77681_dev *dev,
635 enum ad77681_gpios gpio_number,
636 enum ad77681_gpio_output_type output_type);
637int32_t ad77681_set_continuos_read(struct ad77681_dev *dev,
638 enum ad77681_continuous_read continuous_enable);
639int32_t ad77681_clear_error_flags(struct ad77681_dev *dev);
640int32_t ad77681_data_to_voltage(struct ad77681_dev *dev,
641 uint32_t *raw_code,
642 double *voltage);
643int32_t ad77681_CRC_status_handling(struct ad77681_dev *dev,
644 uint16_t *data_buffer);
645int32_t ad77681_set_AINn_buffer(struct ad77681_dev *dev,
646 enum ad77681_AINn_precharge AINn);
647int32_t ad77681_set_AINp_buffer(struct ad77681_dev *dev,
648 enum ad77681_AINp_precharge AINp);
649int32_t ad77681_set_REFn_buffer(struct ad77681_dev *dev,
650 enum ad77681_REFn_buffer REFn);
651int32_t ad77681_set_REFp_buffer(struct ad77681_dev *dev,
652 enum ad77681_REFp_buffer REFp);
653int32_t ad77681_set_filter_type(struct ad77681_dev *dev,
654 enum ad77681_sinc5_fir_decimate decimate,
655 enum ad77681_filter_type filter,
656 uint16_t sinc3_osr);
657int32_t ad77681_set_50HZ_rejection(struct ad77681_dev *dev,
658 uint8_t enable);
659int32_t ad77681_power_down(struct ad77681_dev *dev,
660 enum ad77681_sleep_wake sleep_wake);
661int32_t ad77681_set_status_bit(struct ad77681_dev *dev,
662 bool status_bit);
663int32_t ad77681_set_VCM_output(struct ad77681_dev *dev,
664 enum ad77681_VCM_out VCM_out);
665int32_t ad77681_gpio_write(struct ad77681_dev *dev,
666 uint8_t value,
667 enum ad77681_gpios gpio_number);
668int32_t ad77681_gpio_inout(struct ad77681_dev *dev,
669 uint8_t direction,
670 enum ad77681_gpios gpio_number);
671int32_t ad77681_global_gpio(struct ad77681_dev *devices,
672 enum ad77681_gobal_gpio_enable gpio_enable);
673int32_t ad77681_scratchpad(struct ad77681_dev *dev,
674 uint8_t *sequence);
675int32_t ad77681_error_flags_enabe(struct ad77681_dev *dev);
676int32_t ad77681_update_sample_rate(struct ad77681_dev *dev);
677int32_t ad77681_SINC3_ODR(struct ad77681_dev *dev,
678 uint16_t *sinc3_dec_reg,
679 float sinc3_odr);
680int32_t ad77681_status(struct ad77681_dev *dev,
681 struct ad77681_status_registers *status);
682#endif /* SRC_AD77681_H_ */
struct ad5933_dev * device
Definition main.c:91
ad77681_conv_mode
Definition ad77681.h:365
@ AD77681_CONV_STANDBY
Definition ad77681.h:370
@ AD77681_CONV_CONTINUOUS
Definition ad77681.h:366
@ AD77681_CONV_SINGLE
Definition ad77681.h:368
@ AD77681_CONV_ONE_SHOT
Definition ad77681.h:367
@ AD77681_CONV_PERIODIC
Definition ad77681.h:369
int32_t ad77681_apply_gain(struct ad77681_dev *dev, uint32_t value)
Definition ad77681.c:1110
ad77681_rdy_dout
Definition ad77681.h:378
@ AD77681_RDY_DOUT_DIS
Definition ad77681.h:380
@ AD77681_RDY_DOUT_EN
Definition ad77681.h:379
ad77681_AINp_precharge
Definition ad77681.h:433
@ AD77681_AINp_DISABLED
Definition ad77681.h:435
@ AD77681_AINp_ENABLED
Definition ad77681.h:434
int32_t ad77681_gpio_write(struct ad77681_dev *dev, uint8_t value, enum ad77681_gpios gpio_number)
Definition ad77681.c:1376
int32_t ad77681_error_flags_enabe(struct ad77681_dev *dev)
Definition ad77681.c:1619
ad77681_power_mode
Definition ad77681.h:352
@ AD77681_ECO
Definition ad77681.h:353
@ AD77681_MEDIAN
Definition ad77681.h:354
@ AD77681_FAST
Definition ad77681.h:355
ad77681_REFp_buffer
Definition ad77681.h:446
@ AD77681_BUFp_FULL_BUFFER_ON
Definition ad77681.h:449
@ AD77681_BUFp_ENABLED
Definition ad77681.h:447
@ AD77681_BUFp_DISABLED
Definition ad77681.h:448
int32_t ad77681_data_to_voltage(struct ad77681_dev *dev, uint32_t *raw_code, double *voltage)
Definition ad77681.c:411
ad7761_reset_option
Definition ad77681.h:422
@ AD77681_HARD_RESET
Definition ad77681.h:424
@ AD77681_SOFT_RESET
Definition ad77681.h:423
int32_t ad77681_set_mclk_div(struct ad77681_dev *dev, enum ad77681_mclk_div clk_div)
Definition ad77681.c:588
int32_t ad77681_SINC3_ODR(struct ad77681_dev *dev, uint16_t *sinc3_dec_reg, float sinc3_odr)
Definition ad77681.c:515
int32_t ad77681_global_gpio(struct ad77681_dev *devices, enum ad77681_gobal_gpio_enable gpio_enable)
Definition ad77681.c:1488
int32_t ad77681_set_power_mode(struct ad77681_dev *dev, enum ad77681_power_mode mode)
Definition ad77681.c:562
int32_t ad77681_set_continuos_read(struct ad77681_dev *dev, enum ad77681_continuous_read continuous_enable)
Definition ad77681.c:843
int32_t ad77681_gpio_read(struct ad77681_dev *dev, uint8_t *value, enum ad77681_gpios gpio_number)
Definition ad77681.c:1317
ad77681_REFn_buffer
Definition ad77681.h:439
@ AD77681_BUFn_DISABLED
Definition ad77681.h:441
@ AD77681_BUFn_ENABLED
Definition ad77681.h:440
@ AD77681_BUFn_FULL_BUFFER_ON
Definition ad77681.h:442
int32_t ad77681_status(struct ad77681_dev *dev, struct ad77681_status_registers *status)
Definition ad77681.c:1703
int32_t ad77681_setup(struct ad77681_dev **device, struct ad77681_init_param init_param, struct ad77681_status_registers **status)
Definition ad77681.c:1751
ad77681_gpios
Definition ad77681.h:471
@ AD77681_GPIO2
Definition ad77681.h:474
@ AD77681_GPIO1
Definition ad77681.h:473
@ AD77681_GPIO3
Definition ad77681.h:475
@ AD77681_ALL_GPIOS
Definition ad77681.h:476
@ AD77681_GPIO0
Definition ad77681.h:472
ad77681_sleep_wake
Definition ad77681.h:416
@ AD77681_SLEEP
Definition ad77681.h:417
@ AD77681_WAKE
Definition ad77681.h:418
int32_t ad77681_set_crc_sel(struct ad77681_dev *dev, enum ad77681_crc_sel crc_sel)
Definition ad77681.c:977
ad77681_conv_diag_mux
Definition ad77681.h:383
@ AD77681_TEMP_SENSOR
Definition ad77681.h:384
@ AD77681_NEGATIVE_FS
Definition ad77681.h:387
@ AD77681_AIN_SHORT
Definition ad77681.h:385
@ AD77681_POSITIVE_FS
Definition ad77681.h:386
int32_t ad77681_set_AINp_buffer(struct ad77681_dev *dev, enum ad77681_AINp_precharge AINp)
Definition ad77681.c:666
ad77681_AINn_precharge
Definition ad77681.h:427
@ AD77681_AINn_ENABLED
Definition ad77681.h:428
@ AD77681_AINn_DISABLED
Definition ad77681.h:429
int32_t ad77681_spi_reg_write(struct ad77681_dev *dev, uint8_t reg_addr, uint8_t reg_data)
Definition ad77681.c:162
ad77681_gobal_gpio_enable
Definition ad77681.h:465
@ AD77681_GLOBAL_GPIO_ENABLE
Definition ad77681.h:466
@ AD77681_GLOBAL_GPIO_DISABLE
Definition ad77681.h:467
ad77681_filter_type
Definition ad77681.h:397
@ AD77681_FIR
Definition ad77681.h:402
@ AD77681_SINC5_DECx8
Definition ad77681.h:399
@ AD77681_SINC3
Definition ad77681.h:401
@ AD77681_SINC5
Definition ad77681.h:398
@ AD77681_SINC5_DECx16
Definition ad77681.h:400
int32_t ad77681_apply_offset(struct ad77681_dev *dev, uint32_t value)
Definition ad77681.c:1076
ad77681_mclk_div
Definition ad77681.h:358
@ AD77681_MCLK_DIV_4
Definition ad77681.h:361
@ AD77681_MCLK_DIV_8
Definition ad77681.h:360
@ AD77681_MCLK_DIV_2
Definition ad77681.h:362
@ AD77681_MCLK_DIV_16
Definition ad77681.h:359
int32_t ad77681_soft_reset(struct ad77681_dev *dev)
Definition ad77681.c:1039
uint8_t ad77681_compute_crc8(uint8_t *data, uint8_t data_size, uint8_t init_val)
Definition ad77681.c:61
int32_t ad77681_gpio_open_drain(struct ad77681_dev *dev, enum ad77681_gpios gpio_number, enum ad77681_gpio_output_type output_type)
Definition ad77681.c:1543
int32_t ad77681_gpio_inout(struct ad77681_dev *dev, uint8_t direction, enum ad77681_gpios gpio_number)
Definition ad77681.c:1435
ad77681_sinc5_fir_decimate
Definition ad77681.h:406
@ AD77681_SINC5_FIR_DECx64
Definition ad77681.h:408
@ AD77681_SINC5_FIR_DECx1024
Definition ad77681.h:412
@ AD77681_SINC5_FIR_DECx512
Definition ad77681.h:411
@ AD77681_SINC5_FIR_DECx32
Definition ad77681.h:407
@ AD77681_SINC5_FIR_DECx128
Definition ad77681.h:409
@ AD77681_SINC5_FIR_DECx256
Definition ad77681.h:410
int32_t ad77681_scratchpad(struct ad77681_dev *dev, uint8_t *sequence)
Definition ad77681.c:1505
ad77681_gpio_output_type
Definition ad77681.h:479
@ AD77681_GPIO_OPEN_DRAIN
Definition ad77681.h:481
@ AD77681_GPIO_STRONG_DRIVER
Definition ad77681.h:480
int32_t ad77681_spi_reg_read(struct ad77681_dev *dev, uint8_t reg_addr, uint8_t *reg_data)
Definition ad77681.c:112
int32_t ad77681_initiate_sync(struct ad77681_dev *dev)
Definition ad77681.c:1062
uint8_t ad77681_compute_xor(uint8_t *data, uint8_t data_size, uint8_t init_val)
Definition ad77681.c:89
int32_t ad77681_set_VCM_output(struct ad77681_dev *dev, enum ad77681_VCM_out VCM_out)
Definition ad77681.c:618
int32_t ad77681_set_AINn_buffer(struct ad77681_dev *dev, enum ad77681_AINn_precharge AINn)
Definition ad77681.c:642
int32_t ad77681_programmable_filter(struct ad77681_dev *dev, const float *coeffs, uint8_t num_coeffs)
Definition ad77681.c:1145
int32_t ad77681_power_down(struct ad77681_dev *dev, enum ad77681_sleep_wake sleep_wake)
Definition ad77681.c:871
int32_t ad77681_spi_read_adc_data(struct ad77681_dev *dev, uint8_t *adc_data, enum ad77681_data_read_mode mode)
Definition ad77681.c:279
int32_t ad77681_spi_read_mask(struct ad77681_dev *dev, uint8_t reg_addr, uint8_t mask, uint8_t *data)
Definition ad77681.c:188
ad77681_continuous_read
Definition ad77681.h:485
@ AD77681_CONTINUOUS_READ_ENABLE
Definition ad77681.h:486
@ AD77681_CONTINUOUS_READ_DISABLE
Definition ad77681.h:487
ad77681_VCM_out
Definition ad77681.h:453
@ AD77681_VCM_1_65V
Definition ad77681.h:458
@ AD77681_VCM_OFF
Definition ad77681.h:461
@ AD77681_VCM_1_9V
Definition ad77681.h:457
@ AD77681_VCM_2_5V
Definition ad77681.h:455
@ AD77681_VCM_HALF_VCC
Definition ad77681.h:454
@ AD77681_VCM_0_9V
Definition ad77681.h:460
@ AD77681_VCM_1_1V
Definition ad77681.h:459
@ AD77681_VCM_2_05V
Definition ad77681.h:456
int32_t ad77681_CRC_status_handling(struct ad77681_dev *dev, uint16_t *data_buffer)
Definition ad77681.c:337
ad77681_data_read_mode
Definition ad77681.h:491
@ AD77681_CONTINUOUS_DATA_READ
Definition ad77681.h:493
@ AD77681_REGISTER_DATA_READ
Definition ad77681.h:492
int32_t ad77681_set_REFp_buffer(struct ad77681_dev *dev, enum ad77681_REFp_buffer REFp)
Definition ad77681.c:716
int32_t ad77681_clear_error_flags(struct ad77681_dev *dev)
Definition ad77681.c:1586
int32_t ad77681_set_REFn_buffer(struct ad77681_dev *dev, enum ad77681_REFn_buffer REFn)
Definition ad77681.c:691
int32_t ad77681_set_conv_mode(struct ad77681_dev *dev, enum ad77681_conv_mode conv_mode, enum ad77681_conv_diag_mux diag_mux_sel, bool conv_diag_sel)
Definition ad77681.c:910
int32_t ad77681_set_50HZ_rejection(struct ad77681_dev *dev, uint8_t enable)
Definition ad77681.c:822
int32_t ad77681_set_convlen(struct ad77681_dev *dev, enum ad77681_conv_len conv_len)
Definition ad77681.c:949
ad77681_conv_len
Definition ad77681.h:373
@ AD77681_CONV_16BIT
Definition ad77681.h:375
@ AD77681_CONV_24BIT
Definition ad77681.h:374
int32_t ad77681_update_sample_rate(struct ad77681_dev *dev)
Definition ad77681.c:434
int32_t ad77681_spi_write_mask(struct ad77681_dev *dev, uint8_t reg_addr, uint8_t mask, uint8_t data)
Definition ad77681.c:210
int32_t ad77681_set_filter_type(struct ad77681_dev *dev, enum ad77681_sinc5_fir_decimate decimate, enum ad77681_filter_type filter, uint16_t sinc3_osr)
Definition ad77681.c:755
int32_t ad77681_set_status_bit(struct ad77681_dev *dev, bool status_bit)
Definition ad77681.c:1015
ad77681_crc_sel
Definition ad77681.h:390
@ AD77681_XOR
Definition ad77681.h:392
@ AD77681_CRC
Definition ad77681.h:391
@ AD77681_NO_CRC
Definition ad77681.h:393
Definition ad77681.h:529
bool conv_diag_sel
Definition ad77681.h:537
enum ad77681_VCM_out VCM_out
Definition ad77681.h:541
enum ad77681_AINp_precharge AINp
Definition ad77681.h:543
uint8_t status_bit
Definition ad77681.h:540
enum ad77681_conv_mode conv_mode
Definition ad77681.h:535
enum ad77681_conv_diag_mux diag_mux_sel
Definition ad77681.h:536
struct no_os_spi_desc * spi_desc
Definition ad77681.h:531
enum ad77681_REFp_buffer REFp
Definition ad77681.h:545
uint16_t vref
Definition ad77681.h:549
uint16_t mclk
Definition ad77681.h:550
enum ad77681_AINn_precharge AINn
Definition ad77681.h:542
enum ad77681_sinc5_fir_decimate decimate
Definition ad77681.h:547
uint16_t sinc3_osr
Definition ad77681.h:548
enum ad77681_mclk_div mclk_div
Definition ad77681.h:534
enum ad77681_filter_type filter
Definition ad77681.h:546
uint8_t data_frame_byte
Definition ad77681.h:552
uint32_t sample_rate
Definition ad77681.h:551
enum ad77681_REFn_buffer REFn
Definition ad77681.h:544
enum ad77681_power_mode power_mode
Definition ad77681.h:533
enum ad77681_crc_sel crc_sel
Definition ad77681.h:539
enum ad77681_conv_len conv_len
Definition ad77681.h:538
Definition ad77681.h:555
enum ad77681_filter_type filter
Definition ad77681.h:572
uint16_t mclk
Definition ad77681.h:576
enum ad77681_REFn_buffer REFn
Definition ad77681.h:570
struct no_os_spi_init_param spi_eng_dev_init
Definition ad77681.h:557
enum ad77681_sinc5_fir_decimate decimate
Definition ad77681.h:573
uint16_t sinc3_osr
Definition ad77681.h:574
enum ad77681_conv_diag_mux diag_mux_sel
Definition ad77681.h:562
enum ad77681_conv_len conv_len
Definition ad77681.h:564
enum ad77681_crc_sel crc_sel
Definition ad77681.h:565
enum ad77681_REFp_buffer REFp
Definition ad77681.h:571
enum ad77681_mclk_div mclk_div
Definition ad77681.h:560
bool conv_diag_sel
Definition ad77681.h:563
uint32_t sample_rate
Definition ad77681.h:577
uint16_t vref
Definition ad77681.h:575
enum ad77681_power_mode power_mode
Definition ad77681.h:559
enum ad77681_conv_mode conv_mode
Definition ad77681.h:561
enum ad77681_AINn_precharge AINn
Definition ad77681.h:568
enum ad77681_VCM_out VCM_out
Definition ad77681.h:567
uint8_t data_frame_byte
Definition ad77681.h:578
uint8_t status_bit
Definition ad77681.h:566
enum ad77681_AINp_precharge AINp
Definition ad77681.h:569
Definition ad77681.h:504
bool por_flag
Definition ad77681.h:512
bool dig_error
Definition ad77681.h:507
bool spi_ignore
Definition ad77681.h:513
bool adc_error
Definition ad77681.h:506
bool ram_crc_error
Definition ad77681.h:525
bool adc_filt_saturated
Definition ad77681.h:509
bool filt_not_set_error
Definition ad77681.h:522
bool spi_crc_error
Definition ad77681.h:517
bool dldo_psm_error
Definition ad77681.h:518
bool spi_write_error
Definition ad77681.h:516
bool filt_sat_error
Definition ad77681.h:521
bool adc_err_ext_clk_qual
Definition ad77681.h:508
bool adc_filt_not_settled
Definition ad77681.h:510
bool aldo_psm_error
Definition ad77681.h:519
bool master_error
Definition ad77681.h:505
bool spi_clock_count
Definition ad77681.h:514
bool spi_read_error
Definition ad77681.h:515
bool memoy_map_crc_error
Definition ad77681.h:524
bool fuse_crc_error
Definition ad77681.h:526
bool ref_det_error
Definition ad77681.h:520
bool spi_error
Definition ad77681.h:511
bool ext_clk_qual_error
Definition ad77681.h:523
Definition ad77681.h:497
uint16_t samples
Definition ad77681.h:500
uint16_t count
Definition ad77681.h:499
bool finish
Definition ad77681.h:498
uint32_t raw_data[4096]
Definition ad77681.h:501