precision-converters-firmware
sdp_k1_sdram.h
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1 /***************************************************************************/
13 #ifndef __SDPK1_SDRAM_H
14 #define __SDPK1_SDRAM_H
15 
16 #if defined (TARGET_SDP_K1)
17 
18 #ifdef __cplusplus
19  extern "C" {
20 #endif
21 
22 /******************************************************************************/
23 /***************************** Include Files **********************************/
24 /******************************************************************************/
25 
26 #include "stm32f4xx_hal.h"
27 
28 /******************************************************************************/
29 /********************** Macros and Constants Definition ***********************/
30 /******************************************************************************/
31 
35 #define SDRAM_OK ((uint8_t)0x00)
36 #define SDRAM_ERROR ((uint8_t)0x01)
37 
38 #define SDRAM_DEVICE_ADDR ((uint32_t)0xC0000000)
39 #define SDRAM_DEVICE_SIZE ((uint32_t)0x1000000) /* SDRAM device size in MBytes */
40 
41 /* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_8 */
42 /* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16 */
43 #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_32
44 
45 /* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2 */ /* Works only with 3.3 logic level */
46 #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 /* Works with both 1.8/3.3v logic level */
47 
48 #define REFRESH_COUNT ((uint32_t)0x0569) /* SDRAM refresh counter (90Mhz SD clock) */
49 
50 #define SDRAM_TIMEOUT ((uint32_t)0xFFFF)
51 
52 /* DMA definitions for SDRAM DMA transfer */
53 #define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
54 #define __DMAx_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
55 #define SDRAM_DMAx_CHANNEL DMA_CHANNEL_0
56 #define SDRAM_DMAx_STREAM DMA2_Stream4
57 #define SDRAM_DMAx_IRQn DMA2_Stream4_IRQn
58 #define BSP_SDRAM_DMA_IRQHandler DMA2_Stream4_IRQHandler
59 
60 /* SDRAM register defines */
61 #define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
62 #define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
63 #define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
64 #define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
65 #define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
66 #define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
67 #define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
68 #define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
69 #define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
70 #define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
71 #define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
72 
73 /* SDP SDRAM Pin defines */
74 #define SDRAM_A0 GPIO_PIN_0
75 #define SDRAM_A1 GPIO_PIN_1
76 #define SDRAM_A2 GPIO_PIN_2
77 #define SDRAM_A3 GPIO_PIN_3
78 #define SDRAM_A4 GPIO_PIN_4
79 #define SDRAM_A5 GPIO_PIN_5
80 #define SDRAM_A6 GPIO_PIN_12
81 #define SDRAM_A7 GPIO_PIN_13
82 #define SDRAM_A8 GPIO_PIN_14
83 #define SDRAM_A9 GPIO_PIN_15
84 #define SDRAM_A10 GPIO_PIN_0
85 #define SDRAM_A11 GPIO_PIN_1
86 #define SDRAM_A12 GPIO_PIN_2
87 #define SDRAM_A13 GPIO_PIN_3
88 #define SDRAM_A14 GPIO_PIN_4
89 #define SDRAM_A15 GPIO_PIN_5
90 #define SDRAM_D0 GPIO_PIN_14
91 #define SDRAM_D1 GPIO_PIN_15
92 #define SDRAM_D2 GPIO_PIN_0
93 #define SDRAM_D3 GPIO_PIN_1
94 #define SDRAM_D4 GPIO_PIN_7
95 #define SDRAM_D5 GPIO_PIN_8
96 #define SDRAM_D6 GPIO_PIN_9
97 #define SDRAM_D7 GPIO_PIN_10
98 #define SDRAM_D8 GPIO_PIN_11
99 #define SDRAM_D9 GPIO_PIN_12
100 #define SDRAM_D10 GPIO_PIN_13
101 #define SDRAM_D11 GPIO_PIN_14
102 #define SDRAM_D12 GPIO_PIN_15
103 #define SDRAM_D13 GPIO_PIN_8
104 #define SDRAM_D14 GPIO_PIN_9
105 #define SDRAM_D15 GPIO_PIN_10
106 #define SDRAM_D16 GPIO_PIN_8
107 #define SDRAM_D17 GPIO_PIN_9
108 #define SDRAM_D18 GPIO_PIN_10
109 #define SDRAM_D19 GPIO_PIN_11
110 #define SDRAM_D20 GPIO_PIN_12
111 #define SDRAM_D21 GPIO_PIN_13
112 #define SDRAM_D22 GPIO_PIN_14
113 #define SDRAM_D23 GPIO_PIN_15
114 #define SDRAM_D24 GPIO_PIN_0
115 #define SDRAM_D25 GPIO_PIN_1
116 #define SDRAM_D26 GPIO_PIN_2
117 #define SDRAM_D27 GPIO_PIN_3
118 #define SDRAM_D28 GPIO_PIN_6
119 #define SDRAM_D29 GPIO_PIN_7
120 #define SDRAM_D30 GPIO_PIN_9
121 #define SDRAM_D31 GPIO_PIN_10
122 #define SDRAM_NBL0 GPIO_PIN_0
123 #define SDRAM_NBL1 GPIO_PIN_1
124 #define SDRAM_NBL2 GPIO_PIN_4
125 #define SDRAM_NBL3 GPIO_PIN_5
126 #define SDRAM_SDCLK GPIO_PIN_8
127 #define SDRAM_N_CAS GPIO_PIN_15
128 #define SDRAM_N_RAS GPIO_PIN_11
129 #define SDRAM_SDCKE0 GPIO_PIN_2
130 #define SDRAM_SDNE0 GPIO_PIN_3
131 #define SDRAM_N_WE GPIO_PIN_5
132 
133 /******************************************************************************/
134 /************************ Public Declarations *********************************/
135 /******************************************************************************/
136 
137 uint8_t SDP_SDRAM_Init(void);
138 uint8_t SDP_SDRAM_DeInit(void);
139 void SDP_SDRAM_Initialization_sequence(uint32_t RefreshCount);
140 uint8_t SDP_SDRAM_ReadData_8b(uint32_t pAddress, uint8_t *pData, uint32_t dataSize);
141 uint8_t SDP_SDRAM_ReadData_16b(uint32_t pAddress, uint16_t *pData, uint32_t dataSize);
142 uint8_t SDP_SDRAM_ReadData_32b(uint32_t pAddress, uint32_t *pData, uint32_t dataSize);
143 uint8_t SDP_SDRAM_ReadData_DMA(uint32_t pAddress, uint32_t *pData, uint32_t dataSize);
144 uint8_t SDP_SDRAM_WriteData_8b(uint32_t pAddress, uint8_t *pData, uint32_t dataSize);
145 uint8_t SDP_SDRAM_WriteData_16b(uint32_t pAddress, uint16_t *pData, uint32_t dataSize);
146 uint8_t SDP_SDRAM_WriteData_32b(uint32_t pAddress, uint32_t *pData, uint32_t dataSize);
147 uint8_t SDP_SDRAM_WriteData_DMA(uint32_t pAddress, uint32_t *pData, uint32_t dataSize);
148 uint8_t SDP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
149 
150 /* These functions can be modified in case the current settings (e.g. DMA stream)
151  need to be changed for specific application needs */
152 void SDP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params);
153 void SDP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params);
154 
155 #ifdef __cplusplus
156 }
157 #endif
158 
159 #endif // TARGET_SDP_K1
160 #endif // __SDPK1_SDRAM_H
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