API Reference

Main Module

Parts Module

Clock Device Tree Interface

class adidt.parts.clock_dt.clock_dt

Bases: object

handle_64bit(prop, node, num)

set_clock_node(parent, clk, name, reg)

setter(node, prop_name, value)

update_existing_clock_node(node, clk)

set_vcxo(node, vcxo)

get_prop_across_nodes(node, prop)

get_node_by_prop(parent, prop, value)

get_used_clocks(node)

Clock Generators

HMC7044

class adidt.parts.hmc7044.hmc7044_dt(arch='auto', dt_source='local_sysfs', ip='192.168.2.1', username='root', password='analog', local_dt_filepath='')

Bases: dt, clock_dt

HMC7044 Device tree map class.

pulse_gen_modes = {'GEN_16_PULSE': 5, 'GEN_1_PULSE': 1, 'GEN_2_PULSE': 2, 'GEN_4_PULSE': 3, 'GEN_8_PULSE': 4, 'GEN_CONT_PULSE': 7, 'GEN_LEVEL_SENSITIVE': 0}

driver_modes = {'CML': 0, 'CMOS': 3, 'LVDS': 2, 'LVPECL': 1}

driver_impedances = {'100_OHM': 1, '50_OHM': 3, 'DISABLE': 0}

output_mux_modes = {'ANALOG_DELAY': 1, 'CH_DIV': 0, 'GROUP_PAIR': 3, 'VCO_CLOCK': 4}

cmos_outputs_reg_field_map = {0: {'N': 0, 'P': 1}, 1: {'N': 1, 'P': 0}, 2: {'N': 1, 'P': 0}, 3: {'N': 0, 'P': 1}, 4: {'N': 1, 'P': 0}, 5: {'N': 0, 'P': 1}, 6: {'N': 0, 'P': 1}, 7: {'N': 1, 'P': 0}, 8: {'N': 1, 'P': 0}, 9: {'N': 0, 'P': 1}, 10: {'N': 0, 'P': 1}, 11: {'N': 1, 'P': 0}, 12: {'N': 1, 'P': 0}, 13: {'N': 0, 'P': 1}}

set_clock_node(parent, clk, name, reg)

set_dt_node_from_config(node: Node, config: Dict, append=False)

Set HMC7044 node from JIF configuration

Parameters:

• node (fdt.Node) – Device tree parent node of hmc7044

• config (Dict) – Configuration struct generated from JIF

• append (boolean) – Enable appending to subnode, if false the existing are removed

AD9523-1

class adidt.parts.ad9523_1.ad9523_1_dt

Bases: clock_dt

AD9523-1 Device tree map class.

compatible_id = 'adi,ad9523-1'

set_dt_node_from_config(node: Node, config: Dict, append=False)

Set AD9523-1 node from JIF configuration

Parameters:

• node (fdt.Node) – Device tree parent node of AD9523-1

• config (Dict) – Configuration struct generated from JIF

• append (boolean) – Enable appending to subnode, if false the existing are removed

AD9528

adidt.parts.ad9528.parse_profile(filename)

AD9545

class adidt.parts.ad9545.ad9545_dt(arch='auto', dt_source='local_sysfs', ip='192.168.2.1', username='root', password='analog', local_dt_filepath='')

Bases: dt

AD9545 Device tree map class.

pll_clock_id = 1

out_clock_id = 0

set_clock_node(parent, clk, name, reg)

pll_set_rate(pll_nr: int, rate: int, node: Node)

Rate change for PLLs is trickier, it is found in the assigned-clocks/assigned-clock-rates

output_set_rate(output_nr: int, rate: int, node: Node)

Rate change for PLLs is trickier, it is found in the assigned-clocks/assigned-clock-rates

set_source_priorities_from_config(node: Node, config: Dict)

set_dt_node_from_config(node: Node, config: Dict, append=False)

Set AD9545 node from JIF configuration

Parameters:

• node (fdt.Node) – Device tree parent node of ad9545

• config (Dict) – Configuration struct generated from JIF

RF Transceivers

ADRV9009

adidt.parts.adrv9009.parse_talInit(file)

adidt.parts.adrv9009.handle_ints(val)

adidt.parts.adrv9009.handle_channel_enable(data: dict, key: str, default: int = 0)

adidt.parts.adrv9009.parse_profile(filename)

class adidt.parts.adrv9009.adrv9009_dt(arch='auto', dt_source='local_sysfs', ip='192.168.2.1', username='root', password='analog', local_dt_filepath='')

Bases: dt

set_dt_node_from_config(node: Node, config: Dict, profile: Dict, append=False)

Set ADRV9009 node from JIF configuration

Parameters:

• node (fdt.Node) – Device tree parent node of adrv9009

• config (Dict) – Configuration struct generated from JIF

• append (boolean) – Enable appending to subnode, if false the existing are removed

Boards Module

Board Layout Base

class adidt.boards.layout.layout

Bases: object

Common Layout Class for DT generation templates.

includes = ['']

template_filename = None

output_filename = None

use_plugin_mode = True

gen_dt_preprocess(**kwargs)

gen_dt(**kwargs)

Generate the DT file from configuration structs.

Raises:

• Exception – If the template file does not exist.

• Exception – If the output filename is not defined.

Parameters:

kwargs – Configuration structs.

map_jesd_subclass(name)

Map JESD204 subclass to integer.

Parameters:

name (str) – JESD subclass name.

Raises:

Exception – Invalid subclass name.

Returns:

JESD subclass integer.

Return type:

int

Evaluation Boards

DAQ2

class adidt.boards.daq2.daq2(platform='zcu102', kernel_path=None)

Bases: layout

clock = 'ad9523_1'

adc = 'ad9680'

dac = 'ad9144'

use_plugin_mode = False

DEFAULT_KERNEL_PATH = './linux'

PLATFORM_CONFIGS = {'zc706': {'arch': 'arm', 'base_dts_file': 'arch/arm/boot/dts/xilinx/zynq-zc706.dts', 'base_dts_include': 'zynq-zc706.dts', 'default_fpga_adc_pll': 'XCVR_CPLL', 'default_fpga_dac_pll': 'XCVR_QPLL', 'jesd_phy': 'GTX', 'output_dir': 'generated_dts', 'spi_bus': 'spi0', 'template_filename': 'daq2_zc706.tmpl'}, 'zcu102': {'arch': 'arm64', 'base_dts_file': 'arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-fmcdaq2.dts', 'base_dts_include': 'zynqmp-zcu102-rev10-fmcdaq2.dts', 'default_fpga_adc_pll': 'XCVR_CPLL', 'default_fpga_dac_pll': 'XCVR_QPLL', 'jesd_phy': 'GTH', 'output_dir': 'generated_dts', 'spi_bus': 'spi1', 'template_filename': 'daq2_zcu102.tmpl'}}

__init__(platform='zcu102', kernel_path=None)

Initialize DAQ2 board.

Parameters:

• platform (str) – Target platform (‘zcu102’)

• kernel_path (str, optional) – Path to Linux kernel source tree. If None, validation is skipped for backward compatibility.

Raises:

ValueError – If platform is not supported

template_filename = 'daq2.tmpl'

output_filename = 'daq2.dts'

get_dtc_include_paths()

Get list of include paths for dtc compilation.

Returns:

Include paths for dtc -i option

Return type:

list

validate_and_default_fpga_config(cfg)

Validate and apply platform defaults for FPGA configuration.

Parameters:

cfg (dict) – Configuration dictionary

Returns:

Configuration with FPGA defaults applied

Return type:

dict

make_ints(cfg, keys)

map_jesd_structs(cfg)

map_clocks_to_board_layout(cfg)

gen_dt_preprocess(**kwargs)

Add metadata to template rendering context.

Parameters:

kwargs – Template rendering context

Returns:

Updated context with metadata

Return type:

dict

AD9081 FMC

class adidt.boards.ad9081_fmc.ad9081_fmc(platform='zcu102', kernel_path=None)

Bases: layout

AD9081 FMC board layout map for clocks and DSP

clock = 'HMC7044'

adc = 'ad9081_rx'

dac = 'ad9081_tx'

DEFAULT_KERNEL_PATH = './linux'

PLATFORM_CONFIGS = {'vpk180': {'arch': 'arm64', 'base_dts_file': 'arch/arm64/boot/dts/xilinx/versal-vpk180-revA.dts', 'base_dts_include': 'versal-vpk180-revA.dts', 'default_fpga_adc_pll': 'XCVR_QPLL0', 'default_fpga_dac_pll': 'XCVR_QPLL0', 'jesd_phy': 'GTY', 'output_dir': 'generated_dts', 'spi_bus': 'spi1', 'template_filename': 'ad9081_fmc_vpk180.tmpl'}, 'zc706': {'arch': 'arm', 'base_dts_file': 'arch/arm/boot/dts/zynq-zc706.dts', 'base_dts_include': 'zynq-zc706.dts', 'default_fpga_adc_pll': 'XCVR_QPLL', 'default_fpga_dac_pll': 'XCVR_QPLL', 'jesd_phy': 'GTX', 'output_dir': 'generated_dts', 'spi_bus': 'spi0', 'template_filename': 'ad9081_fmc_zc706.tmpl'}, 'zcu102': {'arch': 'arm64', 'base_dts_file': 'arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts', 'base_dts_include': 'zynqmp-zcu102-rev1.0.dts', 'default_fpga_adc_pll': 'XCVR_QPLL', 'default_fpga_dac_pll': 'XCVR_QPLL', 'jesd_phy': 'GTH', 'output_dir': 'generated_dts', 'spi_bus': 'spi1', 'template_filename': 'ad9081_fmc_zcu102.tmpl'}}

__init__(platform='zcu102', kernel_path=None)

Initialize AD9081 FMC board.

Parameters:

• platform (str) – Target platform (‘zcu102’, ‘vpk180’, or ‘zc706’)

• kernel_path (str, optional) – Path to Linux kernel source tree. If None, validation is skipped for backward compatibility.

Raises:

ValueError – If platform is not supported

template_filename = 'ad9081_fmc_zcu102.tmpl'

output_filename = 'ad9081_fmc_zcu102.dts'

get_dtc_include_paths()

Get list of include paths for dtc compilation.

Returns:

Include paths for dtc -i option

Return type:

list

validate_and_default_fpga_config(cfg)

Validate and apply platform defaults for FPGA configuration.

Parameters:

cfg (dict) – Configuration dictionary

Returns:

Configuration with FPGA defaults applied

Return type:

dict

make_ints(cfg, keys)

Convert keys in a dict to integers.

Parameters:

• cfg (dict) – Configuration.

• keys (list) – Keys to convert.

Returns:

Configuration with keys converted to integers.

Return type:

dict

map_jesd_structs(cfg)

Map JIF configuration to integer structs.

Parameters:

cfg (dict) – JIF configuration.

Returns:

ADC JESD structs. dict: DAC JESD structs.

Return type:

dict

gen_dt_preprocess(**kwargs)

Add metadata to template rendering context.

Parameters:

kwargs – Template rendering context

Returns:

Updated context with metadata

Return type:

dict

map_clocks_to_board_layout(cfg)

Map JIF configuration to board clock connection layout.

Parameters:

cfg (dict) – JIF configuration.

Returns:

Board clock connection layout.

Return type:

dict

AD9084 FMC

AD9084 FMC board device tree generation support.

This module provides device tree generation for the AD9084-FMCA-EBZ evaluation board on Versal platforms (VPK180, VCK190).

The AD9084 is a high-performance multi-channel RF transceiver that uses: - HMC7044 as the primary clock generator - ADF4382 as the device clock PLL - ADF4030 (AION) for JESD204C sysref distribution

Reference: linux/arch/arm64/boot/dts/xilinx/versal-vpk180-reva-ad9084.dts

class adidt.boards.ad9084_fmc.ad9084_fmc(platform='vpk180', kernel_path=None)

Bases: layout

AD9084 FMC board layout map for clocks and DSP

clock = 'HMC7044'

ext_clock = 'ADF4382'

sysref_provider = 'ADF4030'

adc = 'ad9084_rx'

dac = 'ad9084_tx'

DEFAULT_KERNEL_PATH = './linux'

PLATFORM_CONFIGS = {'vck190': {'arch': 'arm64', 'base_dts_file': 'arch/arm64/boot/dts/xilinx/versal-vck190-revA.dts', 'base_dts_include': 'versal-vck190-revA.dts', 'default_fpga_adc_pll': 'XCVR_QPLL0', 'default_fpga_dac_pll': 'XCVR_QPLL0', 'jesd_phy': 'GTY', 'output_dir': 'generated_dts', 'spi_bus': 'spi0', 'template_filename': 'ad9084_fmc_vck190.tmpl'}, 'vcu118': {'arch': 'microblaze', 'base_dts_file': None, 'base_dts_include': 'vcu118_ad9084_204C_M4_L8_NP16_20p0_4x4.dts', 'default_fpga_adc_pll': 'XCVR_QPLL1', 'default_fpga_dac_pll': 'XCVR_QPLL1', 'jesd_phy': 'GTY', 'output_dir': None, 'spi_bus': 'axi_spi_2', 'template_filename': 'ad9084_fmc_vcu118.tmpl'}, 'vpk180': {'arch': 'arm64', 'base_dts_file': 'arch/arm64/boot/dts/xilinx/versal-vpk180-revA.dts', 'base_dts_include': 'versal-vpk180-revA.dts', 'default_fpga_adc_pll': 'XCVR_QPLL0', 'default_fpga_dac_pll': 'XCVR_QPLL0', 'jesd_phy': 'GTY', 'output_dir': 'generated_dts', 'spi_bus': 'spi0', 'template_filename': 'ad9084_fmc_vpk180.tmpl'}}

use_plugin_mode = False

__init__(platform='vpk180', kernel_path=None)

Initialize AD9084 FMC board.

Parameters:

• platform (str) – Target platform (‘vpk180’ or ‘vck190’)

• kernel_path (str, optional) – Path to Linux kernel source tree. If None, uses LINUX_KERNEL_PATH env var or default path.

Raises:

• ValueError – If platform is not supported

• FileNotFoundError – If kernel path is invalid (when explicitly provided)

template_filename = 'ad9084_fmc_vpk180.tmpl'

output_filename = 'ad9084_fmc_vpk180.dts'

get_dtc_include_paths()

Get list of include paths for dtc compilation.

Returns:

Include paths for dtc -i option

Return type:

list

validate_and_default_fpga_config(cfg)

Validate and apply platform defaults for FPGA configuration.

Parameters:

cfg (dict) – Configuration dictionary

Returns:

Configuration with FPGA defaults applied

Return type:

dict

gen_dt_preprocess(**kwargs)

Add metadata to template rendering context.

Parameters:

kwargs – Template rendering context

Returns:

Updated context with metadata

Return type:

dict

map_clocks_to_board_layout(cfg)

Map configuration to board clock connection layout.

The AD9084 uses HMC7044 as the primary clock generator with the following channel assignments: - Channel 1: ADF4030_REFIN (125 MHz) - Channel 3: ADF4030_BSYNC0 (9.765 MHz) - Channel 8: CORE_CLK_TX (312.5 MHz) - Channel 9: CORE_CLK_RX (312.5 MHz) - Channel 10: FPGA_REFCLK (312.5 MHz) - Channel 11: CORE_CLK_RX_B (312.5 MHz) - Channel 12: CORE_CLK_TX_B (312.5 MHz)

Parameters:

cfg (dict) – Configuration dictionary

Returns:

(clock_config, adc_config, dac_config, fpga_config)

Return type:

tuple

ADRV9009 FMC

ADRV9009 FMC board device tree generation support (JSON-based).

This module provides JSON-based device tree generation for the ADRV9009 evaluation board on ZCU102 and ZC706 platforms.

The ADRV9009 is a highly integrated RF transceiver that uses: - AD9528 as the clock generator - JESD204B for high-speed data interface

This is a NEW implementation using JSON configuration (like AD9081), distinct from the existing profile-based implementations in adrv9009_pcbz.py.

Reference: linux/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9009.dts

class adidt.boards.adrv9009_fmc.adrv9009_fmc(platform='zcu102', kernel_path=None)

Bases: layout

ADRV9009 FMC board layout for JSON-based DT generation

clock = 'AD9528'

transceiver = 'ADRV9009'

DEFAULT_KERNEL_PATH = './linux'

PLATFORM_CONFIGS = {'zc706': {'arch': 'arm', 'base_dts_file': 'arch/arm/boot/dts/xilinx/zynq-zc706.dts', 'base_dts_include': 'zynq-zc706.dts', 'clock_ref': 'clkc 16', 'default_fpga_orx_pll': 'XCVR_CPLL', 'default_fpga_rx_pll': 'XCVR_CPLL', 'default_fpga_tx_pll': 'XCVR_QPLL', 'jesd_phy': 'GTX', 'output_dir': 'generated_dts', 'spi_bus': 'spi1', 'template_filename': 'adrv9009_fmc_zc706.tmpl'}, 'zcu102': {'arch': 'arm64', 'base_dts_file': 'arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts', 'base_dts_include': 'zynqmp-zcu102-rev1.0.dts', 'clock_ref': 'zynqmp_clk 71', 'default_fpga_orx_pll': 'XCVR_CPLL', 'default_fpga_rx_pll': 'XCVR_CPLL', 'default_fpga_tx_pll': 'XCVR_QPLL', 'jesd_phy': 'GTH', 'output_dir': 'generated_dts', 'spi_bus': 'spi0', 'template_filename': 'adrv9009_fmc_zcu102.tmpl'}}

use_plugin_mode = False

__init__(platform='zcu102', kernel_path=None)

Initialize ADRV9009 FMC board.

Parameters:

• platform (str) – Target platform (‘zcu102’ or ‘zc706’)

• kernel_path (str, optional) – Path to Linux kernel source tree.

Raises:

• ValueError – If platform is not supported

• FileNotFoundError – If kernel path is invalid (when explicitly provided)

template_filename = 'adrv9009_fmc_zcu102.tmpl'

output_filename = 'adrv9009_fmc_zcu102.dts'

get_dtc_include_paths()

Get list of include paths for dtc compilation.

validate_and_default_fpga_config(cfg)

Validate and apply platform defaults for FPGA configuration.

gen_dt_preprocess(**kwargs)

Add metadata to template rendering context.

map_clocks_to_board_layout(cfg)

Map configuration to board clock connection layout.

The ADRV9009 uses AD9528 as the clock generator with outputs: - Channel 13: DEV_CLK (device clock) - Channel 1: FMC_CLK (FPGA clock) - Channel 12: DEV_SYSREF (device sysref) - Channel 3: FMC_SYSREF (FPGA sysref)

Parameters:

cfg (dict) – Configuration dictionary

Returns:

(clock_config, rx_config, tx_config, orx_config, fpga_config)

Return type:

tuple

ADRV9009 PCB-Z

class adidt.boards.adrv9009_pcbz.adrv9009_pcbz

Bases: layout

ADRV9009-PCBZ FMC board layout map for clocks and DSP

template_filename = 'adi-adrv9009.dtsi'

output_filename = 'adi-adrv9009.dtsi'

profile = None

parse_profile(filename: Path)

Parse a profile file.

Parameters:

filename – Profile file name.

Returns:

Profile configuration.

Return type:

dict

parse_talInit(filename: Path)

gen_dt_preprocess()

ADRV9009 ZU11EG

class adidt.boards.adrv9009_zu11eg.adrv9009_zu11eg

Bases: layout

ADRV9009-ZU11EG SOM board layout map for clocks and DSP

clock = 'HMC7044'

adc = 'adrv9009_rx'

dac = 'adrv9009_tx'

template_filename = 'adrv9009_zu11eg.dts'

output_filename = 'adrv9009_zu11eg_out.dts'

profile = None

make_ints(cfg, keys)

Convert keys in a dict to integers.

Parameters:

• cfg (dict) – Configuration.

• keys (list) – Keys to convert.

Returns:

Configuration with keys converted to integers.

Return type:

dict

map_jesd_structs(cfg)

Map JIF configuration to integer structs.

Parameters:

cfg (dict) – JIF configuration.

Returns:

ADC JESD structs. dict: DAC JESD structs.

Return type:

dict

map_clocks_to_board_layout(cfg)

Map JIF configuration to board clock connection layout.

Parameters:

cfg (dict) – JIF configuration.

Returns:

Board clock connection layout.

Return type:

dict

parse_profile(filename)

Parse a profile file.

Parameters:

filename (str) – Profile file name.

Returns:

Profile configuration.

Return type:

dict