Go to the documentation of this file.
62 #define AD3552R_REG_ADDR_INTERFACE_CONFIG_A 0x00
63 #define AD3552R_MASK_SOFTWARE_RESET (NO_OS_BIT(7) | NO_OS_BIT(0))
64 #define AD3552R_MASK_ADDR_ASCENSION NO_OS_BIT(5)
65 #define AD3552R_MASK_SDO_ACTIVE NO_OS_BIT(4)
66 #define AD3552R_REG_ADDR_INTERFACE_CONFIG_B 0x01
67 #define AD3552R_MASK_SINGLE_INST NO_OS_BIT(7)
68 #define AD3552R_MASK_SHORT_INSTRUCTION NO_OS_BIT(3)
69 #define AD3552R_REG_ADDR_DEVICE_CONFIG 0x02
70 #define AD3552R_MASK_DEVICE_STATUS(n) NO_OS_BIT(4 + (n))
71 #define AD3552R_MASK_CUSTOM_MODES (NO_OS_BIT(3) | NO_OS_BIT(2))
72 #define AD3552R_MASK_OPERATING_MODES NO_OS_GENMASK(1, 0)
73 #define AD3552R_REG_ADDR_CHIP_TYPE 0x03
74 #define AD3552R_MASK_CLASS NO_OS_GENMASK(7, 0)
75 #define AD3552R_REG_ADDR_PRODUCT_ID_L 0x04
76 #define AD3552R_REG_ADDR_PRODUCT_ID_H 0x05
77 #define AD3552R_REG_ADDR_CHIP_GRADE 0x06
78 #define AD3552R_MASK_GRADE NO_OS_GENMASK(7, 4)
79 #define AD3552R_MASK_DEVICE_REVISION NO_OS_GENMASK(3, 0)
80 #define AD3552R_REG_ADDR_SCRATCH_PAD 0x0A
81 #define AD3552R_REG_ADDR_SPI_REVISION 0x0B
82 #define AD3552R_REG_ADDR_VENDOR_L 0x0C
83 #define AD3552R_REG_ADDR_VENDOR_H 0x0D
84 #define AD3552R_REG_ADDR_STREAM_MODE 0x0E
85 #define AD3552R_MASK_LENGTH 0xFF
86 #define AD3552R_REG_ADDR_TRANSFER_REGISTER 0x0F
87 #define AD3552R_MASK_MULTI_IO_MODE (NO_OS_BIT(7) | NO_OS_BIT(6))
88 #define AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE NO_OS_BIT(2)
89 #define AD3552R_REG_ADDR_INTERFACE_CONFIG_C 0x10
90 #define AD3552R_MASK_CRC_ENABLE (NO_OS_BIT(7) | NO_OS_BIT(6) | NO_OS_BIT(1) | NO_OS_BIT(0))
91 #define AD3552R_MASK_STRICT_REGISTER_ACCESS NO_OS_BIT(5)
92 #define AD3552R_REG_ADDR_INTERFACE_STATUS_A 0x11
93 #define AD3552R_MASK_INTERFACE_NOT_READY NO_OS_BIT(7)
94 #define AD3552R_MASK_CLOCK_COUNTING_ERROR NO_OS_BIT(5)
95 #define AD3552R_MASK_INVALID_OR_NO_CRC NO_OS_BIT(3)
96 #define AD3552R_MASK_WRITE_TO_READ_ONLY_REGISTER NO_OS_BIT(2)
97 #define AD3552R_MASK_PARTIAL_REGISTER_ACCESS NO_OS_BIT(1)
98 #define AD3552R_MASK_REGISTER_ADDRESS_INVALID NO_OS_BIT(0)
99 #define AD3552R_REG_ADDR_INTERFACE_CONFIG_D 0x14
100 #define AD3552R_MASK_ALERT_ENABLE_PULLUP NO_OS_BIT(6)
101 #define AD3552R_MASK_MEM_CRC_EN NO_OS_BIT(4)
102 #define AD3552R_MASK_SDO_DRIVE_STRENGTH (NO_OS_BIT(3) | NO_OS_BIT(2))
103 #define AD3552R_MASK_DUAL_SPI_SYNCHROUNOUS_EN NO_OS_BIT(1)
104 #define AD3552R_MASK_SPI_CONFIG_DDR NO_OS_BIT(0)
105 #define AD3552R_REG_ADDR_SH_REFERENCE_CONFIG 0x15
106 #define AD3552R_MASK_IDUMP_FAST_MODE NO_OS_BIT(6)
107 #define AD3552R_MASK_SAMPLE_HOLD_DIFFERENTIAL_USER_EN NO_OS_BIT(5)
108 #define AD3552R_MASK_SAMPLE_HOLD_USER_TRIM (NO_OS_BIT(4) | NO_OS_BIT(3))
109 #define AD3552R_MASK_SAMPLE_HOLD_USER_ENABLE NO_OS_BIT(2)
110 #define AD3552R_MASK_REFERENCE_VOLTAGE_SEL (NO_OS_BIT(1) | NO_OS_BIT(0))
111 #define AD3552R_REG_ADDR_ERR_ALARM_MASK 0x16
112 #define AD3552R_MASK_REF_RANGE_ALARM NO_OS_BIT(6)
113 #define AD3552R_MASK_CLOCK_COUNT_ERR_ALARM NO_OS_BIT(5)
114 #define AD3552R_MASK_MEM_CRC_ERR_ALARM NO_OS_BIT(4)
115 #define AD3552R_MASK_SPI_CRC_ERR_ALARM NO_OS_BIT(3)
116 #define AD3552R_MASK_WRITE_TO_READ_ONLY_ALARM NO_OS_BIT(2)
117 #define AD3552R_MASK_PARTIAL_REGISTER_ACCESS_ALARM NO_OS_BIT(1)
118 #define AD3552R_MASK_REGISTER_ADDRESS_INVALID_ALARM NO_OS_BIT(0)
119 #define AD3552R_REG_ADDR_ERR_STATUS 0x17
120 #define AD3552R_MASK_REF_RANGE_ERR_STATUS NO_OS_BIT(6)
121 #define AD3552R_MASK_DUAL_SPI_STREAM_EXCEEDS_DAC_ERR_STATUS NO_OS_BIT(5)
122 #define AD3552R_MASK_MEM_CRC_ERR_STATUS NO_OS_BIT(4)
123 #define AD3552R_MASK_RESET_STATUS NO_OS_BIT(0)
124 #define AD3552R_REG_ADDR_POWERDOWN_CONFIG 0x18
125 #define AD3552R_MASK_CH_DAC_POWERDOWN(ch) NO_OS_BIT(4 + (ch))
126 #define AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(ch) NO_OS_BIT(ch)
127 #define AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE 0x19
128 #define AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch) ((ch) ? 0xF0 : 0xF)
129 #define AD3552R_REG_ADDR_CH_OFFSET(ch) (0x1B + (ch) * 2)
130 #define AD3552R_MASK_CH_OFFSET_BITS_0_7 0xFF
131 #define AD3552R_REG_ADDR_CH_GAIN(ch) (0x1C + (ch) * 2)
132 #define AD3552R_MASK_CH_RANGE_OVERRIDE NO_OS_BIT(7)
133 #define AD3552R_MASK_CH_GAIN_SCALING_N (NO_OS_BIT(6) | NO_OS_BIT(5))
134 #define AD3552R_MASK_CH_GAIN_SCALING_P (NO_OS_BIT(4) | NO_OS_BIT(3))
135 #define AD3552R_MASK_CH_OFFSET_POLARITY NO_OS_BIT(2)
136 #define AD3552R_MASK_CH_OFFSET_BIT_8 NO_OS_BIT(0)
143 #define AD3552R_SECONDARY_REGION_START 0x28
144 #define AD3552R_REG_ADDR_HW_LDAC_16B 0x28
145 #define AD3552R_REG_ADDR_CH_DAC_16B(ch) (0x2C - (1 - ch) * 2)
146 #define AD3552R_REG_ADDR_DAC_PAGE_MASK_16B 0x2E
147 #define AD3552R_REG_ADDR_CH_SELECT_16B 0x2F
148 #define AD3552R_REG_ADDR_INPUT_PAGE_MASK_16B 0x31
149 #define AD3552R_REG_ADDR_SW_LDAC_16B 0x32
150 #define AD3552R_REG_ADDR_CH_INPUT_16B(ch) (0x36 - (1 - ch) * 2)
152 #define AD3552R_REG_START_24B 0x37
153 #define AD3552R_REG_ADDR_HW_LDAC_24B 0x37
154 #define AD3552R_REG_ADDR_CH_DAC_24B(ch) (0x3D - (1 - ch) * 3)
155 #define AD3552R_REG_ADDR_DAC_PAGE_MASK_24B 0x40
156 #define AD3552R_REG_ADDR_CH_SELECT_24B 0x41
157 #define AD3552R_REG_ADDR_INPUT_PAGE_MASK_24B 0x44
158 #define AD3552R_REG_ADDR_SW_LDAC_24B 0x45
159 #define AD3552R_REG_ADDR_CH_INPUT_24B(ch) (0x4B - (1 - ch) * 3)
161 #define AD3552R_REG_ADDR_MAX 0x4B
164 #define AD3552R_MASK_CH(ch) NO_OS_BIT(ch)
165 #define AD3552R_MASK_ALL_CH (NO_OS_BIT(0) | NO_OS_BIT(1))
166 #define AD3552R_MASK_DAC_12B 0xFFF0
167 #define AD3552R_REAL_BITS_PREC_MODE 16
168 #define AD3552R_STORAGE_BITS_PREC_MODE 24
169 #define AD3552R_REAL_BITS_FAST_MODE 12
170 #define AD3552R_STORAGE_BITS_FAST_MODE 16
171 #define AD3552R_MAX_OFFSET 511
172 #define AD3552R_LDAC_PULSE_US 1
173 #define AD3552R_BOTH_CH_SELECT (NO_OS_BIT(0) | NO_OS_BIT(1))
174 #define AD3552R_BOTH_CH_DESELECT 0x0
177 #define AD3552R_MAX_NUM_CH 2
255 #define AD3552R_CH_OUTPUT_RANGE_CUSTOM 100
287 #ifdef AD3552R_QSPI_IMPLEMENTED
289 AD3552R_SPI_MULTI_IO_MODE,
291 AD3552R_SPI_DATA_RATE,
293 AD3552R_SPI_SYNCHRONOUS_ENABLE,
353 #ifdef AD3552R_QSPI_IMPLEMENTED
355 uint8_t multi_io_mode : 2;
365 uint8_t synchronous : 1;
503 int32_t *integer, int32_t *dec);
506 int32_t *integer, int32_t *dec);
516 uint32_t samples, uint32_t ch_mask,
@ AD3552R_WRITE_DAC_REGS
Definition: ad3552r.h:333
#define AD3552R_REG_ADDR_POWERDOWN_CONFIG
Definition: ad3552r.h:124
#define AD3552R_MASK_SPI_CONFIG_DDR
Definition: ad3552r.h:104
int32_t ad3552r_transfer(struct ad3552r_desc *desc, struct ad3552_transfer_data *data)
Definition: ad3552r.c:547
struct no_os_spi_desc * spi
Definition: ad3552r.h:400
@ AD3552R_MEDIUM_LOW_SDIO_DRIVE_STRENGTH
Definition: ad3552r.h:243
void no_os_put_unaligned_be16(uint16_t val, uint8_t *buf)
@ AD3552R_CH_FAST_EN
Definition: ad3552r.h:324
@ AD3552R_MEDIUM_HIGH_SDIO_DRIVE_STRENGTH
Definition: ad3552r.h:244
@ AD3552R_CH_RANGE_OVERRIDE
Definition: ad3552r.h:308
uint32_t timeout
Definition: ad413x.c:55
int32_t ad3552r_init(struct ad3552r_desc **desc, struct ad3552r_init_param *param)
Definition: ad3552r.c:1250
Structure holding the parameters for GPIO initialization.
Definition: no_os_gpio.h:85
#define AD3552R_MASK_DUAL_SPI_SYNCHROUNOUS_EN
Definition: ad3552r.h:103
#define AD3552R_SCRATCH_PAD_TEST_VAL1
Definition: ad3552r.c:91
#define AD3552R_MASK_INTERFACE_NOT_READY
Definition: ad3552r.h:93
@ AD3552R_CH_GAIN_SCALING_N
Definition: ad3552r.h:316
#define AD3552R_REG_ADDR_MAX
Definition: ad3552r.h:161
@ AD3552R_REGISTER_ADDRESS_INVALID
Definition: ad3552r.h:209
#define AD3552R_MASK_SDO_DRIVE_STRENGTH
Definition: ad3552r.h:102
struct no_os_gpio_desc * reset
Definition: ad3552r.h:402
uint8_t crc_table[NO_OS_CRC8_TABLE_SIZE]
Definition: ad3552r.h:404
#define AD3552R_READ_BIT
Definition: ad3552r.c:80
@ AD3552R_INTERFACE_NOT_READY
Definition: ad3552r.h:202
@ AD3552R_CRC_ENABLE
Definition: ad3552r.h:286
#define AD3552R_REG_ADDR_CH_INPUT_16B(ch)
Definition: ad3552r.h:150
int32_t ad3552r_set_dev_value(struct ad3552r_desc *desc, enum ad3552r_dev_attributes attr, uint16_t val)
Definition: ad3552r.c:708
int32_t ad3552r_init(struct ad3552r_desc **desc, struct ad3552r_init_param *init_param)
Definition: ad3552r.c:1250
#define AD3552R_REG_ADDR_CH_SELECT_24B
Definition: ad3552r.h:156
ad3552r_offset_polarity
Definition: ad3552r.h:268
#define AD3552R_REG_ADDR_CH_DAC_16B(ch)
Definition: ad3552r.h:145
ad3552r_ch_output_range
Definition: ad3552r.h:215
@ AD3552R_MEM_CRC_ERR_STATUS
Definition: ad3552r.h:212
@ AD3552R_DUAL_SPI_STREAM_EXCEEDS_DAC_ERR_STATUS
Definition: ad3552r.h:211
#define AD3552R_MAX_CH_NUM(id)
Definition: ad3552r.c:94
#define AD3552R_LDAC_PULSE_US
Definition: ad3552r.h:172
@ AD3552R_CH_DAC_POWERDOWN
Definition: ad3552r.h:299
Header file of SPI Interface.
int32_t ad3552r_read_reg(struct ad3552r_desc *desc, uint8_t addr, uint16_t *val)
Definition: ad3552r.c:611
#define AD3552R_MASK_CH_GAIN_SCALING_P
Definition: ad3552r.h:134
uint8_t ad3552r_reg_len(uint8_t addr)
Definition: ad3552r.c:221
uint8_t fast_en
Definition: ad3552r.h:395
@ AD3552R_CH_GAIN_SCALING_0_125
Definition: ad3552r.h:265
uint8_t range_override
Definition: ad3552r.h:394
uint8_t single_instr
Definition: ad3552r.h:347
#define AD3552R_CRC_ENABLE_VALUE
Definition: ad3552r.c:82
#define AD3552R_MASK_SOFTWARE_RESET
Definition: ad3552r.h:63
int32_t ad3552r_read_reg(struct ad3552r_desc *desc, uint8_t addr, uint16_t *val)
Definition: ad3552r.c:611
#define pr_err(fmt, args...)
Definition: no_os_print_log.h:94
uint8_t addr
Definition: ad3552r.h:371
int32_t ad3552r_set_asynchronous(struct ad3552r_desc *desc, uint8_t enable)
Definition: ad3552r.c:1421
struct no_os_gpio_init_param * ldac_gpio_param_optional
Definition: ad3552r.h:442
#define AD3552R_CRC_SEED
Definition: ad3552r.c:86
uint8_t ad3552r_reg_len(uint8_t addr)
Definition: ad3552r.c:221
Definition: no_os_spi.h:91
#define NO_OS_IS_ERR_VALUE(x)
Definition: no_os_error.h:56
struct ad3552_transfer_config * spi_cfg
Definition: ad3552r.h:379
uint8_t ad3552r_get_code_reg_addr(uint8_t ch, uint8_t is_dac, uint8_t is_fast)
Definition: ad3552r.c:732
#define AD3552R_MASK_CRC_ENABLE
Definition: ad3552r.h:90
Header file of Delay functions.
#define AD3552R_REG_ADDR_CH_DAC_24B(ch)
Definition: ad3552r.h:154
@ AD3552R_CLOCK_COUNTING_ERROR
Definition: ad3552r.h:205
#define AD3552R_MASK_ADDR_ASCENSION
Definition: ad3552r.h:64
#define AD3552R_MASK_CH(ch)
Definition: ad3552r.h:164
@ AD3552R_CH_HW_LDAC_MASK
Definition: ad3552r.h:320
int32_t ad3552r_remove(struct ad3552r_desc *desc)
Definition: ad3552r.c:1342
int32_t ad3552r_write_samples(struct ad3552r_desc *desc, uint16_t *data, uint32_t samples, uint32_t ch_mask, enum ad3552r_write_mode mode)
Definition: ad3552r.c:1479
@ AD3551R_NUM_CHANNELS
Definition: ad3552r.h:251
@ AD3552R_VREF_SELECT
Definition: ad3552r.h:284
int32_t ad3552r_set_ch_value(struct ad3552r_desc *desc, enum ad3552r_ch_attributes attr, uint8_t ch, uint16_t val)
Definition: ad3552r.c:1022
@ NO_OS_GPIO_HIGH
Definition: no_os_gpio.h:123
@ AD3552R_SDO_DRIVE_STRENGTH
Definition: ad3552r.h:278
#define AD3552R_REG_ADDR_INTERFACE_CONFIG_A
Definition: ad3552r.h:62
@ AD3552R_SINGLE_INST
Definition: ad3552r.c:65
@ AD3542R_CH_OUTPUT_RANGE_NEG_2P5__7P5V
Definition: ad3552r.h:238
Timer control module header.
int32_t ad3552r_write_samples(struct ad3552r_desc *desc, uint16_t *data, uint32_t samples, uint32_t ch_mask, enum ad3552r_write_mode mode)
Definition: ad3552r.c:1479
#define AD3552R_REG_ADDR_HW_LDAC_16B
Definition: ad3552r.h:144
ad3552r_ch_gain_scaling
Definition: ad3552r.h:257
uint8_t is_simultaneous
Definition: ad3552r.h:407
void * no_os_calloc(size_t nitems, size_t size)
Allocate memory and return a pointer to it, set memory to 0.
Definition: chibios_alloc.c:60
#define NO_OS_ARRAY_SIZE(x)
Definition: no_os_util.h:55
ad3552r_status
Definition: ad3552r.h:199
@ AD3552R_PARTIAL_REGISTER_ACCESS
Definition: ad3552r.h:208
@ AD3542R_CH_OUTPUT_RANGE_0__5V
Definition: ad3552r.h:232
@ AD3552R_EXTERNAL_VREF_PIN_INPUT
Definition: ad3552r.h:196
#define AD3552R_REG_ADDR_CH_INPUT_24B(ch)
Definition: ad3552r.h:159
int32_t ad3552r_get_offset(struct ad3552r_desc *desc, uint8_t ch, int32_t *integer, int32_t *dec)
Definition: ad3552r.c:1113
@ AD3542R_CH_OUTPUT_RANGE_0__2P5V
Definition: ad3552r.h:230
enum ad3552r_id chip_id
Definition: ad3552r.h:437
int32_t offset_int
Definition: ad3552r.h:385
@ AD3552R_CH_GAIN_SCALING_0_25
Definition: ad3552r.h:263
@ AD3552R_INVALID_OR_NO_CRC
Definition: ad3552r.h:206
uint8_t stream_length_keep_value
Definition: ad3552r.h:352
@ NO_OS_GPIO_LOW
Definition: no_os_gpio.h:121
uint8_t * tx_buff
Definition: no_os_spi.h:93
struct ad3552_transfer_config spi_cfg
Definition: ad3552r.h:399
#define AD3552R_MAX_REG_SIZE
Definition: ad3552r.c:79
@ AD3552R_CH_OUTPUT_RANGE_NEG_5__5V
Definition: ad3552r.h:223
@ AD3552R_CH_GAIN_OFFSET
Definition: ad3552r.h:310
bool crc_en
Definition: ad3552r.h:451
@ AD3552R_WRITE_TO_READ_ONLY_REGISTER
Definition: ad3552r.h:207
ad3542r_ch_output_range
Definition: ad3552r.h:228
@ AD3552R_INTERNAL_VREF_PIN_FLOATING
Definition: ad3552r.h:192
ad3552r_sdio_drive_strength
Definition: ad3552r.h:241
#define AD3552R_REG_ADDR_INTERFACE_CONFIG_C
Definition: ad3552r.h:89
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: aducm3029_delay.c:132
uint32_t no_os_field_prep(uint32_t mask, uint32_t val)
int32_t ad3552r_get_ch_value(struct ad3552r_desc *desc, enum ad3552r_ch_attributes attr, uint8_t ch, uint16_t *val)
Definition: ad3552r.c:975
#define AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE
Definition: ad3552r.h:127
#define AD3552R_MASK_SINGLE_INST
Definition: ad3552r.h:67
#define AD3552R_MASK_CH_OFFSET_BIT_8
Definition: ad3552r.h:136
Definition: ad3552r.h:382
#define pr_debug(fmt, args...)
Definition: no_os_print_log.h:135
ad3552r_id
Definition: ad3552r.h:183
@ AD3552R_OFFSET_POLARITY_POSITIVE
Definition: ad3552r.h:270
bool is_simultaneous
Definition: ad3552r.h:452
#define AD3552R_MASK_CH_GAIN_SCALING_N
Definition: ad3552r.h:133
int32_t ad3552r_get_dev_value(struct ad3552r_desc *desc, enum ad3552r_dev_attributes attr, uint16_t *val)
Definition: ad3552r.c:682
#define AD3552R_REG_ADDR_HW_LDAC_24B
Definition: ad3552r.h:153
int32_t offset_dec
Definition: ad3552r.h:386
#define AD3552R_REG_ADDR_INTERFACE_CONFIG_B
Definition: ad3552r.h:66
int32_t ad3552r_get_status(struct ad3552r_desc *desc, uint32_t *status, uint8_t clr_err)
@ AD3552R_WRITE_INPUT_REGS
Definition: ad3552r.h:335
#define AD3552R_SECONDARY_REGION_ADDR
Definition: ad3552r.c:87
#define AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch)
Definition: ad3552r.h:128
void no_os_crc8_populate_msb(uint8_t *table, const uint8_t polynomial)
#define AD3552R_REG_ADDR_ERR_STATUS
Definition: ad3552r.h:119
uint8_t * rx_buff
Definition: no_os_spi.h:95
@ AD3541R_ID
Definition: ad3552r.h:184
@ AD3552R_ADDR_ASCENSION
Definition: ad3552r.c:62
bool fast_en
Definition: ad3552r.h:426
int32_t ad3552r_get_dev_value(struct ad3552r_desc *desc, enum ad3552r_dev_attributes attr, uint16_t *val)
Definition: ad3552r.c:682
int32_t ad3552r_remove(struct ad3552r_desc *desc)
Definition: ad3552r.c:1342
@ AD3552R_CH_OUTPUT_RANGE_0__10V
Definition: ad3552r.h:221
struct no_os_gpio_desc * ldac
Definition: ad3552r.h:401
@ AD3552R_INTERNAL_VREF_PIN_2P5V
Definition: ad3552r.h:194
#define AD3552R_MASK_REFERENCE_VOLTAGE_SEL
Definition: ad3552r.h:110
#define AD3552R_MASK_CH_OFFSET_POLARITY
Definition: ad3552r.h:135
@ AD3552R_CH_OUTPUT_RANGE_0__5V
Definition: ad3552r.h:219
#define AD3552R_CH_ATTR_REG(attr)
Definition: ad3552r.c:76
uint8_t gain_scaling_p_inv_log2
Definition: ad3552r.h:415
int32_t ad3552r_set_ch_value(struct ad3552r_desc *desc, enum ad3552r_ch_attributes attr, uint8_t ch, uint16_t val)
Definition: ad3552r.c:1022
@ AD3552R_CH_GAIN_OFFSET_POLARITY
Definition: ad3552r.h:312
#define AD3552R_REG_ADDR_DAC_PAGE_MASK_24B
Definition: ad3552r.h:155
uint8_t cs_change
Definition: no_os_spi.h:99
uint32_t len
Definition: ad3552r.h:375
uint8_t addr_asc
Definition: ad3552r.h:345
@ AD3552R_CH_OUTPUT_RANGE_NEG_10__10V
Definition: ad3552r.h:225
@ AD3552R_STREAM_MODE
Definition: ad3552r.c:67
@ AD3552R_REF_RANGE_ERR_STATUS
Definition: ad3552r.h:210
Definition: ad3552r.h:369
#define AD3552R_ATTR_MASK(attr)
Definition: ad3552r.c:75
struct ad3552r_ch_data ch_data[AD3552R_MAX_NUM_CH]
Definition: ad3552r.h:403
bool en
Definition: ad3552r.h:424
@ AD3552R_CH_AMPLIFIER_POWERDOWN
Definition: ad3552r.h:301
struct ad3552r_channel_init channels[AD3552R_MAX_NUM_CH]
Definition: ad3552r.h:449
struct ad3552r_custom_output_range_cfg custom_range
Definition: ad3552r.h:433
#define AD3552R_REG_ADDR_CH_OFFSET(ch)
Definition: ad3552r.h:129
#define AD3552R_REG_ADDR_CH_GAIN(ch)
Definition: ad3552r.h:131
int32_t ad3552r_get_offset(struct ad3552r_desc *desc, uint8_t ch, int32_t *integer, int32_t *dec)
Definition: ad3552r.c:1113
uint8_t gain_scaling_n_inv_log2
Definition: ad3552r.h:418
#define AD3552R_MAX_NUM_CH
Definition: ad3552r.h:177
int32_t no_os_gpio_remove(struct no_os_gpio_desc *desc)
Free the resources allocated by no_os_gpio_get().
Definition: no_os_gpio.c:110
Structure holding SPI descriptor.
Definition: no_os_spi.h:177
ad3552r_ch_attributes
Definition: ad3552r.h:297
#define AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE
Definition: ad3552r.h:88
#define AD3552R_SCRATCH_PAD_TEST_VAL2
Definition: ad3552r.c:92
num_channels
Definition: ad3552r.h:248
#define AD3552R_CH_ATTR_MASK(ch, attr)
Definition: ad3552r.c:77
@ AD3552R_RESET_STATUS
Definition: ad3552r.h:201
int32_t ad3552r_reset(struct ad3552r_desc *desc)
Definition: ad3552r.c:1354
#define AD3552R_ADDR_MASK
Definition: ad3552r.c:81
@ AD3552R_CH_GAIN_SCALING_0_5
Definition: ad3552r.h:261
struct no_os_spi_init_param spi_param
Definition: ad3552r.h:438
uint8_t n
Definition: ad3552r.h:391
uint8_t range
Definition: ad3552r.h:393
Structure holding the GPIO descriptor.
Definition: no_os_gpio.h:102
int32_t ad3552r_get_ch_value(struct ad3552r_desc *desc, enum ad3552r_ch_attributes attr, uint8_t ch, uint16_t *val)
Definition: ad3552r.c:975
int32_t ad3552r_get_scale(struct ad3552r_desc *desc, uint8_t ch, int32_t *integer, int32_t *dec)
Definition: ad3552r.c:1101
bool single_transfer
Definition: ad3552r.h:453
ad3552r_dev_attributes
Definition: ad3552r.h:275
@ AD3552R_WRITE_INPUT_REGS_AND_TRIGGER_LDAC
Definition: ad3552r.h:337
#define AD3552R_MASK_ALL_CH
Definition: ad3552r.h:165
Definition: ad3552r.h:436
@ AD3552R_CH_GAIN_SCALING_1
Definition: ad3552r.h:259
uint32_t bytes_number
Definition: no_os_spi.h:97
int32_t no_os_spi_transfer(struct no_os_spi_desc *desc, struct no_os_spi_msg *msgs, uint32_t len)
Iterate over head list and send all spi messages.
Definition: no_os_spi.c:191
@ AD3552R_NUM_CHANNELS
Definition: ad3552r.h:252
int32_t ad3552r_ldac_trigger(struct ad3552r_desc *desc, uint16_t mask, uint8_t is_fast)
Definition: ad3552r.c:1397
#define AD3552R_REG_ADDR_STREAM_MODE
Definition: ad3552r.h:84
#define AD3552R_REG_ADDR_TRANSFER_REGISTER
Definition: ad3552r.h:86
#define NO_OS_CRC8_TABLE_SIZE
Definition: no_os_crc8.h:45
#define AD3552R_GAIN_SCALE
Definition: ad3552r.c:100
ad3552r_ch_vref_select
Definition: ad3552r.h:190
ad3552r_spi_attributes
Definition: ad3552r.c:57
int16_t gain_offset
Definition: ad3552r.h:412
@ AD3541R_NUM_CHANNELS
Definition: ad3552r.h:249
#define AD3552R_CRC_DISABLE_VALUE
Definition: ad3552r.c:83
Definition: ad3552r.h:341
int32_t ad3552r_set_dev_value(struct ad3552r_desc *desc, enum ad3552r_dev_attributes attr, uint16_t val)
Definition: ad3552r.c:708
uint32_t no_os_field_get(uint32_t mask, uint32_t word)
int32_t ad3552r_simulatneous_update_enable(struct ad3552r_desc *desc)
Definition: ad3552r.c:759
int32_t ad3552r_single_transfer(struct ad3552r_desc *desc, struct ad3552_transfer_data *data)
Definition: ad3552r.c:501
Definition: ad3552r.h:411
uint16_t rfb_ohms
Definition: ad3552r.h:420
uint8_t no_os_crc8(const uint8_t *table, const uint8_t *pdata, size_t nbytes, uint8_t crc)
void no_os_free(void *ptr)
Deallocate memory previously allocated by a call to no_os_calloc or no_os_malloc.
Definition: chibios_alloc.c:75
int32_t scale_int
Definition: ad3552r.h:383
#define AD3552R_REG_ADDR_PRODUCT_ID_L
Definition: ad3552r.h:75
@ AD3542R_CH_OUTPUT_RANGE_0__10V
Definition: ad3552r.h:234
@ AD3552R_CH_RFB
Definition: ad3552r.h:322
@ AD3552R_STREAM_LENGTH_KEEP_VALUE
Definition: ad3552r.c:69
#define AD3552R_ATTR_REG(attr)
Definition: ad3552r.c:74
void no_os_udelay(uint32_t usecs)
Wait until usecs microseconds passed.
Definition: aducm3029_delay.c:120
@ AD3551R_ID
Definition: ad3552r.h:186
@ AD3542R_CH_OUTPUT_RANGE_NEG_5__5V
Definition: ad3552r.h:236
@ AD3552R_HIGH_SDIO_DRIVE_STRENGTH
Definition: ad3552r.h:245
@ AD3552R_CH_GAIN_SCALING_P
Definition: ad3552r.h:314
int32_t ad3552r_write_reg(struct ad3552r_desc *desc, uint8_t addr, uint16_t val)
Definition: ad3552r.c:577
#define AD3552R_REG_ADDR_SCRATCH_PAD
Definition: ad3552r.h:80
uint16_t rfb
Definition: ad3552r.h:390
int32_t no_os_gpio_set_value(struct no_os_gpio_desc *desc, uint8_t value)
Set the value of the specified GPIO.
Definition: no_os_gpio.c:203
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:119
int32_t ad3552r_ldac_trigger(struct ad3552r_desc *desc, uint16_t mask, uint8_t is_fast)
Definition: ad3552r.c:1397
#define AD3552R_MASK_LENGTH
Definition: ad3552r.h:85
@ AD3552R_CH_OUTPUT_RANGE_SEL
Definition: ad3552r.h:303
@ AD3552R_ID
Definition: ad3552r.h:187
#define AD3552R_DEFAULT_CONFIG_B_VALUE
Definition: ad3552r.c:88
uint8_t p
Definition: ad3552r.h:392
int32_t ad3552r_reset(struct ad3552r_desc *desc)
Definition: ad3552r.c:1354
int16_t gain_offset
Definition: ad3552r.h:387
#define AD3552R_MASK_CH_RANGE_OVERRIDE
Definition: ad3552r.h:132
uint8_t range
Definition: ad3552r.h:432
int32_t ad3552r_simulatneous_update_enable(struct ad3552r_desc *desc)
Definition: ad3552r.c:759
Definition: ad3552r.h:423
#define AD3552R_REG_ADDR_INTERFACE_CONFIG_D
Definition: ad3552r.h:99
int32_t no_os_spi_remove(struct no_os_spi_desc *desc)
Free the resources allocated by no_os_spi_init().
Definition: no_os_spi.c:122
int32_t ad3552r_get_scale(struct ad3552r_desc *desc, uint8_t ch, int32_t *integer, int32_t *dec)
Definition: ad3552r.c:1101
Header file of GPIO Interface.
uint8_t crc_en
Definition: ad3552r.h:406
#define AD3552R_BOTH_CH_DESELECT
Definition: ad3552r.h:174
#define AD3552R_MASK_CH_DAC_POWERDOWN(ch)
Definition: ad3552r.h:125
uint8_t sdo_drive_strength
Definition: ad3552r.h:448
Header file of ad3552r Driver.
#define AD3552R_BOTH_CH_SELECT
Definition: ad3552r.h:173
#define AD3552R_REG_ADDR_INTERFACE_STATUS_A
Definition: ad3552r.h:92
bool use_external_vref
Definition: ad3552r.h:444
#define AD3552R_REG_ADDR_SW_LDAC_16B
Definition: ad3552r.h:149
int32_t no_os_spi_init(struct no_os_spi_desc **desc, const struct no_os_spi_init_param *param)
Initialize the SPI communication peripheral.
Definition: no_os_spi.c:58
uint16_t no_os_get_unaligned_be16(uint8_t *buf)
#define AD3552R_MASK_CH_OFFSET_BITS_0_7
Definition: ad3552r.h:130
int32_t ad3552r_transfer(struct ad3552r_desc *desc, struct ad3552_transfer_data *data)
Definition: ad3552r.c:547
@ AD3552R_LOW_SDIO_DRIVE_STRENGTH
Definition: ad3552r.h:242
#define AD3552R_REG_ADDR_SH_REFERENCE_CONFIG
Definition: ad3552r.h:105
uint8_t * data
Definition: ad3552r.h:373
Header file of utility functions.
uint32_t no_os_find_first_set_bit(uint32_t word)
uint16_t offset
Definition: ad3552r.h:388
#define AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(ch)
Definition: ad3552r.h:126
#define AD3552R_REG_ADDR_CH_SELECT_16B
Definition: ad3552r.h:147
@ AD3542R_ID
Definition: ad3552r.h:185
#define AD3552R_CRC_POLY
Definition: ad3552r.c:85
ad3552r_write_mode
Definition: ad3552r.h:331
@ AD3552R_CH_SELECT
Definition: ad3552r.h:326
bool vref_out_enable
Definition: ad3552r.h:446
int32_t no_os_gpio_direction_output(struct no_os_gpio_desc *desc, uint8_t value)
Enable the output direction of the specified GPIO.
Definition: no_os_gpio.c:153
uint8_t is_read
Definition: ad3552r.h:377
@ AD3552R_CH_TRIGGER_SOFTWARE_LDAC
Definition: ad3552r.h:318
@ AD3552R_CH_CODE
Definition: ad3552r.h:328
uint8_t single_transfer
Definition: ad3552r.h:408
#define AD3552R_REG_ADDR_PRODUCT_ID_H
Definition: ad3552r.h:76
int32_t ad3552r_set_asynchronous(struct ad3552r_desc *desc, uint8_t enable)
Definition: ad3552r.c:1421
#define AD3552R_REG_ADDR_DAC_PAGE_MASK_16B
Definition: ad3552r.h:146
@ AD3552R_CH_OUTPUT_RANGE_0__2P5V
Definition: ad3552r.h:217
uint8_t stream_mode_length
Definition: ad3552r.h:343
Header file of CRC-8 computation.
uint8_t ad3552r_get_code_reg_addr(uint8_t ch, uint8_t is_dac, uint8_t is_fast)
Definition: ad3552r.c:732
@ AD3552R_OFFSET_POLARITY_NEGATIVE
Definition: ad3552r.h:272
uint8_t chip_id
Definition: ad3552r.h:405
#define AD3552R_MASK_MULTI_IO_MODE
Definition: ad3552r.h:87
#define AD3552R_REG_ADDR_SW_LDAC_24B
Definition: ad3552r.h:158
@ AD3542R_NUM_CHANNELS
Definition: ad3552r.h:250
#define NO_OS_DIV_ROUND_CLOSEST(x, y)
Definition: no_os_util.h:60
int32_t ad3552r_write_reg(struct ad3552r_desc *desc, uint8_t addr, uint16_t val)
Definition: ad3552r.c:577
int32_t scale_dec
Definition: ad3552r.h:384
Definition: ad3552r.h:398
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:131
#define AD3552R_CH_OUTPUT_RANGE_CUSTOM
Definition: ad3552r.h:255
uint8_t offset_polarity
Definition: ad3552r.h:389
struct no_os_gpio_init_param * reset_gpio_param_optional
Definition: ad3552r.h:440
int32_t no_os_gpio_get_optional(struct no_os_gpio_desc **desc, const struct no_os_gpio_init_param *param)
Get the value of an optional GPIO.
Definition: no_os_gpio.c:81