no-OS
Classes | Macros | Enumerations | Functions
ad3552r.h File Reference

Header file of ad3552r Driver. More...

#include <stdint.h>
#include <stdbool.h>
#include "no_os_spi.h"
#include "no_os_gpio.h"
#include "no_os_crc8.h"
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Classes

struct  ad3552_transfer_config
 
struct  ad3552_transfer_data
 
struct  ad3552r_ch_data
 
struct  ad3552r_desc
 
struct  ad3552r_custom_output_range_cfg
 
struct  ad3552r_channel_init
 
struct  ad3552r_init_param
 

Macros

#define AD3552R_REG_ADDR_INTERFACE_CONFIG_A   0x00
 
#define AD3552R_MASK_SOFTWARE_RESET   (NO_OS_BIT(7) | NO_OS_BIT(0))
 
#define AD3552R_MASK_ADDR_ASCENSION   NO_OS_BIT(5)
 
#define AD3552R_MASK_SDO_ACTIVE   NO_OS_BIT(4)
 
#define AD3552R_REG_ADDR_INTERFACE_CONFIG_B   0x01
 
#define AD3552R_MASK_SINGLE_INST   NO_OS_BIT(7)
 
#define AD3552R_MASK_SHORT_INSTRUCTION   NO_OS_BIT(3)
 
#define AD3552R_REG_ADDR_DEVICE_CONFIG   0x02
 
#define AD3552R_MASK_DEVICE_STATUS(n)   NO_OS_BIT(4 + (n))
 
#define AD3552R_MASK_CUSTOM_MODES   (NO_OS_BIT(3) | NO_OS_BIT(2))
 
#define AD3552R_MASK_OPERATING_MODES   NO_OS_GENMASK(1, 0)
 
#define AD3552R_REG_ADDR_CHIP_TYPE   0x03
 
#define AD3552R_MASK_CLASS   NO_OS_GENMASK(7, 0)
 
#define AD3552R_REG_ADDR_PRODUCT_ID_L   0x04
 
#define AD3552R_REG_ADDR_PRODUCT_ID_H   0x05
 
#define AD3552R_REG_ADDR_CHIP_GRADE   0x06
 
#define AD3552R_MASK_GRADE   NO_OS_GENMASK(7, 4)
 
#define AD3552R_MASK_DEVICE_REVISION   NO_OS_GENMASK(3, 0)
 
#define AD3552R_REG_ADDR_SCRATCH_PAD   0x0A
 
#define AD3552R_REG_ADDR_SPI_REVISION   0x0B
 
#define AD3552R_REG_ADDR_VENDOR_L   0x0C
 
#define AD3552R_REG_ADDR_VENDOR_H   0x0D
 
#define AD3552R_REG_ADDR_STREAM_MODE   0x0E
 
#define AD3552R_MASK_LENGTH   0xFF
 
#define AD3552R_REG_ADDR_TRANSFER_REGISTER   0x0F
 
#define AD3552R_MASK_MULTI_IO_MODE   (NO_OS_BIT(7) | NO_OS_BIT(6))
 
#define AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE   NO_OS_BIT(2)
 
#define AD3552R_REG_ADDR_INTERFACE_CONFIG_C   0x10
 
#define AD3552R_MASK_CRC_ENABLE   (NO_OS_BIT(7) | NO_OS_BIT(6) | NO_OS_BIT(1) | NO_OS_BIT(0))
 
#define AD3552R_MASK_STRICT_REGISTER_ACCESS   NO_OS_BIT(5)
 
#define AD3552R_REG_ADDR_INTERFACE_STATUS_A   0x11
 
#define AD3552R_MASK_INTERFACE_NOT_READY   NO_OS_BIT(7)
 
#define AD3552R_MASK_CLOCK_COUNTING_ERROR   NO_OS_BIT(5)
 
#define AD3552R_MASK_INVALID_OR_NO_CRC   NO_OS_BIT(3)
 
#define AD3552R_MASK_WRITE_TO_READ_ONLY_REGISTER   NO_OS_BIT(2)
 
#define AD3552R_MASK_PARTIAL_REGISTER_ACCESS   NO_OS_BIT(1)
 
#define AD3552R_MASK_REGISTER_ADDRESS_INVALID   NO_OS_BIT(0)
 
#define AD3552R_REG_ADDR_INTERFACE_CONFIG_D   0x14
 
#define AD3552R_MASK_ALERT_ENABLE_PULLUP   NO_OS_BIT(6)
 
#define AD3552R_MASK_MEM_CRC_EN   NO_OS_BIT(4)
 
#define AD3552R_MASK_SDO_DRIVE_STRENGTH   (NO_OS_BIT(3) | NO_OS_BIT(2))
 
#define AD3552R_MASK_DUAL_SPI_SYNCHROUNOUS_EN   NO_OS_BIT(1)
 
#define AD3552R_MASK_SPI_CONFIG_DDR   NO_OS_BIT(0)
 
#define AD3552R_REG_ADDR_SH_REFERENCE_CONFIG   0x15
 
#define AD3552R_MASK_IDUMP_FAST_MODE   NO_OS_BIT(6)
 
#define AD3552R_MASK_SAMPLE_HOLD_DIFFERENTIAL_USER_EN   NO_OS_BIT(5)
 
#define AD3552R_MASK_SAMPLE_HOLD_USER_TRIM   (NO_OS_BIT(4) | NO_OS_BIT(3))
 
#define AD3552R_MASK_SAMPLE_HOLD_USER_ENABLE   NO_OS_BIT(2)
 
#define AD3552R_MASK_REFERENCE_VOLTAGE_SEL   (NO_OS_BIT(1) | NO_OS_BIT(0))
 
#define AD3552R_REG_ADDR_ERR_ALARM_MASK   0x16
 
#define AD3552R_MASK_REF_RANGE_ALARM   NO_OS_BIT(6)
 
#define AD3552R_MASK_CLOCK_COUNT_ERR_ALARM   NO_OS_BIT(5)
 
#define AD3552R_MASK_MEM_CRC_ERR_ALARM   NO_OS_BIT(4)
 
#define AD3552R_MASK_SPI_CRC_ERR_ALARM   NO_OS_BIT(3)
 
#define AD3552R_MASK_WRITE_TO_READ_ONLY_ALARM   NO_OS_BIT(2)
 
#define AD3552R_MASK_PARTIAL_REGISTER_ACCESS_ALARM   NO_OS_BIT(1)
 
#define AD3552R_MASK_REGISTER_ADDRESS_INVALID_ALARM   NO_OS_BIT(0)
 
#define AD3552R_REG_ADDR_ERR_STATUS   0x17
 
#define AD3552R_MASK_REF_RANGE_ERR_STATUS   NO_OS_BIT(6)
 
#define AD3552R_MASK_DUAL_SPI_STREAM_EXCEEDS_DAC_ERR_STATUS   NO_OS_BIT(5)
 
#define AD3552R_MASK_MEM_CRC_ERR_STATUS   NO_OS_BIT(4)
 
#define AD3552R_MASK_RESET_STATUS   NO_OS_BIT(0)
 
#define AD3552R_REG_ADDR_POWERDOWN_CONFIG   0x18
 
#define AD3552R_MASK_CH_DAC_POWERDOWN(ch)   NO_OS_BIT(4 + (ch))
 
#define AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(ch)   NO_OS_BIT(ch)
 
#define AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE   0x19
 
#define AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch)   ((ch) ? 0xF0 : 0xF)
 
#define AD3552R_REG_ADDR_CH_OFFSET(ch)   (0x1B + (ch) * 2)
 
#define AD3552R_MASK_CH_OFFSET_BITS_0_7   0xFF
 
#define AD3552R_REG_ADDR_CH_GAIN(ch)   (0x1C + (ch) * 2)
 
#define AD3552R_MASK_CH_RANGE_OVERRIDE   NO_OS_BIT(7)
 
#define AD3552R_MASK_CH_GAIN_SCALING_N   (NO_OS_BIT(6) | NO_OS_BIT(5))
 
#define AD3552R_MASK_CH_GAIN_SCALING_P   (NO_OS_BIT(4) | NO_OS_BIT(3))
 
#define AD3552R_MASK_CH_OFFSET_POLARITY   NO_OS_BIT(2)
 
#define AD3552R_MASK_CH_OFFSET_BIT_8   NO_OS_BIT(0)
 
#define AD3552R_SECONDARY_REGION_START   0x28
 
#define AD3552R_REG_ADDR_HW_LDAC_16B   0x28
 
#define AD3552R_REG_ADDR_CH_DAC_16B(ch)   (0x2C - (1 - ch) * 2)
 
#define AD3552R_REG_ADDR_DAC_PAGE_MASK_16B   0x2E
 
#define AD3552R_REG_ADDR_CH_SELECT_16B   0x2F
 
#define AD3552R_REG_ADDR_INPUT_PAGE_MASK_16B   0x31
 
#define AD3552R_REG_ADDR_SW_LDAC_16B   0x32
 
#define AD3552R_REG_ADDR_CH_INPUT_16B(ch)   (0x36 - (1 - ch) * 2)
 
#define AD3552R_REG_START_24B   0x37
 
#define AD3552R_REG_ADDR_HW_LDAC_24B   0x37
 
#define AD3552R_REG_ADDR_CH_DAC_24B(ch)   (0x3D - (1 - ch) * 3)
 
#define AD3552R_REG_ADDR_DAC_PAGE_MASK_24B   0x40
 
#define AD3552R_REG_ADDR_CH_SELECT_24B   0x41
 
#define AD3552R_REG_ADDR_INPUT_PAGE_MASK_24B   0x44
 
#define AD3552R_REG_ADDR_SW_LDAC_24B   0x45
 
#define AD3552R_REG_ADDR_CH_INPUT_24B(ch)   (0x4B - (1 - ch) * 3)
 
#define AD3552R_REG_ADDR_MAX   0x4B
 
#define AD3552R_MASK_CH(ch)   NO_OS_BIT(ch)
 
#define AD3552R_MASK_ALL_CH   (NO_OS_BIT(0) | NO_OS_BIT(1))
 
#define AD3552R_MASK_DAC_12B   0xFFF0
 
#define AD3552R_REAL_BITS_PREC_MODE   16
 
#define AD3552R_STORAGE_BITS_PREC_MODE   24
 
#define AD3552R_REAL_BITS_FAST_MODE   12
 
#define AD3552R_STORAGE_BITS_FAST_MODE   16
 
#define AD3552R_MAX_OFFSET   511
 
#define AD3552R_LDAC_PULSE_US   1
 
#define AD3552R_BOTH_CH_SELECT   (NO_OS_BIT(0) | NO_OS_BIT(1))
 
#define AD3552R_BOTH_CH_DESELECT   0x0
 
#define AD3552R_MAX_NUM_CH   2
 
#define AD3552R_CH_OUTPUT_RANGE_CUSTOM   100
 

Enumerations

enum  ad3552r_id {
  AD3541R_ID,
  AD3542R_ID,
  AD3551R_ID,
  AD3552R_ID
}
 
enum  ad3552r_ch_vref_select {
  AD3552R_INTERNAL_VREF_PIN_FLOATING,
  AD3552R_INTERNAL_VREF_PIN_2P5V,
  AD3552R_EXTERNAL_VREF_PIN_INPUT
}
 
enum  ad3552r_status {
  AD3552R_RESET_STATUS = 0x0001,
  AD3552R_INTERFACE_NOT_READY = 0x0002,
  AD3552R_CLOCK_COUNTING_ERROR = 0x0004,
  AD3552R_INVALID_OR_NO_CRC = 0x0008,
  AD3552R_WRITE_TO_READ_ONLY_REGISTER = 0x0010,
  AD3552R_PARTIAL_REGISTER_ACCESS = 0x0020,
  AD3552R_REGISTER_ADDRESS_INVALID = 0x0040,
  AD3552R_REF_RANGE_ERR_STATUS = 0x0080,
  AD3552R_DUAL_SPI_STREAM_EXCEEDS_DAC_ERR_STATUS = 0x0100,
  AD3552R_MEM_CRC_ERR_STATUS = 0x0200
}
 
enum  ad3552r_ch_output_range {
  AD3552R_CH_OUTPUT_RANGE_0__2P5V,
  AD3552R_CH_OUTPUT_RANGE_0__5V,
  AD3552R_CH_OUTPUT_RANGE_0__10V,
  AD3552R_CH_OUTPUT_RANGE_NEG_5__5V,
  AD3552R_CH_OUTPUT_RANGE_NEG_10__10V
}
 
enum  ad3542r_ch_output_range {
  AD3542R_CH_OUTPUT_RANGE_0__2P5V,
  AD3542R_CH_OUTPUT_RANGE_0__5V,
  AD3542R_CH_OUTPUT_RANGE_0__10V,
  AD3542R_CH_OUTPUT_RANGE_NEG_5__5V,
  AD3542R_CH_OUTPUT_RANGE_NEG_2P5__7P5V
}
 
enum  ad3552r_sdio_drive_strength {
  AD3552R_LOW_SDIO_DRIVE_STRENGTH,
  AD3552R_MEDIUM_LOW_SDIO_DRIVE_STRENGTH,
  AD3552R_MEDIUM_HIGH_SDIO_DRIVE_STRENGTH,
  AD3552R_HIGH_SDIO_DRIVE_STRENGTH
}
 
enum  num_channels {
  AD3541R_NUM_CHANNELS =1,
  AD3542R_NUM_CHANNELS =2,
  AD3551R_NUM_CHANNELS =1,
  AD3552R_NUM_CHANNELS =2
}
 
enum  ad3552r_ch_gain_scaling {
  AD3552R_CH_GAIN_SCALING_1,
  AD3552R_CH_GAIN_SCALING_0_5,
  AD3552R_CH_GAIN_SCALING_0_25,
  AD3552R_CH_GAIN_SCALING_0_125
}
 
enum  ad3552r_offset_polarity {
  AD3552R_OFFSET_POLARITY_POSITIVE,
  AD3552R_OFFSET_POLARITY_NEGATIVE
}
 
enum  ad3552r_dev_attributes {
  AD3552R_SDO_DRIVE_STRENGTH,
  AD3552R_VREF_SELECT,
  AD3552R_CRC_ENABLE
}
 
enum  ad3552r_ch_attributes {
  AD3552R_CH_DAC_POWERDOWN,
  AD3552R_CH_AMPLIFIER_POWERDOWN,
  AD3552R_CH_OUTPUT_RANGE_SEL,
  AD3552R_CH_RANGE_OVERRIDE,
  AD3552R_CH_GAIN_OFFSET,
  AD3552R_CH_GAIN_OFFSET_POLARITY,
  AD3552R_CH_GAIN_SCALING_P,
  AD3552R_CH_GAIN_SCALING_N,
  AD3552R_CH_TRIGGER_SOFTWARE_LDAC,
  AD3552R_CH_HW_LDAC_MASK,
  AD3552R_CH_RFB,
  AD3552R_CH_FAST_EN,
  AD3552R_CH_SELECT,
  AD3552R_CH_CODE
}
 
enum  ad3552r_write_mode {
  AD3552R_WRITE_DAC_REGS,
  AD3552R_WRITE_INPUT_REGS,
  AD3552R_WRITE_INPUT_REGS_AND_TRIGGER_LDAC
}
 

Functions

uint8_t ad3552r_reg_len (uint8_t addr)
 
uint8_t ad3552r_get_code_reg_addr (uint8_t ch, uint8_t is_dac, uint8_t is_fast)
 
int32_t ad3552r_init (struct ad3552r_desc **desc, struct ad3552r_init_param *init_param)
 
int32_t ad3552r_remove (struct ad3552r_desc *desc)
 
int32_t ad3552r_reset (struct ad3552r_desc *desc)
 
int32_t ad3552r_get_status (struct ad3552r_desc *desc, uint32_t *status, uint8_t clr_err)
 
int32_t ad3552r_transfer (struct ad3552r_desc *desc, struct ad3552_transfer_data *data)
 
int32_t ad3552r_write_reg (struct ad3552r_desc *desc, uint8_t addr, uint16_t val)
 
int32_t ad3552r_read_reg (struct ad3552r_desc *desc, uint8_t addr, uint16_t *val)
 
int32_t ad3552r_get_dev_value (struct ad3552r_desc *desc, enum ad3552r_dev_attributes attr, uint16_t *val)
 
int32_t ad3552r_set_dev_value (struct ad3552r_desc *desc, enum ad3552r_dev_attributes attr, uint16_t val)
 
int32_t ad3552r_get_ch_value (struct ad3552r_desc *desc, enum ad3552r_ch_attributes attr, uint8_t ch, uint16_t *val)
 
int32_t ad3552r_set_ch_value (struct ad3552r_desc *desc, enum ad3552r_ch_attributes attr, uint8_t ch, uint16_t val)
 
int32_t ad3552r_get_scale (struct ad3552r_desc *desc, uint8_t ch, int32_t *integer, int32_t *dec)
 
int32_t ad3552r_get_offset (struct ad3552r_desc *desc, uint8_t ch, int32_t *integer, int32_t *dec)
 
int32_t ad3552r_ldac_trigger (struct ad3552r_desc *desc, uint16_t mask, uint8_t is_fast)
 
int32_t ad3552r_set_asynchronous (struct ad3552r_desc *desc, uint8_t enable)
 
int32_t ad3552r_write_samples (struct ad3552r_desc *desc, uint16_t *data, uint32_t samples, uint32_t ch_mask, enum ad3552r_write_mode mode)
 
int32_t ad3552r_simulatneous_update_enable (struct ad3552r_desc *desc)
 
int32_t ad3552r_axi_write_data (struct ad3552r_desc *desc, uint32_t *buf, uint16_t samples, bool cyclic, int cyclic_secs)
 Write data samples to dac. More...
 

Detailed Description

Header file of ad3552r Driver.

IIO Header file of ad3552r Driver.

Author
Mihail Chindris (Mihai.nosp@m.l.Ch.nosp@m.indri.nosp@m.s@an.nosp@m.alog..nosp@m.com)

Copyright 2021(c) Analog Devices, Inc.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
  2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  3. Neither the name of Analog Devices, Inc. nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Macro Definition Documentation

◆ AD3552R_BOTH_CH_DESELECT

#define AD3552R_BOTH_CH_DESELECT   0x0

◆ AD3552R_BOTH_CH_SELECT

#define AD3552R_BOTH_CH_SELECT   (NO_OS_BIT(0) | NO_OS_BIT(1))

◆ AD3552R_CH_OUTPUT_RANGE_CUSTOM

#define AD3552R_CH_OUTPUT_RANGE_CUSTOM   100

◆ AD3552R_LDAC_PULSE_US

#define AD3552R_LDAC_PULSE_US   1

◆ AD3552R_MASK_ADDR_ASCENSION

#define AD3552R_MASK_ADDR_ASCENSION   NO_OS_BIT(5)

◆ AD3552R_MASK_ALERT_ENABLE_PULLUP

#define AD3552R_MASK_ALERT_ENABLE_PULLUP   NO_OS_BIT(6)

◆ AD3552R_MASK_ALL_CH

#define AD3552R_MASK_ALL_CH   (NO_OS_BIT(0) | NO_OS_BIT(1))

◆ AD3552R_MASK_CH

#define AD3552R_MASK_CH (   ch)    NO_OS_BIT(ch)

◆ AD3552R_MASK_CH_AMPLIFIER_POWERDOWN

#define AD3552R_MASK_CH_AMPLIFIER_POWERDOWN (   ch)    NO_OS_BIT(ch)

◆ AD3552R_MASK_CH_DAC_POWERDOWN

#define AD3552R_MASK_CH_DAC_POWERDOWN (   ch)    NO_OS_BIT(4 + (ch))

◆ AD3552R_MASK_CH_GAIN_SCALING_N

#define AD3552R_MASK_CH_GAIN_SCALING_N   (NO_OS_BIT(6) | NO_OS_BIT(5))

◆ AD3552R_MASK_CH_GAIN_SCALING_P

#define AD3552R_MASK_CH_GAIN_SCALING_P   (NO_OS_BIT(4) | NO_OS_BIT(3))

◆ AD3552R_MASK_CH_OFFSET_BIT_8

#define AD3552R_MASK_CH_OFFSET_BIT_8   NO_OS_BIT(0)

◆ AD3552R_MASK_CH_OFFSET_BITS_0_7

#define AD3552R_MASK_CH_OFFSET_BITS_0_7   0xFF

◆ AD3552R_MASK_CH_OFFSET_POLARITY

#define AD3552R_MASK_CH_OFFSET_POLARITY   NO_OS_BIT(2)

◆ AD3552R_MASK_CH_OUTPUT_RANGE_SEL

#define AD3552R_MASK_CH_OUTPUT_RANGE_SEL (   ch)    ((ch) ? 0xF0 : 0xF)

◆ AD3552R_MASK_CH_RANGE_OVERRIDE

#define AD3552R_MASK_CH_RANGE_OVERRIDE   NO_OS_BIT(7)

◆ AD3552R_MASK_CLASS

#define AD3552R_MASK_CLASS   NO_OS_GENMASK(7, 0)

◆ AD3552R_MASK_CLOCK_COUNT_ERR_ALARM

#define AD3552R_MASK_CLOCK_COUNT_ERR_ALARM   NO_OS_BIT(5)

◆ AD3552R_MASK_CLOCK_COUNTING_ERROR

#define AD3552R_MASK_CLOCK_COUNTING_ERROR   NO_OS_BIT(5)

◆ AD3552R_MASK_CRC_ENABLE

#define AD3552R_MASK_CRC_ENABLE   (NO_OS_BIT(7) | NO_OS_BIT(6) | NO_OS_BIT(1) | NO_OS_BIT(0))

◆ AD3552R_MASK_CUSTOM_MODES

#define AD3552R_MASK_CUSTOM_MODES   (NO_OS_BIT(3) | NO_OS_BIT(2))

◆ AD3552R_MASK_DAC_12B

#define AD3552R_MASK_DAC_12B   0xFFF0

◆ AD3552R_MASK_DEVICE_REVISION

#define AD3552R_MASK_DEVICE_REVISION   NO_OS_GENMASK(3, 0)

◆ AD3552R_MASK_DEVICE_STATUS

#define AD3552R_MASK_DEVICE_STATUS (   n)    NO_OS_BIT(4 + (n))

◆ AD3552R_MASK_DUAL_SPI_STREAM_EXCEEDS_DAC_ERR_STATUS

#define AD3552R_MASK_DUAL_SPI_STREAM_EXCEEDS_DAC_ERR_STATUS   NO_OS_BIT(5)

◆ AD3552R_MASK_DUAL_SPI_SYNCHROUNOUS_EN

#define AD3552R_MASK_DUAL_SPI_SYNCHROUNOUS_EN   NO_OS_BIT(1)

◆ AD3552R_MASK_GRADE

#define AD3552R_MASK_GRADE   NO_OS_GENMASK(7, 4)

◆ AD3552R_MASK_IDUMP_FAST_MODE

#define AD3552R_MASK_IDUMP_FAST_MODE   NO_OS_BIT(6)

◆ AD3552R_MASK_INTERFACE_NOT_READY

#define AD3552R_MASK_INTERFACE_NOT_READY   NO_OS_BIT(7)

◆ AD3552R_MASK_INVALID_OR_NO_CRC

#define AD3552R_MASK_INVALID_OR_NO_CRC   NO_OS_BIT(3)

◆ AD3552R_MASK_LENGTH

#define AD3552R_MASK_LENGTH   0xFF

◆ AD3552R_MASK_MEM_CRC_EN

#define AD3552R_MASK_MEM_CRC_EN   NO_OS_BIT(4)

◆ AD3552R_MASK_MEM_CRC_ERR_ALARM

#define AD3552R_MASK_MEM_CRC_ERR_ALARM   NO_OS_BIT(4)

◆ AD3552R_MASK_MEM_CRC_ERR_STATUS

#define AD3552R_MASK_MEM_CRC_ERR_STATUS   NO_OS_BIT(4)

◆ AD3552R_MASK_MULTI_IO_MODE

#define AD3552R_MASK_MULTI_IO_MODE   (NO_OS_BIT(7) | NO_OS_BIT(6))

◆ AD3552R_MASK_OPERATING_MODES

#define AD3552R_MASK_OPERATING_MODES   NO_OS_GENMASK(1, 0)

◆ AD3552R_MASK_PARTIAL_REGISTER_ACCESS

#define AD3552R_MASK_PARTIAL_REGISTER_ACCESS   NO_OS_BIT(1)

◆ AD3552R_MASK_PARTIAL_REGISTER_ACCESS_ALARM

#define AD3552R_MASK_PARTIAL_REGISTER_ACCESS_ALARM   NO_OS_BIT(1)

◆ AD3552R_MASK_REF_RANGE_ALARM

#define AD3552R_MASK_REF_RANGE_ALARM   NO_OS_BIT(6)

◆ AD3552R_MASK_REF_RANGE_ERR_STATUS

#define AD3552R_MASK_REF_RANGE_ERR_STATUS   NO_OS_BIT(6)

◆ AD3552R_MASK_REFERENCE_VOLTAGE_SEL

#define AD3552R_MASK_REFERENCE_VOLTAGE_SEL   (NO_OS_BIT(1) | NO_OS_BIT(0))

◆ AD3552R_MASK_REGISTER_ADDRESS_INVALID

#define AD3552R_MASK_REGISTER_ADDRESS_INVALID   NO_OS_BIT(0)

◆ AD3552R_MASK_REGISTER_ADDRESS_INVALID_ALARM

#define AD3552R_MASK_REGISTER_ADDRESS_INVALID_ALARM   NO_OS_BIT(0)

◆ AD3552R_MASK_RESET_STATUS

#define AD3552R_MASK_RESET_STATUS   NO_OS_BIT(0)

◆ AD3552R_MASK_SAMPLE_HOLD_DIFFERENTIAL_USER_EN

#define AD3552R_MASK_SAMPLE_HOLD_DIFFERENTIAL_USER_EN   NO_OS_BIT(5)

◆ AD3552R_MASK_SAMPLE_HOLD_USER_ENABLE

#define AD3552R_MASK_SAMPLE_HOLD_USER_ENABLE   NO_OS_BIT(2)

◆ AD3552R_MASK_SAMPLE_HOLD_USER_TRIM

#define AD3552R_MASK_SAMPLE_HOLD_USER_TRIM   (NO_OS_BIT(4) | NO_OS_BIT(3))

◆ AD3552R_MASK_SDO_ACTIVE

#define AD3552R_MASK_SDO_ACTIVE   NO_OS_BIT(4)

◆ AD3552R_MASK_SDO_DRIVE_STRENGTH

#define AD3552R_MASK_SDO_DRIVE_STRENGTH   (NO_OS_BIT(3) | NO_OS_BIT(2))

◆ AD3552R_MASK_SHORT_INSTRUCTION

#define AD3552R_MASK_SHORT_INSTRUCTION   NO_OS_BIT(3)

◆ AD3552R_MASK_SINGLE_INST

#define AD3552R_MASK_SINGLE_INST   NO_OS_BIT(7)

◆ AD3552R_MASK_SOFTWARE_RESET

#define AD3552R_MASK_SOFTWARE_RESET   (NO_OS_BIT(7) | NO_OS_BIT(0))

◆ AD3552R_MASK_SPI_CONFIG_DDR

#define AD3552R_MASK_SPI_CONFIG_DDR   NO_OS_BIT(0)

◆ AD3552R_MASK_SPI_CRC_ERR_ALARM

#define AD3552R_MASK_SPI_CRC_ERR_ALARM   NO_OS_BIT(3)

◆ AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE

#define AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE   NO_OS_BIT(2)

◆ AD3552R_MASK_STRICT_REGISTER_ACCESS

#define AD3552R_MASK_STRICT_REGISTER_ACCESS   NO_OS_BIT(5)

◆ AD3552R_MASK_WRITE_TO_READ_ONLY_ALARM

#define AD3552R_MASK_WRITE_TO_READ_ONLY_ALARM   NO_OS_BIT(2)

◆ AD3552R_MASK_WRITE_TO_READ_ONLY_REGISTER

#define AD3552R_MASK_WRITE_TO_READ_ONLY_REGISTER   NO_OS_BIT(2)

◆ AD3552R_MAX_NUM_CH

#define AD3552R_MAX_NUM_CH   2

◆ AD3552R_MAX_OFFSET

#define AD3552R_MAX_OFFSET   511

◆ AD3552R_REAL_BITS_FAST_MODE

#define AD3552R_REAL_BITS_FAST_MODE   12

◆ AD3552R_REAL_BITS_PREC_MODE

#define AD3552R_REAL_BITS_PREC_MODE   16

◆ AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE

#define AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE   0x19

◆ AD3552R_REG_ADDR_CH_DAC_16B

#define AD3552R_REG_ADDR_CH_DAC_16B (   ch)    (0x2C - (1 - ch) * 2)

◆ AD3552R_REG_ADDR_CH_DAC_24B

#define AD3552R_REG_ADDR_CH_DAC_24B (   ch)    (0x3D - (1 - ch) * 3)

◆ AD3552R_REG_ADDR_CH_GAIN

#define AD3552R_REG_ADDR_CH_GAIN (   ch)    (0x1C + (ch) * 2)

◆ AD3552R_REG_ADDR_CH_INPUT_16B

#define AD3552R_REG_ADDR_CH_INPUT_16B (   ch)    (0x36 - (1 - ch) * 2)

◆ AD3552R_REG_ADDR_CH_INPUT_24B

#define AD3552R_REG_ADDR_CH_INPUT_24B (   ch)    (0x4B - (1 - ch) * 3)

◆ AD3552R_REG_ADDR_CH_OFFSET

#define AD3552R_REG_ADDR_CH_OFFSET (   ch)    (0x1B + (ch) * 2)

◆ AD3552R_REG_ADDR_CH_SELECT_16B

#define AD3552R_REG_ADDR_CH_SELECT_16B   0x2F

◆ AD3552R_REG_ADDR_CH_SELECT_24B

#define AD3552R_REG_ADDR_CH_SELECT_24B   0x41

◆ AD3552R_REG_ADDR_CHIP_GRADE

#define AD3552R_REG_ADDR_CHIP_GRADE   0x06

◆ AD3552R_REG_ADDR_CHIP_TYPE

#define AD3552R_REG_ADDR_CHIP_TYPE   0x03

◆ AD3552R_REG_ADDR_DAC_PAGE_MASK_16B

#define AD3552R_REG_ADDR_DAC_PAGE_MASK_16B   0x2E

◆ AD3552R_REG_ADDR_DAC_PAGE_MASK_24B

#define AD3552R_REG_ADDR_DAC_PAGE_MASK_24B   0x40

◆ AD3552R_REG_ADDR_DEVICE_CONFIG

#define AD3552R_REG_ADDR_DEVICE_CONFIG   0x02

◆ AD3552R_REG_ADDR_ERR_ALARM_MASK

#define AD3552R_REG_ADDR_ERR_ALARM_MASK   0x16

◆ AD3552R_REG_ADDR_ERR_STATUS

#define AD3552R_REG_ADDR_ERR_STATUS   0x17

◆ AD3552R_REG_ADDR_HW_LDAC_16B

#define AD3552R_REG_ADDR_HW_LDAC_16B   0x28

◆ AD3552R_REG_ADDR_HW_LDAC_24B

#define AD3552R_REG_ADDR_HW_LDAC_24B   0x37

◆ AD3552R_REG_ADDR_INPUT_PAGE_MASK_16B

#define AD3552R_REG_ADDR_INPUT_PAGE_MASK_16B   0x31

◆ AD3552R_REG_ADDR_INPUT_PAGE_MASK_24B

#define AD3552R_REG_ADDR_INPUT_PAGE_MASK_24B   0x44

◆ AD3552R_REG_ADDR_INTERFACE_CONFIG_A

#define AD3552R_REG_ADDR_INTERFACE_CONFIG_A   0x00

◆ AD3552R_REG_ADDR_INTERFACE_CONFIG_B

#define AD3552R_REG_ADDR_INTERFACE_CONFIG_B   0x01

◆ AD3552R_REG_ADDR_INTERFACE_CONFIG_C

#define AD3552R_REG_ADDR_INTERFACE_CONFIG_C   0x10

◆ AD3552R_REG_ADDR_INTERFACE_CONFIG_D

#define AD3552R_REG_ADDR_INTERFACE_CONFIG_D   0x14

◆ AD3552R_REG_ADDR_INTERFACE_STATUS_A

#define AD3552R_REG_ADDR_INTERFACE_STATUS_A   0x11

◆ AD3552R_REG_ADDR_MAX

#define AD3552R_REG_ADDR_MAX   0x4B

◆ AD3552R_REG_ADDR_POWERDOWN_CONFIG

#define AD3552R_REG_ADDR_POWERDOWN_CONFIG   0x18

◆ AD3552R_REG_ADDR_PRODUCT_ID_H

#define AD3552R_REG_ADDR_PRODUCT_ID_H   0x05

◆ AD3552R_REG_ADDR_PRODUCT_ID_L

#define AD3552R_REG_ADDR_PRODUCT_ID_L   0x04

◆ AD3552R_REG_ADDR_SCRATCH_PAD

#define AD3552R_REG_ADDR_SCRATCH_PAD   0x0A

◆ AD3552R_REG_ADDR_SH_REFERENCE_CONFIG

#define AD3552R_REG_ADDR_SH_REFERENCE_CONFIG   0x15

◆ AD3552R_REG_ADDR_SPI_REVISION

#define AD3552R_REG_ADDR_SPI_REVISION   0x0B

◆ AD3552R_REG_ADDR_STREAM_MODE

#define AD3552R_REG_ADDR_STREAM_MODE   0x0E

◆ AD3552R_REG_ADDR_SW_LDAC_16B

#define AD3552R_REG_ADDR_SW_LDAC_16B   0x32

◆ AD3552R_REG_ADDR_SW_LDAC_24B

#define AD3552R_REG_ADDR_SW_LDAC_24B   0x45

◆ AD3552R_REG_ADDR_TRANSFER_REGISTER

#define AD3552R_REG_ADDR_TRANSFER_REGISTER   0x0F

◆ AD3552R_REG_ADDR_VENDOR_H

#define AD3552R_REG_ADDR_VENDOR_H   0x0D

◆ AD3552R_REG_ADDR_VENDOR_L

#define AD3552R_REG_ADDR_VENDOR_L   0x0C

◆ AD3552R_REG_START_24B

#define AD3552R_REG_START_24B   0x37

◆ AD3552R_SECONDARY_REGION_START

#define AD3552R_SECONDARY_REGION_START   0x28

◆ AD3552R_STORAGE_BITS_FAST_MODE

#define AD3552R_STORAGE_BITS_FAST_MODE   16

◆ AD3552R_STORAGE_BITS_PREC_MODE

#define AD3552R_STORAGE_BITS_PREC_MODE   24

Enumeration Type Documentation

◆ ad3542r_ch_output_range

enum ad3542r_ch_output_range
Enumerator
AD3542R_CH_OUTPUT_RANGE_0__2P5V 
AD3542R_CH_OUTPUT_RANGE_0__5V 
AD3542R_CH_OUTPUT_RANGE_0__10V 
AD3542R_CH_OUTPUT_RANGE_NEG_5__5V 
AD3542R_CH_OUTPUT_RANGE_NEG_2P5__7P5V 

◆ ad3552r_ch_attributes

enum ad3552r_ch_attributes
Enumerator
AD3552R_CH_DAC_POWERDOWN 
AD3552R_CH_AMPLIFIER_POWERDOWN 
AD3552R_CH_OUTPUT_RANGE_SEL 
AD3552R_CH_RANGE_OVERRIDE 
AD3552R_CH_GAIN_OFFSET 
AD3552R_CH_GAIN_OFFSET_POLARITY 
AD3552R_CH_GAIN_SCALING_P 
AD3552R_CH_GAIN_SCALING_N 
AD3552R_CH_TRIGGER_SOFTWARE_LDAC 
AD3552R_CH_HW_LDAC_MASK 
AD3552R_CH_RFB 
AD3552R_CH_FAST_EN 
AD3552R_CH_SELECT 
AD3552R_CH_CODE 

◆ ad3552r_ch_gain_scaling

enum ad3552r_ch_gain_scaling
Enumerator
AD3552R_CH_GAIN_SCALING_1 
AD3552R_CH_GAIN_SCALING_0_5 
AD3552R_CH_GAIN_SCALING_0_25 
AD3552R_CH_GAIN_SCALING_0_125 

◆ ad3552r_ch_output_range

enum ad3552r_ch_output_range
Enumerator
AD3552R_CH_OUTPUT_RANGE_0__2P5V 
AD3552R_CH_OUTPUT_RANGE_0__5V 
AD3552R_CH_OUTPUT_RANGE_0__10V 
AD3552R_CH_OUTPUT_RANGE_NEG_5__5V 
AD3552R_CH_OUTPUT_RANGE_NEG_10__10V 

◆ ad3552r_ch_vref_select

enum ad3552r_ch_vref_select
Enumerator
AD3552R_INTERNAL_VREF_PIN_FLOATING 
AD3552R_INTERNAL_VREF_PIN_2P5V 
AD3552R_EXTERNAL_VREF_PIN_INPUT 

◆ ad3552r_dev_attributes

enum ad3552r_dev_attributes
Enumerator
AD3552R_SDO_DRIVE_STRENGTH 
AD3552R_VREF_SELECT 
AD3552R_CRC_ENABLE 

◆ ad3552r_id

enum ad3552r_id
Enumerator
AD3541R_ID 
AD3542R_ID 
AD3551R_ID 
AD3552R_ID 

◆ ad3552r_offset_polarity

enum ad3552r_offset_polarity
Enumerator
AD3552R_OFFSET_POLARITY_POSITIVE 
AD3552R_OFFSET_POLARITY_NEGATIVE 

◆ ad3552r_sdio_drive_strength

enum ad3552r_sdio_drive_strength
Enumerator
AD3552R_LOW_SDIO_DRIVE_STRENGTH 
AD3552R_MEDIUM_LOW_SDIO_DRIVE_STRENGTH 
AD3552R_MEDIUM_HIGH_SDIO_DRIVE_STRENGTH 
AD3552R_HIGH_SDIO_DRIVE_STRENGTH 

◆ ad3552r_status

enum ad3552r_status
Enumerator
AD3552R_RESET_STATUS 
AD3552R_INTERFACE_NOT_READY 
AD3552R_CLOCK_COUNTING_ERROR 
AD3552R_INVALID_OR_NO_CRC 
AD3552R_WRITE_TO_READ_ONLY_REGISTER 
AD3552R_PARTIAL_REGISTER_ACCESS 
AD3552R_REGISTER_ADDRESS_INVALID 
AD3552R_REF_RANGE_ERR_STATUS 
AD3552R_DUAL_SPI_STREAM_EXCEEDS_DAC_ERR_STATUS 
AD3552R_MEM_CRC_ERR_STATUS 

◆ ad3552r_write_mode

enum ad3552r_write_mode
Enumerator
AD3552R_WRITE_DAC_REGS 
AD3552R_WRITE_INPUT_REGS 
AD3552R_WRITE_INPUT_REGS_AND_TRIGGER_LDAC 

◆ num_channels

enum num_channels
Enumerator
AD3541R_NUM_CHANNELS 
AD3542R_NUM_CHANNELS 
AD3551R_NUM_CHANNELS 
AD3552R_NUM_CHANNELS 

Function Documentation

◆ ad3552r_axi_write_data()

int32_t ad3552r_axi_write_data ( struct ad3552r_desc *  desc,
uint32_t *  buf,
uint16_t  samples,
bool  cyclic,
int  cyclic_secs 
)

Write data samples to dac.

Parameters
desc- The device structure.
buf- The buffer to fill.
samples- number of samples to write.
cyclic- cyclic transfer.
cyclic_secs- 0 means forever.
Returns
0 in case of success, negative error code otherwise.
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◆ ad3552r_get_ch_value()

int32_t ad3552r_get_ch_value ( struct ad3552r_desc *  desc,
enum ad3552r_ch_attributes  attr,
uint8_t  ch,
uint16_t *  val 
)

◆ ad3552r_get_code_reg_addr()

uint8_t ad3552r_get_code_reg_addr ( uint8_t  ch,
uint8_t  is_dac,
uint8_t  is_fast 
)

◆ ad3552r_get_dev_value()

int32_t ad3552r_get_dev_value ( struct ad3552r_desc *  desc,
enum ad3552r_dev_attributes  attr,
uint16_t *  val 
)

◆ ad3552r_get_offset()

int32_t ad3552r_get_offset ( struct ad3552r_desc *  desc,
uint8_t  ch,
int32_t *  integer,
int32_t *  dec 
)

◆ ad3552r_get_scale()

int32_t ad3552r_get_scale ( struct ad3552r_desc *  desc,
uint8_t  ch,
int32_t *  integer,
int32_t *  dec 
)

◆ ad3552r_get_status()

int32_t ad3552r_get_status ( struct ad3552r_desc *  desc,
uint32_t *  status,
uint8_t  clr_err 
)

◆ ad3552r_init()

int32_t ad3552r_init ( struct ad3552r_desc **  desc,
struct ad3552r_init_param *  init_param 
)
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◆ ad3552r_ldac_trigger()

int32_t ad3552r_ldac_trigger ( struct ad3552r_desc *  desc,
uint16_t  mask,
uint8_t  is_fast 
)
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◆ ad3552r_read_reg()

int32_t ad3552r_read_reg ( struct ad3552r_desc *  desc,
uint8_t  addr,
uint16_t *  val 
)

◆ ad3552r_reg_len()

uint8_t ad3552r_reg_len ( uint8_t  addr)
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◆ ad3552r_remove()

int32_t ad3552r_remove ( struct ad3552r_desc *  desc)
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◆ ad3552r_reset()

int32_t ad3552r_reset ( struct ad3552r_desc *  desc)
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◆ ad3552r_set_asynchronous()

int32_t ad3552r_set_asynchronous ( struct ad3552r_desc *  desc,
uint8_t  enable 
)

◆ ad3552r_set_ch_value()

int32_t ad3552r_set_ch_value ( struct ad3552r_desc *  desc,
enum ad3552r_ch_attributes  attr,
uint8_t  ch,
uint16_t  val 
)

◆ ad3552r_set_dev_value()

int32_t ad3552r_set_dev_value ( struct ad3552r_desc *  desc,
enum ad3552r_dev_attributes  attr,
uint16_t  val 
)
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◆ ad3552r_simulatneous_update_enable()

int32_t ad3552r_simulatneous_update_enable ( struct ad3552r_desc *  desc)

◆ ad3552r_transfer()

int32_t ad3552r_transfer ( struct ad3552r_desc *  desc,
struct ad3552_transfer_data *  data 
)
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◆ ad3552r_write_reg()

int32_t ad3552r_write_reg ( struct ad3552r_desc *  desc,
uint8_t  addr,
uint16_t  val 
)
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◆ ad3552r_write_samples()

int32_t ad3552r_write_samples ( struct ad3552r_desc *  desc,
uint16_t *  data,
uint32_t  samples,
uint32_t  ch_mask,
enum ad3552r_write_mode  mode 
)
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