ad4110.h File Reference

Header file of AD4110 Driver. More...

#include <stdint.h>
#include <stdbool.h>
#include "no_os_delay.h"
#include "no_os_gpio.h"
#include "no_os_spi.h"
#include "no_os_irq.h"

Include dependency graph for ad4110.h:

Classes
struct	ad4110_dev
struct	ad4110_init_param
struct	ad4110_callback_ctx

Macros
#define	AD4110_CMD_WR_COM_REG(x)
#define	AD4110_CMD_READ_COM_REG(x)
#define	AD4110_DEV_ADDR_MASK   (0x30)
#define	A4110_ADC   0x00
#define	A4110_AFE   0x01
#define	AD4110_REG_AFE_TOP_STATUS   0x0
#define	AD4110_REG_AFE_CNTRL1   0x1
#define	AD4110_REG_AFE_CLK_CTRL   0x3
#define	AD4110_REG_AFE_CNTRL2   0x4
#define	AD4110_REG_PGA_RTD_CTRL   0x5
#define	AD4110_REG_AFE_ERR_DISABLE   0x6
#define	AD4110_REG_AFE_DETAIL_STATUS   0x7
#define	AD4110_REG_AFE_CAL_DATA   0xC
#define	AD4110_REG_AFE_RSENSE_DATA   0xD
#define	AD4110_REG_AFE_NO_PWR_DEFAULT_SEL   0xE
#define	AD4110_REG_AFE_NO_PWR_DEFAULT_STATUS   0xF
#define	AD4110_REG_ADC_STATUS   0x0
#define	AD4110_REG_ADC_MODE   0x1
#define	AD4110_REG_ADC_INTERFACE   0x2
#define	AD4110_REG_ADC_CONFIG   0x3
#define	AD4110_REG_DATA   0x4
#define	AD4110_REG_FILTER   0x5
#define	AD4110_REG_ADC_GPIO_CONFIG   0x6
#define	AD4110_REG_ID   0x7
#define	AD4110_ADC_OFFSET0   0x8
#define	AD4110_ADC_OFFSET1   0x9
#define	AD4110_ADC_OFFSET2   0xA
#define	AD4110_ADC_OFFSET3   0xB
#define	AD4110_ADC_GAIN0   0xC
#define	AD4110_ADC_GAIN1   0xD
#define	AD4110_ADC_GAIN2   0xE
#define	AD4110_ADC_GAIN3   0xF
#define	AD4110_REG_AFE_CNTRL1_CRC_EN   (1 << 14)
#define	AD4110_REG_AFE_CNTRL1_DISRTD   (1 << 9)
#define	AD4110_REG_AFE_CLK_CTRL_CFG(x)
#define	AD4110_REG_AFE_CNTRL2_IMODE_MSK   (1 << 1)
#define	AD4110_REG_AFE_CNTRL2_EXT_R_SEL_MSK   (1 << 2)
#define	AD4110_REG_AFE_CNTRL2_EN_FLD_PWR_MSK   (1 << 3)
#define	AD4110_AFE_VBIAS(x)
#define	AD4110_AFE_VBIAS_ON   0x1
#define	AD4110_AFE_VBIAS_DEFAULT_OFF   0x2
#define	AD4110_AFE_VBIAS_OFF   0x3
#define	AD4110_REG_AFE_CNTRL2_AINP_UP1   (1 << 8)
#define	AD4110_REG_AFE_CNTRL2_AINP_UP100   (1 << 9)
#define	AD4110_REG_AFE_CNTRL2_AINP_DN1   (1 << 10)
#define	AD4110_REG_AFE_CNTRL2_AINP_DN100   (1 << 11)
#define	AD4110_REG_AFE_CNTRL2_AINN_UP1   (1 << 12)
#define	AD4110_REG_AFE_CNTRL2_AINN_UP100   (1 << 13)
#define	AD4110_REG_AFE_CNTRL2_AINN_DN1   (1 << 14)
#define	AD4110_REG_AFE_CNTRL2_AINN_DN100   (1 << 15)
#define	AD4110_REG_PGA_RTD_CTRL_23W_EN_MSK   (1 << 15)
#define	AD4110_REG_PGA_RTD_CTRL_I_COM_SEL(x)
#define	AD4110_REG_PGA_RTD_CTRL_I_EXC_SEL(x)
#define	AD4110_REG_PGA_RTD_CTRL_EXT_RTD   (1 << 8)
#define	AD4110_REG_PGA_RTD_CTRL_GAIN_CH(x)
#define	AD4110_REG_PGA_RTD_CTRL_GAIN_CH_MSK   0xF0
#define	AD4110_REG_AFE_ERR_DIS_AIN_OC   (1 << 1)
#define	AD4110_REG_AFE_ERR_DIS_FLD_PWR_OC   (1 << 2)
#define	AD4110_REG_AFE_ERR_DIS_I_COM   (1 << 6)
#define	AD4110_REG_AFE_ERR_DIS_I_EXC   (1 << 7)
#define	AD4110_REG_AFE_ERR_DIS_AINP_OV   (1 << 8)
#define	AD4110_REG_AFE_ERR_DIS_AINN_OV   (1 << 9)
#define	AD4110_REG_AFE_ERR_DIS_AINP_UV   (1 << 10)
#define	AD4110_REG_AFE_ERR_DIS_AINN_UV   (1 << 11)
#define	AD4110_REG_NO_PWR_DEFAULT_SEL_MSK   0xFF
#define	AD4110_REG_ADC_STATUS_RDY   (1 << 7)
#define	AD4110_REG_ADC_MODE_MSK   0x70
#define	AD4110_ADC_MODE(x)
#define	AD4110_REG_ADC_MODE_REF_EN   (1 << 15)
#define	AD4110_REG_ADC_DELAY(x)
#define	AD4110_REG_ADC_CLK_SEL(x)
#define	AD4110_REG_ADC_INTERFACE_CRC_EN_MSK   0x0C
#define	AD4110_ADC_CRC_EN(x)
#define	AD4110_REG_ADC_INTERFACE_WL16_MSK   0x01
#define	AD4110_REG_ADC_INTERFACE_DS_MSK   0x40
#define	AD4110_DATA_STAT_EN   (1 << 6)
#define	AD4110_REG_ADC_CONFIG_CHAN_EN_MSK   0xF
#define	AD4110_REG_ADC_CONFIG_CHAN_EN_0   (1 << 0)
#define	AD4110_REG_ADC_CONFIG_CHAN_EN_1   (1 << 1)
#define	AD4110_REG_ADC_CONFIG_CHAN_EN_2   (1 << 2)
#define	AD4110_REG_ADC_CONFIG_CHAN_EN_3   (1 << 3)
#define	AD4110_REG_ADC_CONFIG_REF_SEL(x)
#define	AD4110_REG_ADC_CONFIG_BIT_6   (1 << 6)
#define	AD4110_REG_ADC_CONFIG_AIN_BUFF(x)
#define	AD4110_REG_ADC_CONFIG_BI_UNIPOLAR   (1 << 12)
#define	AD4110_REG_ADC_FILTER_ODR(x)
#define	AD4110_REG_ADC_FILTER_ORDER(x)
#define	AD4110_REG_ADC_FILTER_SEL_ENH(x)
#define	AD4110_REG_ADC_FILTER_EN_ENH   (1 << 11)
#define	AD4110_REG_GPIO_CONFIG_ERR_EN(x)
#define	AD4110_REG_GPIO_CONFIG_SYNC_EN(x)
#define	AD4110_CRC8_POLY   0x07
#define	AD4110_ADC_CONV_TIMEOUT   10000

Enumerations
enum	ad4110_adc_clk_sel {   AD4110_ADC_INT_CLK ,   AD4110_ADC_INT_CLK_CLKIO ,   AD4110_ADC_EXT_CLK }
enum	ad4110_afe_clk_cfg {   AD4110_AFE_INT_CLOCK = 0 ,   AD4110_AFE_ADC_CLOCKED = 2 }
enum	ad4110_sync_en {   AD4110_SYNC_DIS ,   AD4110_SYNC_EN }
enum	ad4110_voltage_reference {   AD4110_EXT_REF = 0 ,   AD4110_INT_2_5V_REF = 2 ,   AD4110_AVDD5_REF = 3 }
enum	ad4110_state {   AD4110_DISABLE ,   AD4110_ENABLE }
enum	ad4110_data_word_length {   AD4110_DATA_WL24 ,   AD4110_DATA_WL16 }
enum	ad4110_adc_mode {   AD4110_CONTINOUS_CONV_MODE = 0 ,   AD4110_SINGLE_CONV_MODE = 1 ,   AD4110_STANDBY_MODE = 2 ,   AD4110_PW_DOWN_MODE = 3 ,   AD4110_SYS_OFFSET_CAL = 6 ,   AD4110_SYS_GAIN_CAL = 7 }
enum	ad4110_op_mode {   AD4110_VOLTAGE_MODE ,   AD4110_CURRENT_MODE ,   AD4110_CURRENT_MODE_EXT_R_SEL ,   AD4110_THERMOCOUPLE ,   AD4110_FLD_POWER_MODE ,   AD4110_RTD_2W_MODE ,   AD4110_RTD_3W_MODE ,   AD4110_RTD_4W_MODE }
enum	ad4110_adc_crc_mode {   AD4110_ADC_CRC_DISABLE ,   AD4110_ADC_XOR_CRC ,   AD4110_ADC_CRC_CRC }
enum	ad4110_afe_crc_mode {   AD4110_AFE_CRC_DISABLE ,   AD4110_AFE_CRC }
enum	ad4110_gain {   AD4110_GAIN_0_2 ,   AD4110_GAIN_0_25 ,   AD4110_GAIN_0_3 ,   AD4110_GAIN_0_375 ,   AD4110_GAIN_0_5 ,   AD4110_GAIN_0_75 ,   AD4110_GAIN_1 ,   AD4110_GAIN_1_5 ,   AD4110_GAIN_2 ,   AD4110_GAIN_3 ,   AD4110_GAIN_4 ,   AD4110_GAIN_6 ,   AD4110_GAIN_8 ,   AD4110_GAIN_12 ,   AD4110_GAIN_16 ,   AD4110_GAIN_24 }
enum	ad4110_ain_buffer {   DISABLE_AIN_BUFFER ,   ENABLE_NEG_BUFFER ,   ENABLE_POS_BUFFER ,   ENABLE_FULL_BUFFER }
enum	ad4110_odr {   KSPS_125_A ,   KSPS_125_B ,   KSPS_62P5_A ,   KSPS_62P5_B ,   KSPS_31P25 ,   KSPS_25 ,   KSPS_15P625 ,   KSPS_10P417 ,   KSPS_5 ,   KSPS_2P5 ,   KSPS_1 ,   SPS_500 ,   SPS_400P6 ,   SPS_200 ,   SPS_100P2 ,   SPS_60 ,   SPS_50 ,   SPS_20 ,   SPS_16P7 ,   SPS_10 ,   SPS_5 }
enum	ad4110_order {   sinc5_sinc1 = 0x0 ,   sinc3 = 0x3 }

Functions
uint8_t	ad4110_compute_crc8 (uint8_t *data, uint8_t data_size)
uint8_t	ad4110_compute_xor (uint8_t *data, uint8_t data_size)
int32_t	ad4110_spi_int_reg_write_msk (struct ad4110_dev *dev, uint8_t reg_map, uint8_t reg_addr, uint32_t data, uint16_t mask)
int32_t	ad4110_set_adc_mode (struct ad4110_dev *dev, enum ad4110_adc_mode mode)
int32_t	ad4110_set_gain (struct ad4110_dev *dev, enum ad4110_gain gain)
int32_t	ad4110_set_adc_clk (struct ad4110_dev *dev, enum ad4110_adc_clk_sel clk)
int32_t	ad4110_set_afe_clk (struct ad4110_dev *dev, enum ad4110_afe_clk_cfg clk)
int32_t	ad4110_set_reference (struct ad4110_dev *dev, enum ad4110_voltage_reference ref)
int32_t	ad4110_set_op_mode (struct ad4110_dev *dev, enum ad4110_op_mode mode)
int32_t	ad4110_spi_do_soft_reset (struct ad4110_dev *dev)
uint8_t	ad4110_get_data_size (struct ad4110_dev *dev, uint8_t reg_map, uint8_t reg_addr)
int32_t	ad4110_spi_int_reg_write (struct ad4110_dev *dev, uint8_t reg_map, uint8_t reg_addr, uint32_t reg_data)
int32_t	ad4110_spi_int_reg_read (struct ad4110_dev *dev, uint8_t reg_map, uint8_t reg_addr, uint32_t *reg_data)
int32_t	ad4110_continuous_read (struct ad4110_dev *dev, uint32_t *buffer, uint32_t buffer_size)
int32_t	ad4110_spi_int_data_reg_read (struct ad4110_dev *dev, uint32_t *reg_data)
int32_t	ad4110_setup (struct ad4110_dev **device, struct ad4110_init_param init_param)
int	ad4110_set_channel_status (struct ad4110_dev *dev, uint8_t chan_id, bool status)
	Enable/Disable channel.
int	ad4110_set_analog_input_buffer (struct ad4110_dev *dev, enum ad4110_ain_buffer buffer)
	Assign analog input buffer.
int	ad4110_set_bipolar (struct ad4110_dev *dev, bool bipolar)
	Set polarity.
int	ad4110_set_odr (struct ad4110_dev *dev, enum ad4110_odr odr)
	Set Output Data Rate.
int	ad4110_set_order (struct ad4110_dev *dev, enum ad4110_order order)
	Set Order of Filter.
int	ad4110_do_single_read (struct ad4110_dev *dev, uint32_t *buffer)
	ADC data read in single conversion mode.
int	ad4110_wait_for_rdy_low (struct ad4110_dev *dev, uint32_t timeout)
	Wait for RDY bit to go low indicating conversion completion.

Detailed Description

Header file of AD4110 Driver.

Author

Stefan Popa (stefa.nosp@m.n.po.nosp@m.pa@an.nosp@m.alog.nosp@m..com) Andrei Porumb (andre.nosp@m.i.po.nosp@m.rumb@.nosp@m.anal.nosp@m.og.co.nosp@m.m) Mihail Chindris (mihai.nosp@m.l.ch.nosp@m.indri.nosp@m.s@an.nosp@m.alog..nosp@m.com)

Copyright 2021(c) Analog Devices, Inc.

SPDX-License-Identifier: BSD-3-Clause

Macro Definition Documentation

A4110_ADC

#define A4110_ADC   0x00

A4110_AFE

#define A4110_AFE   0x01

AD4110_ADC_CONV_TIMEOUT

#define AD4110_ADC_CONV_TIMEOUT   10000

AD4110_ADC_CRC_EN

#define AD4110_ADC_CRC_EN

(

x

)

Value:

(((x) & 0x3) << 2)

AD4110_ADC_GAIN0

#define AD4110_ADC_GAIN0   0xC

AD4110_ADC_GAIN1

#define AD4110_ADC_GAIN1   0xD

AD4110_ADC_GAIN2

#define AD4110_ADC_GAIN2   0xE

AD4110_ADC_GAIN3

#define AD4110_ADC_GAIN3   0xF

AD4110_ADC_MODE

#define AD4110_ADC_MODE

(

x

)

Value:

(((x) & 0x7) << 4)

AD4110_ADC_OFFSET0

#define AD4110_ADC_OFFSET0   0x8

AD4110_ADC_OFFSET1

#define AD4110_ADC_OFFSET1   0x9

AD4110_ADC_OFFSET2

#define AD4110_ADC_OFFSET2   0xA

AD4110_ADC_OFFSET3

#define AD4110_ADC_OFFSET3   0xB

AD4110_AFE_VBIAS

#define AD4110_AFE_VBIAS

(

x

)

Value:

(((x) & 0x3) << 6)

AD4110_AFE_VBIAS_DEFAULT_OFF

#define AD4110_AFE_VBIAS_DEFAULT_OFF   0x2

AD4110_AFE_VBIAS_OFF

#define AD4110_AFE_VBIAS_OFF   0x3

AD4110_AFE_VBIAS_ON

#define AD4110_AFE_VBIAS_ON   0x1

AD4110_CMD_READ_COM_REG

#define AD4110_CMD_READ_COM_REG

(

x

)

Value:

(0x40 | ((x) & 0xF))

AD4110_CMD_WR_COM_REG

#define AD4110_CMD_WR_COM_REG

(

x

)

Value:

(0x00 | ((x) & 0xF))

AD4110_CRC8_POLY

#define AD4110_CRC8_POLY   0x07

AD4110_DATA_STAT_EN

#define AD4110_DATA_STAT_EN   (1 << 6)

AD4110_DEV_ADDR_MASK

#define AD4110_DEV_ADDR_MASK   (0x30)

AD4110_REG_ADC_CLK_SEL

#define AD4110_REG_ADC_CLK_SEL

(

x

)

Value:

(((x) & 0x3) << 2)

AD4110_REG_ADC_CONFIG

#define AD4110_REG_ADC_CONFIG   0x3

AD4110_REG_ADC_CONFIG_AIN_BUFF

#define AD4110_REG_ADC_CONFIG_AIN_BUFF

(

x

)

Value:

((((x) & 0x3) << 8))

AD4110_REG_ADC_CONFIG_BI_UNIPOLAR

#define AD4110_REG_ADC_CONFIG_BI_UNIPOLAR   (1 << 12)

AD4110_REG_ADC_CONFIG_BIT_6

#define AD4110_REG_ADC_CONFIG_BIT_6   (1 << 6)

AD4110_REG_ADC_CONFIG_CHAN_EN_0

#define AD4110_REG_ADC_CONFIG_CHAN_EN_0   (1 << 0)

AD4110_REG_ADC_CONFIG_CHAN_EN_1

#define AD4110_REG_ADC_CONFIG_CHAN_EN_1   (1 << 1)

AD4110_REG_ADC_CONFIG_CHAN_EN_2

#define AD4110_REG_ADC_CONFIG_CHAN_EN_2   (1 << 2)

AD4110_REG_ADC_CONFIG_CHAN_EN_3

#define AD4110_REG_ADC_CONFIG_CHAN_EN_3   (1 << 3)

AD4110_REG_ADC_CONFIG_CHAN_EN_MSK

#define AD4110_REG_ADC_CONFIG_CHAN_EN_MSK   0xF

AD4110_REG_ADC_CONFIG_REF_SEL

#define AD4110_REG_ADC_CONFIG_REF_SEL

(

x

)

Value:

(((x) & 0x3) << 4)

AD4110_REG_ADC_DELAY

#define AD4110_REG_ADC_DELAY

(

x

)

Value:

(((x) & 0x7) << 8)

AD4110_REG_ADC_FILTER_EN_ENH

#define AD4110_REG_ADC_FILTER_EN_ENH   (1 << 11)

AD4110_REG_ADC_FILTER_ODR

#define AD4110_REG_ADC_FILTER_ODR

(

x

)

Value:

(((x) & 0x1F) << 0)

AD4110_REG_ADC_FILTER_ORDER

#define AD4110_REG_ADC_FILTER_ORDER

(

x

)

Value:

(((x) & 0x3) << 5)

AD4110_REG_ADC_FILTER_SEL_ENH

#define AD4110_REG_ADC_FILTER_SEL_ENH

(

x

)

Value:

(((x) & 0x7) << 8)

AD4110_REG_ADC_GPIO_CONFIG

#define AD4110_REG_ADC_GPIO_CONFIG   0x6

AD4110_REG_ADC_INTERFACE

#define AD4110_REG_ADC_INTERFACE   0x2

AD4110_REG_ADC_INTERFACE_CRC_EN_MSK

#define AD4110_REG_ADC_INTERFACE_CRC_EN_MSK   0x0C

AD4110_REG_ADC_INTERFACE_DS_MSK

#define AD4110_REG_ADC_INTERFACE_DS_MSK   0x40

AD4110_REG_ADC_INTERFACE_WL16_MSK

#define AD4110_REG_ADC_INTERFACE_WL16_MSK   0x01

AD4110_REG_ADC_MODE

#define AD4110_REG_ADC_MODE   0x1

AD4110_REG_ADC_MODE_MSK

#define AD4110_REG_ADC_MODE_MSK   0x70

AD4110_REG_ADC_MODE_REF_EN

#define AD4110_REG_ADC_MODE_REF_EN   (1 << 15)

AD4110_REG_ADC_STATUS

#define AD4110_REG_ADC_STATUS   0x0

AD4110_REG_ADC_STATUS_RDY

#define AD4110_REG_ADC_STATUS_RDY   (1 << 7)

AD4110_REG_AFE_CAL_DATA

#define AD4110_REG_AFE_CAL_DATA   0xC

AD4110_REG_AFE_CLK_CTRL

#define AD4110_REG_AFE_CLK_CTRL   0x3

AD4110_REG_AFE_CLK_CTRL_CFG

#define AD4110_REG_AFE_CLK_CTRL_CFG

(

x

)

Value:

(((x) & 0x3) << 3)

AD4110_REG_AFE_CNTRL1

#define AD4110_REG_AFE_CNTRL1   0x1

AD4110_REG_AFE_CNTRL1_CRC_EN

#define AD4110_REG_AFE_CNTRL1_CRC_EN   (1 << 14)

AD4110_REG_AFE_CNTRL1_DISRTD

#define AD4110_REG_AFE_CNTRL1_DISRTD   (1 << 9)

AD4110_REG_AFE_CNTRL2

#define AD4110_REG_AFE_CNTRL2   0x4

AD4110_REG_AFE_CNTRL2_AINN_DN1

#define AD4110_REG_AFE_CNTRL2_AINN_DN1   (1 << 14)

AD4110_REG_AFE_CNTRL2_AINN_DN100

#define AD4110_REG_AFE_CNTRL2_AINN_DN100   (1 << 15)

AD4110_REG_AFE_CNTRL2_AINN_UP1

#define AD4110_REG_AFE_CNTRL2_AINN_UP1   (1 << 12)

AD4110_REG_AFE_CNTRL2_AINN_UP100

#define AD4110_REG_AFE_CNTRL2_AINN_UP100   (1 << 13)

AD4110_REG_AFE_CNTRL2_AINP_DN1

#define AD4110_REG_AFE_CNTRL2_AINP_DN1   (1 << 10)

AD4110_REG_AFE_CNTRL2_AINP_DN100

#define AD4110_REG_AFE_CNTRL2_AINP_DN100   (1 << 11)

AD4110_REG_AFE_CNTRL2_AINP_UP1

#define AD4110_REG_AFE_CNTRL2_AINP_UP1   (1 << 8)

AD4110_REG_AFE_CNTRL2_AINP_UP100

#define AD4110_REG_AFE_CNTRL2_AINP_UP100   (1 << 9)

AD4110_REG_AFE_CNTRL2_EN_FLD_PWR_MSK

#define AD4110_REG_AFE_CNTRL2_EN_FLD_PWR_MSK   (1 << 3)

AD4110_REG_AFE_CNTRL2_EXT_R_SEL_MSK

#define AD4110_REG_AFE_CNTRL2_EXT_R_SEL_MSK   (1 << 2)

AD4110_REG_AFE_CNTRL2_IMODE_MSK

#define AD4110_REG_AFE_CNTRL2_IMODE_MSK   (1 << 1)

AD4110_REG_AFE_DETAIL_STATUS

#define AD4110_REG_AFE_DETAIL_STATUS   0x7

AD4110_REG_AFE_ERR_DIS_AIN_OC

#define AD4110_REG_AFE_ERR_DIS_AIN_OC   (1 << 1)

AD4110_REG_AFE_ERR_DIS_AINN_OV

#define AD4110_REG_AFE_ERR_DIS_AINN_OV   (1 << 9)

AD4110_REG_AFE_ERR_DIS_AINN_UV

#define AD4110_REG_AFE_ERR_DIS_AINN_UV   (1 << 11)

AD4110_REG_AFE_ERR_DIS_AINP_OV

#define AD4110_REG_AFE_ERR_DIS_AINP_OV   (1 << 8)

AD4110_REG_AFE_ERR_DIS_AINP_UV

#define AD4110_REG_AFE_ERR_DIS_AINP_UV   (1 << 10)

AD4110_REG_AFE_ERR_DIS_FLD_PWR_OC

#define AD4110_REG_AFE_ERR_DIS_FLD_PWR_OC   (1 << 2)

AD4110_REG_AFE_ERR_DIS_I_COM

#define AD4110_REG_AFE_ERR_DIS_I_COM   (1 << 6)

AD4110_REG_AFE_ERR_DIS_I_EXC

#define AD4110_REG_AFE_ERR_DIS_I_EXC   (1 << 7)

AD4110_REG_AFE_ERR_DISABLE

#define AD4110_REG_AFE_ERR_DISABLE   0x6

AD4110_REG_AFE_NO_PWR_DEFAULT_SEL

#define AD4110_REG_AFE_NO_PWR_DEFAULT_SEL   0xE

AD4110_REG_AFE_NO_PWR_DEFAULT_STATUS

#define AD4110_REG_AFE_NO_PWR_DEFAULT_STATUS   0xF

AD4110_REG_AFE_RSENSE_DATA

#define AD4110_REG_AFE_RSENSE_DATA   0xD

AD4110_REG_AFE_TOP_STATUS

#define AD4110_REG_AFE_TOP_STATUS   0x0

AD4110_REG_DATA

#define AD4110_REG_DATA   0x4

AD4110_REG_FILTER

#define AD4110_REG_FILTER   0x5

AD4110_REG_GPIO_CONFIG_ERR_EN

#define AD4110_REG_GPIO_CONFIG_ERR_EN

(

x

)

Value:

(((x) & 0x3) << 9)

AD4110_REG_GPIO_CONFIG_SYNC_EN

#define AD4110_REG_GPIO_CONFIG_SYNC_EN

(

x

)

Value:

(((x) & 0x1) << 11)

AD4110_REG_ID

#define AD4110_REG_ID   0x7

AD4110_REG_NO_PWR_DEFAULT_SEL_MSK

#define AD4110_REG_NO_PWR_DEFAULT_SEL_MSK   0xFF

AD4110_REG_PGA_RTD_CTRL

#define AD4110_REG_PGA_RTD_CTRL   0x5

AD4110_REG_PGA_RTD_CTRL_23W_EN_MSK

#define AD4110_REG_PGA_RTD_CTRL_23W_EN_MSK   (1 << 15)

AD4110_REG_PGA_RTD_CTRL_EXT_RTD

#define AD4110_REG_PGA_RTD_CTRL_EXT_RTD   (1 << 8)

AD4110_REG_PGA_RTD_CTRL_GAIN_CH

#define AD4110_REG_PGA_RTD_CTRL_GAIN_CH

(

x

)

Value:

(((x) & 0xF) << 4)

AD4110_REG_PGA_RTD_CTRL_GAIN_CH_MSK

#define AD4110_REG_PGA_RTD_CTRL_GAIN_CH_MSK   0xF0

AD4110_REG_PGA_RTD_CTRL_I_COM_SEL

#define AD4110_REG_PGA_RTD_CTRL_I_COM_SEL

(

x

)

Value:

(((x) & 0x7) << 12)

AD4110_REG_PGA_RTD_CTRL_I_EXC_SEL

#define AD4110_REG_PGA_RTD_CTRL_I_EXC_SEL

(

x

)

Value:

(((x) & 0x7) << 9)

Enumeration Type Documentation

ad4110_adc_clk_sel

enum ad4110_adc_clk_sel

Enumerator
AD4110_ADC_INT_CLK
AD4110_ADC_INT_CLK_CLKIO
AD4110_ADC_EXT_CLK

ad4110_adc_crc_mode

enum ad4110_adc_crc_mode

Enumerator
AD4110_ADC_CRC_DISABLE
AD4110_ADC_XOR_CRC
AD4110_ADC_CRC_CRC

ad4110_adc_mode

enum ad4110_adc_mode

Enumerator
AD4110_CONTINOUS_CONV_MODE
AD4110_SINGLE_CONV_MODE
AD4110_STANDBY_MODE
AD4110_PW_DOWN_MODE
AD4110_SYS_OFFSET_CAL
AD4110_SYS_GAIN_CAL

ad4110_afe_clk_cfg

enum ad4110_afe_clk_cfg

Enumerator
AD4110_AFE_INT_CLOCK
AD4110_AFE_ADC_CLOCKED

ad4110_afe_crc_mode

enum ad4110_afe_crc_mode

Enumerator
AD4110_AFE_CRC_DISABLE
AD4110_AFE_CRC

ad4110_ain_buffer

enum ad4110_ain_buffer

Enumerator
DISABLE_AIN_BUFFER
ENABLE_NEG_BUFFER
ENABLE_POS_BUFFER
ENABLE_FULL_BUFFER

ad4110_data_word_length

enum ad4110_data_word_length

Enumerator
AD4110_DATA_WL24
AD4110_DATA_WL16

ad4110_gain

enum ad4110_gain

Enumerator
AD4110_GAIN_0_2
AD4110_GAIN_0_25
AD4110_GAIN_0_3
AD4110_GAIN_0_375
AD4110_GAIN_0_5
AD4110_GAIN_0_75
AD4110_GAIN_1
AD4110_GAIN_1_5
AD4110_GAIN_2
AD4110_GAIN_3
AD4110_GAIN_4
AD4110_GAIN_6
AD4110_GAIN_8
AD4110_GAIN_12
AD4110_GAIN_16
AD4110_GAIN_24

ad4110_odr

enum ad4110_odr

Enumerator
KSPS_125_A
KSPS_125_B
KSPS_62P5_A
KSPS_62P5_B
KSPS_31P25
KSPS_25
KSPS_15P625
KSPS_10P417
KSPS_5
KSPS_2P5
KSPS_1
SPS_500
SPS_400P6
SPS_200
SPS_100P2
SPS_60
SPS_50
SPS_20
SPS_16P7
SPS_10
SPS_5

ad4110_op_mode

enum ad4110_op_mode

Enumerator
AD4110_VOLTAGE_MODE
AD4110_CURRENT_MODE
AD4110_CURRENT_MODE_EXT_R_SEL
AD4110_THERMOCOUPLE
AD4110_FLD_POWER_MODE
AD4110_RTD_2W_MODE
AD4110_RTD_3W_MODE
AD4110_RTD_4W_MODE

ad4110_order

enum ad4110_order

Enumerator
sinc5_sinc1
sinc3

ad4110_state

enum ad4110_state

Enumerator
AD4110_DISABLE
AD4110_ENABLE

ad4110_sync_en

enum ad4110_sync_en

Enumerator
AD4110_SYNC_DIS
AD4110_SYNC_EN

ad4110_voltage_reference

enum ad4110_voltage_reference

Enumerator
AD4110_EXT_REF
AD4110_INT_2_5V_REF
AD4110_AVDD5_REF

Function Documentation

ad4110_compute_crc8()

uint8_t ad4110_compute_crc8	(	uint8_t *	data,
		uint8_t	data_size )

Compute CRC8 checksum.

Parameters

data	- The data buffer.
data_size	- The size of the data buffer.

Returns

CRC8 checksum.

ad4110_compute_xor()

uint8_t ad4110_compute_xor	(	uint8_t *	data,
		uint8_t	data_size )

Compute XOR checksum.

Parameters

data	- The data buffer.
data_size	- The size of the data buffer.

Returns

XOR checksum.

ad4110_continuous_read()

int32_t ad4110_continuous_read	(	struct ad4110_dev *	dev,
		uint32_t *	buffer,
		uint32_t	buffer_size )

ADC continuous read fills buffer with buffer_size number of samples.

Parameters

dev	- The device structure.
buffer	- The buffer.
buffer_size	- The buffer size = number of samples.

Returns

0 in case of success, negative error code otherwise.

ad4110_do_single_read()

int ad4110_do_single_read	(	struct ad4110_dev *	dev,
		uint32_t *	buffer )

ADC data read in single conversion mode.

Parameters

dev	- The device structure.
buffer	- The data buffer.

Returns

0 in case of success, negative error code otherwise.

ad4110_get_data_size()

uint8_t ad4110_get_data_size	(	struct ad4110_dev *	dev,
		uint8_t	reg_map,
		uint8_t	reg_addr )

Get the data size of a specified register.

Parameters

dev	- The device structure.
reg_map	- The register map. Accepted values: A4110_ADC A4110_AFE
reg_addr	- The register address.

Returns

the data size in bytes

ad4110_set_adc_clk()

int32_t ad4110_set_adc_clk	(	struct ad4110_dev *	dev,
		enum ad4110_adc_clk_sel	clk )

Set ADC clock.

Parameters

dev	- The device structure.
clk	- The clock mode. Accepted values: AD4110_ADC_INT_CLK AD4110_ADC_INT_CLK_CLKIO AD4110_ADC_EXT_CLK

Returns

0 in case of success, negative error code otherwise.

ad4110_set_adc_mode()

int32_t ad4110_set_adc_mode	(	struct ad4110_dev *	dev,
		enum ad4110_adc_mode	mode )

Set the mode of the ADC.

Parameters

dev	- The device structure.
mode	- The ADC mode Accepted values: AD4110_CONTINOUS_CONV_MODE AD4110_SINGLE_CONV_MODE AD4110_STANDBY_MODE AD4110_PW_DOWN_MODE AD4110_SYS_OFFSET_CAL AD4110_SYS_GAIN_CAL

Returns

0 in case of success, negative error code otherwise.

ad4110_set_afe_clk()

int32_t ad4110_set_afe_clk	(	struct ad4110_dev *	dev,
		enum ad4110_afe_clk_cfg	clk )

Set AFE clock.

Parameters

dev	- The device structure.
clk	- The clock mode. Accepted values: AD4110_AFE_INT_CLOCK AD4110_AFE_ADC_CLOCKED

Returns

0 in case of success, negative error code otherwise.

ad4110_set_analog_input_buffer()

int ad4110_set_analog_input_buffer	(	struct ad4110_dev *	dev,
		enum ad4110_ain_buffer	buffer )

Assign analog input buffer.

Parameters

dev	- The device structure.
buffer	- Choice of analog input buffer to be set

Returns

0 in case of success, negative error code otherwise.

ad4110_set_bipolar()

int ad4110_set_bipolar	(	struct ad4110_dev *	dev,
		bool	bipolar )

Set polarity.

Parameters

dev	- The device structure.
bipolar	- True in case of Bipolar/ False in case of Unipolar

Returns

0 in case of success, negative error code otherwise.

ad4110_set_channel_status()

int ad4110_set_channel_status	(	struct ad4110_dev *	dev,
		uint8_t	chan_id,
		bool	status )

Enable/Disable channel.

Parameters

dev	- The device structure.
chan_id	- Channel ID (number)
status	- Channel Status (True for Enable and False for Disable)

Returns

0 in case of success, negative error code otherwise.

ad4110_set_gain()

int32_t ad4110_set_gain	(	struct ad4110_dev *	dev,
		enum ad4110_gain	gain )

Set the gain.

Parameters

dev	- The device structure.
gain	- The gain value. Accepted values: AD4110_GAIN_0_2 AD4110_GAIN_0_25 AD4110_GAIN_0_3 AD4110_GAIN_0_375 AD4110_GAIN_0_5 AD4110_GAIN_0_75 AD4110_GAIN_1 AD4110_GAIN_1_5 AD4110_GAIN_2 AD4110_GAIN_3 AD4110_GAIN_4 AD4110_GAIN_6 AD4110_GAIN_8 AD4110_GAIN_12 AD4110_GAIN_16 AD4110_GAIN_24

Returns

0 in case of success, negative error code otherwise.

ad4110_set_odr()

int ad4110_set_odr	(	struct ad4110_dev *	dev,
		enum ad4110_odr	odr )

Set Output Data Rate.

Parameters

dev	- The device structure.
odr	- Choice of ODR to be set

Returns

0 in case of success, negative error code otherwise.

ad4110_set_op_mode()

int32_t ad4110_set_op_mode	(	struct ad4110_dev *	dev,
		enum ad4110_op_mode	mode )

Set the operation mode.

Parameters

dev	- The device structure.
mode	- The operation mode type. Accepted values: AD4110_VOLTAGE_MODE AD4110_CURRENT_MODE AD4110_CURRENT_MODE_EXT_R_SEL AD4110_THERMOCOUPLE AD4110_FLD_POWER_MODE AD4110_RTD_2W_MODE AD4110_RTD_3W_MODE AD4110_RTD_4W_MODE

Returns

0 in case of success, negative error code otherwise.

ad4110_set_order()

int ad4110_set_order	(	struct ad4110_dev *	dev,
		enum ad4110_order	order )

Set Order of Filter.

Parameters

dev	- The device structure.
order	- Choice of order to be set

Returns

0 in case of success, negative error code otherwise.

ad4110_set_reference()

int32_t ad4110_set_reference	(	struct ad4110_dev *	dev,
		enum ad4110_voltage_reference	ref )

Set the voltage reference.

Parameters

dev	- The device structure.
ref	- The voltage reference. Accepted values: AD4110_EXT_REF AD4110_INT_2_5V_REF AD4110_AVDD5_REF

Returns

0 in case of success, negative error code otherwise.

ad4110_setup()

int32_t ad4110_setup	(	struct ad4110_dev **	device,
		struct ad4110_init_param	init_param )

Initialize the device.

Parameters

device	- The device structure.
init_param	- The structure that contains the device initial parameters.

Returns

0 in case of success, negative error code otherwise.

ad4110_spi_do_soft_reset()

int32_t ad4110_spi_do_soft_reset

(

struct ad4110_dev *

dev

)

Do a SPI software reset.

Parameters

dev	- The device structure.

Returns

0 in case of success, negative error code otherwise.

ad4110_spi_int_data_reg_read()

int32_t ad4110_spi_int_data_reg_read	(	struct ad4110_dev *	dev,
		uint32_t *	reg_data )

SPI internal DATA register read from device.

Parameters

dev	- The device structure.
reg_data	- The register data.

Returns

0 in case of success, negative error code otherwise.

ad4110_spi_int_reg_read()

int32_t ad4110_spi_int_reg_read	(	struct ad4110_dev *	dev,
		uint8_t	reg_map,
		uint8_t	reg_addr,
		uint32_t *	reg_data )

SPI internal register read from device.

Parameters

dev	- The device structure.
reg_map	- The register map. Accepted values: A4110_ADC A4110_AFE
reg_addr	- The register address.
reg_data	- The register data.

Returns

0 in case of success, negative error code otherwise.

ad4110_spi_int_reg_write()

int32_t ad4110_spi_int_reg_write	(	struct ad4110_dev *	dev,
		uint8_t	reg_map,
		uint8_t	reg_addr,
		uint32_t	reg_data )

SPI internal register write to device.

Parameters

dev	- The device structure.
reg_map	- The register map. Accepted values: A4110_ADC A4110_AFE
reg_addr	- The register address.
reg_data	- The register data.

Returns

0 in case of success, negative error code otherwise.

ad4110_spi_int_reg_write_msk()

int32_t ad4110_spi_int_reg_write_msk	(	struct ad4110_dev *	dev,
		uint8_t	reg_map,
		uint8_t	reg_addr,
		uint32_t	data,
		uint16_t	mask )

SPI internal register write to device using a mask.

Parameters

dev	- The device structure.
reg_map	- The register map. Accepted values: A4110_ADC A4110_AFE
reg_addr	- The register address.
data	- The register data.
mask	- The mask.

Returns

0 in case of success, negative error code otherwise.

ad4110_wait_for_rdy_low()

int ad4110_wait_for_rdy_low	(	struct ad4110_dev *	dev,
		uint32_t	timeout )

Wait for RDY bit to go low indicating conversion completion.

Parameters

dev	- The device structure.
timeout	- ADC conversion timeout

Returns

0 in case of success, negative error code otherwise.