ad4170.h

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/***************************************************************************/
#ifndef AD4170_H_
#define AD4170_H_
 
#include <stdint.h>
#include <stdbool.h>
#include "no_os_util.h"
#include "no_os_gpio.h"
#include "no_os_spi.h"
 
#ifndef ECOMM
#define ECOMM 70
#endif
 
#define AD4170_R1B              (1ul << 16)
#define AD4170_R2B              (2ul << 16)
#define AD4170_R3B              (3ul << 16)
#define AD4170_R4B              (4ul << 16)
#define AD4170_TRANSF_LEN(x)            ((x) >> 16)
#define AD4170_ADDR(x)              ((x) & 0xFFFF)
 
#define AD4170_SPI_SYNC_PATTERN         0x2645
 
#define AD4170_REG_READ_6(x)            (((x) & 0x3F) | 0x40)
#define AD4170_REG_WRITE_6(x)           ((x) & 0x3F)
#define AD4170_REG_READ_14(x)           (((x) & 0x3FFF) | 0x4000)
#define AD4170_REG_WRITE_14(x)          ((x) & 0x3FFF)
#define AD4170_REG_INTERFACE_CONFIG_A       (AD4170_R1B | 0x00)
#define AD4170_REG_INTERFACE_CONFIG_B       (AD4170_R1B | 0x01)
#define AD4170_REG_DEVICE_CONFIG        (AD4170_R1B | 0x02)
#define AD4170_REG_CHIP_TYPE            (AD4170_R1B | 0x03)
#define AD4170_REG_PRODUCT_ID_L         (AD4170_R1B | 0x04)
#define AD4170_REG_PRODUCT_ID_H         (AD4170_R1B | 0x05)
#define AD4170_REG_CHIP_GRADE           (AD4170_R1B | 0x06)
#define AD4170_REG_SCRATCH_PAD          (AD4170_R1B | 0x0a)
#define AD4170_REG_SPI_REVISION         (AD4170_R1B | 0x0b)
#define AD4170_REG_VENDOR_L         (AD4170_R1B | 0x0c)
#define AD4170_REG_VENDOR_H         (AD4170_R1B | 0x0d)
#define AD4170_REG_INTERFACE_CONFIG_C       (AD4170_R1B | 0x10)
#define AD4170_REG_INTERFACE_STATUS_A       (AD4170_R1B | 0x11)
#define AD4170_REG_DATA_STATUS          (AD4170_R2B | 0x14)
#define AD4170_REG_DATA_16b         (AD4170_R2B | 0x16)
#define AD4170_REG_DATA_16b_STATUS      (AD4170_R3B | 0x18)
#define AD4170_REG_DATA_24b         (AD4170_R3B | 0x1c)
#define AD4170_REG_DATA_24b_STATUS      (AD4170_R4B | 0x20)
#define AD4170_REG_DATA_32b         (AD4170_R4B | 0x24)
#define AD4170_REG_DATA_PER_CHANNEL(ch)     (AD4170_R3B | (0x28 + 4 * (ch)))
#define AD4170_REG_PIN_MUXING           (AD4170_R2B | 0x68)
#define AD4170_REG_CLOCK_CTRL           (AD4170_R2B | 0x6a)
#define AD4170_REG_STANDBY_CTRL         (AD4170_R2B | 0x6c)
#define AD4170_REG_POWER_DOWN_SW        (AD4170_R2B | 0x6e)
#define AD4170_REG_ADC_CTRL         (AD4170_R2B | 0x70)
#define AD4170_REG_ERROR_EN         (AD4170_R2B | 0x72)
#define AD4170_REG_ERROR            (AD4170_R2B | 0x74)
#define AD4170_REG_CHANNEL_EN           (AD4170_R2B | 0x78)
#define AD4170_REG_ADC_CHANNEL_SETUP(ch)    (AD4170_R2B | (0x80 + 4 * (ch)))
#define AD4170_REG_ADC_CHANNEL_MAP(ch)      (AD4170_R2B | (0x82 + 4 * (ch)))
#define AD4170_REG_ADC_SETUPS_MISC(n)       (AD4170_R2B | (0xc0 + 14 * (n)))
#define AD4170_REG_ADC_SETUPS_AFE(n)        (AD4170_R2B | (0xc2 + 14 * (n)))
#define AD4170_REG_ADC_SETUPS_FILTER(n)     (AD4170_R2B | (0xc4 + 14 * (n)))
#define AD4170_REG_ADC_SETUPS_FILTER_FS(n)  (AD4170_R2B | (0xc6 + 14 * (n)))
#define AD4170_REG_ADC_SETUPS_OFFSET(n)     (AD4170_R3B | (0xc8 + 14 * (n)))
#define AD4170_REG_ADC_SETUPS_GAIN(n)       (AD4170_R3B | (0xcb + 14 * (n)))
#define AD4170_REG_REF_CONTROL          (AD4170_R2B | 0x130)
#define AD4170_REG_V_BIAS           (AD4170_R2B | 0x134)
#define AD4170_REG_I_PULLUP         (AD4170_R2B | 0x136)
#define AD4170_REG_CURRENT_SOURCE(n)        (AD4170_R2B | (0x138 + 2 * (n)))
#define AD4170_REG_FIR_CONTROL          (AD4170_R2B | 0x140)
#define AD4170_REG_COEFF_WRITE_DATA     (AD4170_R4B | 0x143)
#define AD4170_REG_COEFF_READ_DATA      (AD4170_R4B | 0x147)
#define AD4170_REG_COEFF_ADDRESS        (AD4170_R2B | 0x14b)
#define AD4170_REG_COEFF_WRRD_STB       (AD4170_R2B | 0x14d)
#define AD4170_REG_DAC_SPAN         (AD4170_R2B | 0x150)
#define AD4170_REG_DAC_CHANNEL_EN       (AD4170_R2B | 0x152)
#define AD4170_REG_DAC_HW_TOGGLE_MASK       (AD4170_R2B | 0x154)
#define AD4170_REG_DAC_HW_LDAC_MASK     (AD4170_R2B | 0x156)
#define AD4170_REG_DAC_DATA(ch)         (AD4170_R2B | (0x158 + 2 * (ch)))
#define AD4170_REG_DAC_SW_TOGGLE_TRIGGERS   (AD4170_R2B | 0x168)
#define AD4170_REG_DAC_SW_LDAC_TRIGGERS     (AD4170_R2B | 0x16a)
#define AD4170_REG_DAC_INPUTA(ch)       (AD4170_R2B | (0x16c + 2 * (ch)))
#define AD4170_REG_DAC_INPUTB(ch)       (AD4170_R2B | (0x17c + 2 * (ch)))
#define AD4170_REG_GPIO_MODE            (AD4170_R2B | 0x190)
#define AD4170_REG_OUTPUT_DATA          (AD4170_R2B | 0x192)
#define AD4170_REG_INPUT_DATA           (AD4170_R2B | 0x194)
 
/* AD4170_REG_INTERFACE_CONFIG_A */
#define AD4170_SW_RESET_MSK                 NO_OS_BIT(7)
#define AD4170_ADDR_ASCENSION_MSK               NO_OS_BIT(5)
#define AD4170_SDO_ENABLE_MSK                   NO_OS_BIT(4)
#define AD4170_SW_RESETX_MSK                    NO_OS_BIT(0)
 
/* AD4170_REG_INTERFACE_CONFIG_B */
#define AD4170_INTERFACE_CONFIG_B_SINGLE_INST_MSK       NO_OS_BIT(7)
#define AD4170_INTERFACE_CONFIG_B_SHORT_INSTRUCTION_MSK     NO_OS_BIT(3)
#define AD4170_INTERFACE_CONFIG_B_SHORT_INSTRUCTION(x)      (((x) & 0x1) << 3)
 
/* AD4170_REG_INTERFACE_CONFIG_C */
#define AD4170_INTERFACE_CONFIG_C_CRC_MSK           (NO_OS_BIT(7) | NO_OS_BIT(6) | NO_OS_BIT(1) | NO_OS_BIT(0))
#define AD4170_INTERFACE_CONFIG_C_CRC(x)            (((~x) & 0x3) | (((x) << 6) & 0xC0))
#define AD4170_INTERFACE_CONFIG_C_STRICT_REG_ACCESS_MSK     NO_OS_BIT(5)
#define AD4170_INTERFACE_CONFIG_C_STRICT_REG_ACCESS(x)      (((x) & 0x1) << 5)
#define AD4170_CRC8_POLYNOMIAL                  0x7
#define AD4170_CRC8_INITIAL_VALUE               0xA5
 
/* AD4170_REG_INTERFACE_STATUS_A */
#define AD4170_INTERFACE_STATUS_A_NOT_READY_ERR_MSK     NO_OS_BIT(7)
#define AD4170_INTERFACE_STATUS_A_CLOCK_COUNT_ERR_MSK       NO_OS_BIT(4)
#define AD4170_INTERFACE_STATUS_A_CRC_ERR_MSK           NO_OS_BIT(3)
#define AD4170_INTERFACE_STATUS_A_INVALID_ACCESS_ERR_MSK    NO_OS_BIT(2)
#define AD4170_INTERFACE_STATUS_A_PARTIAL_ACCESS_ERR_MSK    NO_OS_BIT(1)
#define AD4170_INTERFACE_STATUS_A_ADDR_INVALID_ERR_MSK      NO_OS_BIT(0)
 
/* AD4170_REG_PRODUCT_ID */
#define AD4170_PRODUCT_ID_L_VALUE               0x40
#define AD4170_PRODUCT_ID_H_VALUE               0x0
 
/* AD4190_REG_PRODUCT_ID */
#define AD4190_PRODUCT_ID_L_VALUE               0x48
#define AD4190_PRODUCT_ID_H_VALUE               0x0
 
/* AD4190_8_REG_PRODUCT_ID */
#define AD4190_8_PRODUCT_ID_L_VALUE             0x49
#define AD4190_8_PRODUCT_ID_H_VALUE             0x0
 
/* AD4195_8_REG_PRODUCT_ID */
#define AD4195_8_PRODUCT_ID_L_VALUE             0x49
#define AD4195_8_PRODUCT_ID_H_VALUE             0x0
 
/* AD4170_REG_DATA_STATUS */
#define AD4170_DATA_STATUS_MASTER_ERR_S_MSK         NO_OS_BIT(7)
#define AD4170_DATA_STATUS_POR_FLAG_S_MSK           NO_OS_BIT(6)
#define AD4170_DATA_STATUS_RDYB_MSK             NO_OS_BIT(5)
#define AD4170_DATA_STATUS_SETTLED_FIR_MSK          NO_OS_BIT(4)
#define AD4170_DATA_STATUS_CH_ACTIVE_MSK            NO_OS_GENMASK(3,0)
 
/* AD4170_REG_PIN_MUXING */
#define AD4170_PIN_MUXING_CHAN_TO_GPIO_MSK          NO_OS_BIT(14)
#define AD4170_PIN_MUXING_DIG_AUX2_CTRL_MSK         NO_OS_GENMASK(7,6)
#define AD4170_PIN_MUXING_DIG_AUX1_CTRL_MSK         NO_OS_GENMASK(5,4)
#define AD4170_PIN_MUXING_SYNC_CTRL_MSK             NO_OS_GENMASK(3,2)
#define AD4170_PIN_MUXING_DIG_OUT_STR_MSK           NO_OS_BIT(1)
#define AD4170_PIN_MUXING_SDO_RDBY_DLY_MSK          NO_OS_BIT(0)
 
/* AD4170_REG_CLOCK_CTRL */
#define AD4170_CLOCK_CTRL_DCLK_DIVIDE_MSK           NO_OS_GENMASK(7,6)
#define AD4170_CLOCK_CTRL_CLOCKDIV_MSK              NO_OS_GENMASK(5,4)
#define AD4170_CLOCK_CTRL_CLOCKSEL_MSK              NO_OS_GENMASK(1,0)
 
/* AD4170_REG_STANDBY_CTRL */
#define AD4170_STANDBY_CTRL_STB_EN_CLOCK_MSK            NO_OS_BIT(8)
#define AD4170_STANDBY_CTRL_STB_EN_IPULLUP_MSK          NO_OS_BIT(7)
#define AD4170_STANDBY_CTRL_STB_EN_DIAGNOSTICS_MSK      NO_OS_BIT(6)
#define AD4170_STANDBY_CTRL_STB_EN_DAC_MSK          NO_OS_BIT(5)
#define AD4170_STANDBY_CTRL_STB_EN_PDSW1_MSK            NO_OS_BIT(4)
#define AD4170_STANDBY_CTRL_STB_EN_PDSW0_MSK            NO_OS_BIT(3)
#define AD4170_STANDBY_CTRL_STB_EN_VBIAS_MSK            NO_OS_BIT(2)
#define AD4170_STANDBY_CTRL_STB_EN_IEXC_MSK         NO_OS_BIT(1)
#define AD4170_STANDBY_CTRL_STB_EN_REFERENCE_MSK        NO_OS_BIT(0)
 
/* AD4170_REG_POWER_DOWN_SW */
#define AD4170_POWER_DOWN_SW_PDSW1_MSK              NO_OS_BIT(1)
#define AD4170_POWER_DOWN_SW_PDSW0_MSK              NO_OS_BIT(0)
 
/* AD4170_REG_ADC_CTRL */
#define AD4170_ADC_CTRL_PARALLEL_FILT_EN_MSK            NO_OS_BIT(8)
#define AD4170_ADC_CTRL_MULTI_DATA_REG_SEL_MSK          NO_OS_BIT(7)
#define AD4170_ADC_CTRL_CONT_READ_STATUS_EN_MSK         NO_OS_BIT(6)
#define AD4170_REG_CTRL_CONT_READ_MSK               NO_OS_GENMASK(5,4)
#define AD4170_REG_CTRL_MODE_MSK                NO_OS_GENMASK(3,0)
 
/* AD4170_REG_ERROR_EN and AD4170_REG_ERROR */
#define AD4170_ERROR_DEVICE_ERROR_MSK               NO_OS_BIT(15)
#define AD4170_ERROR_DLDO_PSM_ERR_MSK               NO_OS_BIT(13)
#define AD4170_ERROR_ALDO_PSM_ERR_MSK               NO_OS_BIT(12)
#define AD4170_ERROR_IOUT3_COMP_ERR_MSK             NO_OS_BIT(11)
#define AD4170_ERROR_IOUT2_COMP_ERR_MSK             NO_OS_BIT(10)
#define AD4170_ERROR_IOUT1_COMP_ERR_MSK             NO_OS_BIT(9)
#define AD4170_ERROR_IOUT0_COMP_ERR_MSK             NO_OS_BIT(8)
#define AD4170_ERROR_REF_DIFF_MIN_ERR_MSK           NO_OS_BIT(7)
#define AD4170_ERROR_REF_OV_UV_ERR_MSK              NO_OS_BIT(6)
#define AD4170_ERROR_AINM_OV_UV_ERR_MSK             NO_OS_BIT(5)
#define AD4170_ERROR_AINP_OV_UV_ERR_MSK             NO_OS_BIT(4)
#define AD4170_ERROR_ADC_CONV_ERR_MSK               NO_OS_BIT(3)
#define AD4170_ERROR_MM_CRC_ERR_MSK             NO_OS_BIT(1)
#define AD4170_ERROR_ROM_CRC_ERR_MSK                NO_OS_BIT(0)
 
/* AD4170_REG_CHANNEL_EN */
#define AD4170_CHANNEL(ch)                  NO_OS_BIT(ch)
 
/* AD4170_REG_ADC_CHANNEL_SETUP */
#define AD4170_CHANNEL_SETUPN_REPEAT_N_MSK          NO_OS_GENMASK(15,8)
#define AD4170_CHANNEL_SETUPN_DELAY_N_MSK           NO_OS_GENMASK(6,4)
#define AD4170_CHANNEL_SETUPN_SETUP_N_MSK           NO_OS_GENMASK(2,0)
 
/* AD4170_REG_ADC_CHANNEL_MAP */
#define AD4170_CHANNEL_MAPN_AINP_MSK                NO_OS_GENMASK(12,8)
#define AD4170_CHANNEL_MAPN_AINM_MSK                NO_OS_GENMASK(4,0)
 
/* AD4170_REG_ADC_SETUPS_MISC */
#define AD4170_ADC_SETUPS_MISC_CHOP_IEXC_MSK            NO_OS_GENMASK(15,14)
#define AD4170_ADC_SETUPS_MISC_CHOP_ADC_MSK         NO_OS_GENMASK(9,8)
#define AD4170_ADC_SETUPS_MISC_BURNOUT_MSK          NO_OS_GENMASK(1,0)
 
/* AD4170_REG_ADC_SETUPS_AFE */
#define AD4170_ADC_SETUPS_AFE_REF_BUF_M_MSK         NO_OS_GENMASK(11,10)
#define AD4170_ADC_SETUPS_AFE_REF_BUF_P_MSK         NO_OS_GENMASK(9,8)
#define AD4170_ADC_SETUPS_AFE_REF_SELECT_MSK            NO_OS_GENMASK(6,5)
#define AD4170_ADC_SETUPS_AFE_BIPOLAR_MSK           NO_OS_BIT(4)
#define AD4170_ADC_SETUPS_AFE_PGA_GAIN_MSK          NO_OS_GENMASK(3,0)
 
/* AD4170_REG_ADC_SETUPS_FILTER */
#define AD4170_ADC_SETUPS_POST_FILTER_SEL_MSK           NO_OS_GENMASK(7,4)
#define AD4170_ADC_SETUPS_FILTER_TYPE_MSK           NO_OS_GENMASK(3,0)
 
/* AD4170_REG_CURRENT_SOURCE */
#define AD4170_CURRENT_SOURCE_I_OUT_PIN_MSK         NO_OS_GENMASK(12,8)
#define AD4170_CURRENT_SOURCE_I_OUT_VAL_MSK         NO_OS_GENMASK(2,0)
 
/* AD4170_REG_REF_CONTROL */
#define AD4170_REF_CONTROL_REF_EN_MSK               NO_OS_BIT(0)
 
/* AD4170_REG_FIR_CONTROL */
#define AD4170_FIR_CONTROL_IIR_MODE_MSK             NO_OS_BIT(15)
#define AD4170_FIR_CONTROL_FIR_MODE_MSK             NO_OS_GENMASK(14,12)
#define AD4170_FIR_CONTROL_COEFF_SET_MSK            NO_OS_BIT(10)
#define AD4170_FIR_CONTROL_FIR_LENGTH_MSK           NO_OS_GENMASK(6,0)
 
/* AD4170_REG_DAC_SPAN */
#define AD4170_REG_DAC_SPAN_DAC_GAIN_MSK            NO_OS_BIT(0)
 
/* AD4170_REG_DAC_CHANNEL_EN */
#define AD4170_REG_DAC_CHANNEL_EN_DAC_EN_MSK            NO_OS_BIT(0)
 
/* AD4170_REG_DAC_HW_TOGGLE_MASK */
#define AD4170_REG_DAC_HW_TOGGLE_MASK_HW_TOGGLE_EN_MSK      NO_OS_BIT(0)
 
/* AD4170_REG_DAC_HW_LDAC_MASK */
#define AD4170_REG_DAC_HW_LDAC_MASK_HW_LDAC_EN_MSK      NO_OS_BIT(0)
 
/* AD4170_REG_DAC_DATA */
#define AD4170_REG_DAC_DATA_MSK                 NO_OS_GENMASK(11,0)
 
/* AD4170_REG_DAC_SW_TOGGLE_TRIGGERS */
#define AD4170_REG_DAC_SW_TOGGLE_TRIGGERS_SW_TOGGLE_MSK     NO_OS_BIT(0)
 
/* AD4170_REG_DAC_SW_LDAC_TRIGGERS */
#define AD4170_REG_DAC_SW_LDAC_TRIGGERS_SW_LDAC_EN_MSK      NO_OS_BIT(0)
 
#define AD4170_NUM_CHANNELS                 16
#define AD4170_NUM_SETUPS                   8
#define AD4170_NUM_CURRENT_SOURCE               4
#define AD4170_FIR_COEFF_MAX_LENGTH             72

enum ad4170_chan_to_gpio {
    AD4170_CHANNEL_NOT_TO_GPIO,
    AD4170_CHANNEL_TO_GPIO
};

enum ad4170_dig_aux2_ctrl {
    AD4170_DIG_AUX2_DISABLED,
    AD4170_DIG_AUX2_LDAC,
    AD4170_DIG_AUX2_SYNC,
    AD4170_DIG_AUX2_MODOUT
};

enum ad4170_dig_aux1_ctrl {
    AD4170_DIG_AUX1_DISABLED,
    AD4170_DIG_AUX1_RDY,
    AD4170_DIG_AUX1_SYNC,
    AD4170_DIG_AUX1_MODOUT
};

enum ad4170_sync_ctrl {
    AD4170_SYNC_DISABLED,
    AD4170_SYNC_STANDARD,
    AD4170_SYNC_ALTERNATE
};

enum ad4170_dig_out_str {
    AD4170_DIG_STR_DEFAULT,
    AD4170_DIG_STR_HIGH
};

enum ad4170_sdo_rdby_dly {
    AD4170_SDO_RDY_SCLK,
    AD4170_SDO_RDY_CSB
};

struct ad4170_pin_muxing {
    enum ad4170_chan_to_gpio chan_to_gpio;
    enum ad4170_dig_aux2_ctrl dig_aux2_ctrl;
    enum ad4170_dig_aux1_ctrl dig_aux1_ctrl;
    enum ad4170_sync_ctrl sync_ctrl;
    enum ad4170_dig_out_str dig_out_str;
    enum ad4170_sdo_rdby_dly sdo_rdby_dly;
};

enum ad4170_dclk_div {
    AD4170_DCLKDIVBY1,
    AD4170_DCLKDIVBY2,
    AD4170_DCLKDIVBY4,
    AD4170_DCLKDIVBY8
};

enum ad4170_mclk_div {
    AD4170_CLKDIVBY1,
    AD4170_CLKDIVBY2,
    AD4170_CLKDIVBY4,
    AD4170_CLKDIVBY8
};

enum ad4170_clocksel {
    AD4170_INTERNAL_OSC,
    AD4170_INTERNAL_OSC_OUTPUT,
    AD4170_EXTERNAL_OSC,
    AD4170_EXTERNAL_XTAL
};

struct ad4170_clock_ctrl {
    enum ad4170_dclk_div dclk_divide;
    enum ad4170_mclk_div clockdiv;
    enum ad4170_clocksel clocksel;
};

enum ad4170_cont_read {
    AD4170_CONT_READ_OFF,
    AD4170_CONT_READ_ON,
    AD4170_CONT_TRANSMIT_ON
};

enum ad4170_mode {
    AD4170_MODE_CONT,
    AD4170_MODE_CONT_FIR,
    AD4170_MODE_CONT_IIR,
    AD4170_MODE_SINGLE = 0x4,
    AD4170_MODE_STANDBY,
    AD4170_MODE_POWER_DOWN,
    AD4170_MODE_IDLE,
    AD4170_MODE_SYS_OFFSET_CAL,
    AD4170_MODE_SYS_GAIN_CAL,
    AD4170_MODE_SELF_OFFSET_CAL,
    AD4170_MODE_SELF_GAIN_CAL
};

struct ad4170_adc_ctrl {
    bool parallel_filt_en;
    bool multi_data_reg_sel;
    bool cont_read_status_en;
    enum ad4170_cont_read cont_read;
    enum ad4170_mode mode;
};

enum ad4170_delay_n {
    AD4170_DLY_0,
    AD4170_DLY_16,
    AD4170_DLY_256,
    AD4170_DLY_1024,
    AD4170_DLY_2048,
    AD4170_DLY_4096,
    AD4170_DLY_8192,
    AD4170_DLY_16384
};

enum ad4170_ain {
    AD4170_AIN0,
    AD4170_AIN1,
    AD4170_AIN2,
    AD4170_AIN3,
    AD4170_AIN4,
    AD4170_AIN5,
    AD4170_AIN6,
    AD4170_AIN7,
    AD4170_AIN8,
    AD4170_AIN9,
    AD4170_AIN10,
    AD4170_AIN11,
    AD4170_AIN12,
    AD4170_AIN13,
    AD4170_AIN14,
    AD4170_AIN15,
    AD4170_AIN16,
    AD4170_TEMP_SENSOR_P = 17,
    AD4170_TEMP_SENSOR_N = 17,
    AD4170_AVDD_AVSS_P = 18,
    AD4170_AVDD_AVSS_N = 18,
    AD4170_IOVDD_DGND_P = 19,
    AD4170_IOVDD_DGND_N = 19,
    AD4170_DAC,
    AD4170_ALDO,
    AD4170_DLDO,
    AD4170_AVSS,
    AD4170_DGND,
    AD4170_REFIN1_P,
    AD4170_REFIN1_N,
    AD4170_REFIN2_P,
    AD4170_REFIN2_N,
    AD4170_REFOUT,
    AD4170_OPEN = 31
};

struct ad4170_channel_setup {
    uint8_t repeat_n;
    enum ad4170_delay_n delay_n;
    uint8_t setup_n;
};

struct ad4170_channel_map {
    enum ad4170_ain ainp;
    enum ad4170_ain ainm;
};

enum ad4170_chop_iexc {
    AD4170_CHOP_IEXC_OFF,
    AD4170_CHOP_IEXC_AB,
    AD4170_CHOP_IEXC_CD,
    AD4170_CHOP_IEXC_ABCD
};

enum ad4170_chop_adc {
    AD4170_CHOP_OFF,
    AD4170_CHOP_MUX,
    AD4170_CHOP_ACX_4PIN,
    AD4170_CHOP_ACX_2PIN
};

enum ad4170_burnout {
    AD4170_BURNOUT_OFF,
    AD4170_BURNOUT_100N,
    AD4170_BURNOUT_2U,
    AD4170_BURNOUT_10U
};

struct ad4170_misc {
    enum ad4170_chop_iexc chop_iexc;
    enum ad4170_chop_adc chop_adc;
    enum ad4170_burnout burnout;
};

enum ad4170_ref_buf {
    AD4170_REF_BUF_PRE,
    AD4170_REF_BUF_FULL,
    AD4170_REF_BUF_BYPASS
};

enum ad4170_ref_select {
    AD4170_REFIN_REFIN1,
    AD4170_REFIN_REFIN2,
    AD4170_REFIN_REFOUT,
    AD4170_REFIN_AVDD
};

enum ad4170_pga_gain {
    AD4170_PGA_GAIN_1,
    AD4170_PGA_GAIN_2,
    AD4170_PGA_GAIN_4,
    AD4170_PGA_GAIN_8,
    AD4170_PGA_GAIN_16,
    AD4170_PGA_GAIN_32,
    AD4170_PGA_GAIN_64,
    AD4170_PGA_GAIN_128,
    AD4170_PGA_GAIN_0P5,
    AD4170_PGA_GAIN_1_PRECHARGE
};

struct ad4170_afe {
    enum ad4170_ref_buf ref_buf_m;
    enum ad4170_ref_buf ref_buf_p;
    enum ad4170_ref_select ref_select;
    bool bipolar;
    enum ad4170_pga_gain pga_gain;
};

enum ad4170_post_filter {
    AD4170_POST_FILTER_NONE,
    AD4170_POST_FILTER_40MS,
    AD4170_POST_FILTER_50MS,
    AD4170_POST_FILTER_60MS,
    AD4170_POST_FILTER_FAST_AC,
    AD4170_POST_FILTER_AVG16,
    AD4170_POST_FILTER_AVG20,
    AD4170_POST_FILTER_AVG24
};

enum ad4170_filter_type {
    AD4170_FILT_SINC5_AVG = 0x0,
    AD4170_FILT_SINC5 = 0x4,
    AD4170_FILT_SINC3 = 0x6
};

struct ad4170_filter {
    enum ad4170_post_filter post_filter_sel;
    enum ad4170_filter_type filter_type;
};

struct ad4170_setup {
    struct ad4170_misc misc;
    struct ad4170_afe afe;
    struct ad4170_filter filter;
    uint16_t filter_fs;
    uint32_t offset;
    uint32_t gain;
};

struct ad4170_ref_control {
    bool ref_en;
};

enum ad4170_i_out_pin {
    AD4170_I_OUT_AIN0,
    AD4170_I_OUT_AIN1,
    AD4170_I_OUT_AIN2,
    AD4170_I_OUT_AIN3,
    AD4170_I_OUT_AIN4,
    AD4170_I_OUT_AIN5,
    AD4170_I_OUT_AIN6,
    AD4170_I_OUT_AIN7,
    AD4170_I_OUT_AIN8,
    AD4170_I_OUT_AIN9,
    AD4170_I_OUT_AIN10,
    AD4170_I_OUT_AIN11,
    AD4170_I_OUT_AIN12,
    AD4170_I_OUT_AIN13,
    AD4170_I_OUT_AIN14,
    AD4170_I_OUT_AIN15,
    AD4170_I_OUT_AINCOM,
    AD4170_I_OUT_GPIO0,
    AD4170_I_OUT_GPIO1,
    AD4170_I_OUT_GPIO2,
    AD4170_I_OUT_GPIO3
};

enum ad4170_i_out_val {
    AD4170_I_OUT_0UA,
    AD4170_I_OUT_10UA,
    AD4170_I_OUT_50UA,
    AD4170_I_OUT_100UA,
    AD4170_I_OUT_250UA,
    AD4170_I_OUT_500UA,
    AD4170_I_OUT_1000UA,
    AD4170_I_OUT_1500UA
};

struct ad4170_current_source {
    enum ad4170_i_out_pin i_out_pin;
    enum ad4170_i_out_val i_out_val;
};

enum ad4170_fir_mode {
    AD4170_FIR_DEFAULT,
    AD4170_FIR_SYM_ODD,
    AD4170_FIR_SYM_EVEN,
    AD4170_FIR_ANTISYM_ODD,
    AD4170_FIR_ANTISYM_EVEN,
    AD4170_FIR_ASYM
};

enum ad4170_fir_coeff_set {
    /* FIR set 0. Use coefficient addresses 0 to FIR_LENGTH-1 */
    AD4170_FIR_COEFF_SET0,
    /* FIR set 1. Use coefficient addresses 72 to 72 + FIR_LENGTH-1 */
    AD4170_FIR_COEFF_SET1
};

struct ad4170_fir_control {
    enum ad4170_fir_mode fir_mode;
    enum ad4170_fir_coeff_set coeff_set;
    uint8_t fir_length;
    int32_t *fir_coefficients;
};

enum ad4170_dac_gain {
    AD4170_DAC_GAIN_1,
    AD4170_DAC_GAIN_2
};

struct ad4170_dac_config {
    bool enabled;
    enum ad4170_dac_gain gain;
    bool hw_toggle;
    bool hw_ldac;
};

struct ad4170_config {
    struct ad4170_pin_muxing pin_muxing;
    struct ad4170_clock_ctrl clock_ctrl;
    uint16_t standby_ctrl;
    uint16_t powerdown_sw;
    uint16_t error_en;
    struct ad4170_adc_ctrl adc_ctrl;
    uint16_t channel_en;
    struct ad4170_channel_setup setup[AD4170_NUM_CHANNELS];
    struct ad4170_channel_map map[AD4170_NUM_CHANNELS];
    struct ad4170_setup setups[AD4170_NUM_SETUPS];
    struct ad4170_ref_control ref_control;
    uint16_t v_bias;
    uint16_t i_pullup;
    struct ad4170_current_source current_source[AD4170_NUM_CURRENT_SOURCE];
    struct ad4170_fir_control fir_control;
    struct ad4170_dac_config dac;
};

struct ad4170_spi_settings {
    bool short_instruction;
    bool crc_enabled;
    bool sync_loss_detect;
};

enum ad4170_id {
    ID_AD4170,
    ID_AD4171,
    ID_AD4172,
    ID_AD4190,
    ID_AD4195,
    ID_AD4190_8,
    ID_AD4195_8
};

struct ad4170_init_param {
    enum ad4170_id id;
    struct no_os_spi_init_param spi_init;
    struct ad4170_spi_settings spi_settings;
    /* Rdy GPIO (EOC) monitor timeout loop counter */
    uint32_t rdy_conv_timeout;
    struct ad4170_config config;
    struct no_os_gpio_init_param *gpio_sync_inb;
    struct no_os_gpio_init_param *gpio_dig_aux1;
    struct no_os_gpio_init_param *gpio_dig_aux2;
};

struct ad4170_dev {
    enum ad4170_id id;
    struct no_os_spi_init_param spi_init;
    struct no_os_spi_desc *spi_desc;
    struct ad4170_spi_settings spi_settings;
    /* Rdy GPIO (EOC) monitor timeout loop counter */
    uint32_t rdy_conv_timeout;
    bool big_endian;
    struct ad4170_config config;
    struct no_os_gpio_init_param *gpio_sync_inb_init;
    struct no_os_gpio_desc *gpio_sync_inb;
    struct no_os_gpio_init_param *gpio_dig_aux1_init;
    struct no_os_gpio_desc *gpio_dig_aux1;
    struct no_os_gpio_init_param *gpio_dig_aux2_init;
    bool dig_aux2_output;
    struct no_os_gpio_desc *gpio_dig_aux2;
    bool digif;
};

extern struct ad4170_config ad4170_config_reset;
 
int ad4170_spi_reg_read(struct ad4170_dev *dev,
            uint32_t reg_addr,
            uint32_t *reg_data);
int ad4170_spi_reg_write(struct ad4170_dev *dev,
             uint32_t reg_addr,
             uint32_t reg_data);
int ad4170_spi_reg_write_mask(struct ad4170_dev *dev,
                  uint32_t reg_addr,
                  uint8_t mask,
                  uint32_t reg_data);
int ad4170_reset_spi_interface(struct ad4170_dev *dev);
int ad4170_get_data16(struct ad4170_dev *dev, uint16_t *data);
int ad4170_get_data16s(struct ad4170_dev *dev, uint16_t *data,
               uint8_t *status);
int ad4170_get_data24(struct ad4170_dev *dev, uint32_t *data);
int ad4170_get_data24s(struct ad4170_dev *dev, uint32_t *data,
               uint8_t *status);
int ad4170_get_data32(struct ad4170_dev *dev, uint32_t *data);
int ad4170_get_ch_data(struct ad4170_dev *dev, uint8_t ch, uint32_t *data);
int ad4170_read16(struct ad4170_dev *dev, uint32_t *pbuf,
          uint16_t nb_samples);
int ad4170_read16s(struct ad4170_dev *dev, uint32_t *pbuf,
           uint16_t nb_samples);
int ad4170_read24(struct ad4170_dev *dev, uint32_t *pbuf,
          uint16_t nb_samples);
int ad4170_read24s(struct ad4170_dev *dev, uint32_t *pbuf,
           uint16_t nb_samples);
int ad4170_read32(struct ad4170_dev *dev, uint32_t *pbuf,
          uint16_t nb_samples);
int ad4170_continuous_read(struct ad4170_dev *dev, uint32_t *data_out,
               uint8_t *status_out, uint16_t nb_samples);
int ad4170_continuous_read_exit(struct ad4170_dev *dev);
int ad4170_continuous_transmit_exit(struct ad4170_dev *dev);
int ad4170_reset(struct ad4170_dev *dev);
int ad4170_get_status(struct ad4170_dev *dev, uint16_t *status);
int ad4170_set_pin_muxing(struct ad4170_dev *dev,
              struct ad4170_pin_muxing pin_muxing);
int ad4170_set_dclk_div(struct ad4170_dev *dev,
            enum ad4170_dclk_div clk_div);
int ad4170_set_mclk_div(struct ad4170_dev *dev,
            enum ad4170_mclk_div clk_div);
int ad4170_set_clocksel(struct ad4170_dev *dev, enum ad4170_clocksel sel);
int ad4170_set_standby_ctrl(struct ad4170_dev *dev, uint16_t standby_ctrl);
int ad4170_set_powerdown_sw(struct ad4170_dev *dev, uint16_t powerdown_sw);
int ad4170_set_error_en(struct ad4170_dev *dev, uint16_t error_en);
int ad4170_set_error(struct ad4170_dev *dev, uint16_t error);
int ad4170_get_error(struct ad4170_dev *dev, uint16_t *error);
int ad4170_set_adc_ctrl(struct ad4170_dev *dev,
            struct ad4170_adc_ctrl adc_ctrl);
int ad4170_set_channel_en(struct ad4170_dev *dev, uint16_t channel_en);
int ad4170_set_channel_setup(struct ad4170_dev *dev, uint8_t ch,
                 struct ad4170_channel_setup setup);
int ad4170_set_channel_map(struct ad4170_dev *dev, uint8_t ch,
               struct ad4170_channel_map map);
int ad4170_set_setup(struct ad4170_dev *dev, uint8_t n,
             struct ad4170_setup setup);
int ad4170_set_ref_control(struct ad4170_dev *dev, bool enable);
int ad4170_set_v_bias(struct ad4170_dev *dev, uint16_t ch_mask);
int ad4170_set_i_pullup(struct ad4170_dev *dev, uint16_t ch_mask);
int ad4170_set_current_source(struct ad4170_dev *dev, uint8_t n,
                  struct ad4170_current_source current_source);
int ad4170_set_fir_control(struct ad4170_dev *dev,
               struct ad4170_fir_control fir_control);
int ad4170_set_dac_config(struct ad4170_dev *dev,
              struct ad4170_dac_config config);
int ad4170_set_dac_data(struct ad4170_dev *dev, uint16_t code);
int ad4170_set_dac_inputa(struct ad4170_dev *dev, uint16_t code);
int ad4170_set_dac_inputb(struct ad4170_dev *dev, uint16_t code);
int ad4170_dac_sw_ldac(struct ad4170_dev *dev, bool polarity);
int ad4170_dac_sw_toggle(struct ad4170_dev *dev, bool polarity);
int ad4170_dac_hw_toggle(struct ad4170_dev *dev, bool polarity);
int ad4170_init(struct ad4170_dev **device,
        struct ad4170_init_param *init_param);
int ad4170_remove(struct ad4170_dev *dev);
int ad4170_regmap(struct ad4170_dev *dev);
#endif