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parameters.c File Reference

Definition of STM32 platform data used by ad463x_fmcz project. More...

#include "parameters.h"
#include "stm32_dma.h"
#include "no_os_pwm.h"
Include dependency graph for parameters.c:

Variables

DMA_HandleTypeDef hdma_tim8_ch1
 
DMA_HandleTypeDef hdma_spi1_rx
 
struct stm32_uart_init_param ad463x_uart_extra_ip
 
struct no_os_dma_init_param dma_init
 
struct stm32_dma_channel txdma_channel
 
struct stm32_dma_channel rxdma_channel
 
struct stm32_gpio_init_param cnv_pwm_gpio_extra_init_params
 
struct stm32_pwm_init_param cnv_pwm_extra_init_params
 
struct stm32_pwm_init_param cs_pwm_extra_init_params
 
struct no_os_pwm_init_param cs_pwm_init
 
struct stm32_pwm_init_param tx_pwm_extra_init_params
 
struct no_os_pwm_init_param tx_pwm_init
 
struct stm32_spi_init_param ad463x_spi_extra_ip
 

Detailed Description

Definition of STM32 platform data used by ad463x_fmcz project.

Author
Axel Haslam (ahasl.nosp@m.am@b.nosp@m.aylib.nosp@m.re.c.nosp@m.om)

Copyright 2024(c) Analog Devices, Inc.

SPDX-License-Identifier: BSD-3-Clause

Variable Documentation

◆ ad463x_spi_extra_ip

struct stm32_spi_init_param ad463x_spi_extra_ip
Initial value:
= {
.chip_select_port = SPI_CS_PORT,
.get_input_clock = HAL_RCC_GetPCLK2Freq,
.dma_init = &dma_init,
.txdma_ch = &txdma_channel,
.rxdma_ch = &rxdma_channel,
.irq_num = DMA2_Stream0_IRQn,
.pwm_init = &cs_pwm_init,
.tx_pwm_init = &tx_pwm_init,
.alternate = GPIO_AF1_TIM1,
}
struct stm32_dma_channel txdma_channel
Definition parameters.c:28
struct no_os_pwm_init_param cs_pwm_init
Definition parameters.c:83
struct stm32_dma_channel rxdma_channel
Definition parameters.c:37
struct no_os_dma_init_param dma_init
Definition parameters.c:22
struct no_os_pwm_init_param tx_pwm_init
Definition parameters.c:111
#define SPI_CS_PORT
Definition parameters.h:40

◆ ad463x_uart_extra_ip

struct stm32_uart_init_param ad463x_uart_extra_ip
Initial value:
= {
.huart = &huart5,
}
UART_HandleTypeDef huart5

◆ cnv_pwm_extra_init_params

struct stm32_pwm_init_param cnv_pwm_extra_init_params
Initial value:
= {
.htimer = &htim1,
.pwm_timer = STM32_PWM_TIMER_TIM,
.prescaler = 1,
.timer_autoreload = true,
.mode = TIM_OC_PWM1,
.timer_chn = 3,
.complementary_channel = false,
.get_timer_clock = HAL_RCC_GetPCLK2Freq,
.clock_divider = 2,
.trigger_output = PWM_TRGO_UPDATE,
}
TIM_HandleTypeDef htim1
@ STM32_PWM_TIMER_TIM
Definition stm32_pwm.h:18
@ PWM_TRGO_UPDATE
Definition stm32_pwm.h:45
@ TIM_OC_PWM1
Definition stm32_pwm.h:24

◆ cnv_pwm_gpio_extra_init_params

struct stm32_gpio_init_param cnv_pwm_gpio_extra_init_params
Initial value:
= {
.mode = GPIO_MODE_AF_PP,
.speed = GPIO_SPEED_FREQ_VERY_HIGH,
.alternate = GPIO_AF1_TIM1
}

◆ cs_pwm_extra_init_params

struct stm32_pwm_init_param cs_pwm_extra_init_params
Initial value:
= {
.htimer = &htim2,
.pwm_timer = STM32_PWM_TIMER_TIM,
.prescaler = 1,
.timer_autoreload = true,
.mode = TIM_OC_PWM1,
.timer_chn = 1,
.complementary_channel = false,
.get_timer_clock = HAL_RCC_GetPCLK1Freq,
.clock_divider = 2,
.onepulse_enable = true,
.slave_mode = STM32_PWM_SM_TRIGGER,
.trigger_source = PWM_TS_ITR0,
.trigger_output = PWM_TRGO_ENABLE,
}
TIM_HandleTypeDef htim2
@ STM32_PWM_SM_TRIGGER
Definition stm32_pwm.h:55
@ PWM_TRGO_ENABLE
Definition stm32_pwm.h:44
@ PWM_TS_ITR0
Definition stm32_pwm.h:30

◆ cs_pwm_init

struct no_os_pwm_init_param cs_pwm_init
Initial value:
= {
.id = 2,
.period_ns = CS_PWM_PERIOD_NS,
.duty_cycle_ns = CS_PWM_DUTY_NS,
.platform_ops = &stm32_pwm_ops,
}
struct stm32_pwm_init_param cs_pwm_extra_init_params
Definition parameters.c:67
#define CS_PWM_PERIOD_NS
Definition parameters.h:72
#define CS_PWM_DUTY_NS
Definition parameters.h:73
@ NO_OS_PWM_POLARITY_HIGH
Definition no_os_pwm.h:24
const struct no_os_pwm_platform_ops stm32_pwm_ops
STM32 platform specific PWM platform ops structure.
Definition stm32_pwm.c:1178

◆ dma_init

struct no_os_dma_init_param dma_init
Initial value:
= {
.id = 0,
.num_ch = 2,
.platform_ops = &stm32_dma_ops,
}
const struct no_os_dma_platform_ops stm32_dma_ops
stm32 platform specific DMA platform ops structure
Definition stm32_dma.c:257

◆ hdma_spi1_rx

DMA_HandleTypeDef hdma_spi1_rx
extern

◆ hdma_tim8_ch1

DMA_HandleTypeDef hdma_tim8_ch1
extern

◆ rxdma_channel

struct stm32_dma_channel rxdma_channel
Initial value:
= {
.hdma = &hdma_spi1_rx,
.ch_num = DMA_CHANNEL_3,
.mem_increment = true,
.mem_data_alignment = DATA_ALIGN_BYTE,
.per_data_alignment = DATA_ALIGN_BYTE,
.dma_mode = DMA_NORMAL_MODE,
}
DMA_HandleTypeDef hdma_spi1_rx
@ DMA_NORMAL_MODE
Definition stm32_dma.h:33
@ DATA_ALIGN_BYTE
Definition stm32_dma.h:23

◆ tx_pwm_extra_init_params

struct stm32_pwm_init_param tx_pwm_extra_init_params
Initial value:
= {
.htimer = &htim8,
.pwm_timer = STM32_PWM_TIMER_TIM,
.prescaler = 1,
.timer_autoreload = true,
.mode = TIM_OC_PWM1,
.timer_chn = 1,
.complementary_channel = false,
.get_timer_clock = HAL_RCC_GetPCLK2Freq,
.clock_divider = 2,
.onepulse_enable = true,
.slave_mode = STM32_PWM_SM_TRIGGER,
.trigger_source = PWM_TS_ITR0,
.dma_enable = true,
.repetitions = TX_PWM_REPS,
}
TIM_HandleTypeDef htim8
#define TX_PWM_REPS
Definition parameters.h:69

◆ tx_pwm_init

struct no_os_pwm_init_param tx_pwm_init
Initial value:
= {
.id = 8,
.period_ns = TX_PWM_PERIOD_NS,
.duty_cycle_ns = TX_PWM_DUTY_NS,
.platform_ops = &stm32_pwm_ops,
}
struct stm32_pwm_init_param tx_pwm_extra_init_params
Definition parameters.c:94
#define TX_PWM_DUTY_NS
Definition parameters.h:68
#define TX_PWM_PERIOD_NS
Definition parameters.h:67

◆ txdma_channel

struct stm32_dma_channel txdma_channel
Initial value:
= {
.hdma = &hdma_tim8_ch1,
.ch_num = DMA_CHANNEL_7,
.mem_increment = false,
.mem_data_alignment = DATA_ALIGN_BYTE,
.per_data_alignment = DATA_ALIGN_BYTE,
.dma_mode = DMA_CIRCULAR_MODE
}
DMA_HandleTypeDef hdma_tim8_ch1
@ DMA_CIRCULAR_MODE
Definition stm32_dma.h:34