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35 #ifndef __PARAMETERS_H__
36 #define __PARAMETERS_H__
42 #include <xparameters.h>
43 #include <xil_cache.h>
51 #define AD463x_DMA_BASEADDR XPAR_AXI_AD463X_DMA_BASEADDR
52 #define AD463x_SPI_ENGINE_BASEADDR XPAR_SPI_AD463X_SPI_AD463X_AXI_REGMAP_BASEADDR
53 #define RX_CLKGEN_BASEADDR XPAR_SPI_CLKGEN_BASEADDR
54 #define AXI_PWMGEN_BASEADDR XPAR_CNV_GENERATOR_BASEADDR
56 #define AD463x_SPI_CS 0
58 #define GPIO_OFFSET 54
59 #define GPIO_RESETN_1 GPIO_OFFSET + 32
60 #define GPIO_PGIA_0 GPIO_OFFSET + 33
61 #define GPIO_PGIA_1 GPIO_OFFSET + 34
62 #define GPIO_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
64 #define UART_BAUDRATE 115200
65 #define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID
66 #define UART_IRQ_ID XPAR_XUARTPS_1_INTR
67 #define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
72 #ifdef _XPARAMETERS_PS_H_
73 #define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID
74 #define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
76 #ifdef XPS_BOARD_ZCU102
77 #define UART_IRQ_ID XPAR_XUARTPS_0_INTR
79 #define UART_IRQ_ID XPAR_XUARTPS_1_INTR
82 #else // _XPARAMETERS_PS_H_
83 #define UART_DEVICE_ID XPAR_AXI_UART_DEVICE_ID
84 #define INTC_DEVICE_ID XPAR_INTC_SINGLE_DEVICE_ID
85 #define UART_IRQ_ID XPAR_AXI_INTC_AXI_UART_INTERRUPT_INTR
86 #endif // _XPARAMETERS_PS_H_
89 #define UART_BAUDRATE 115200
90 #define UART_EXTRA &uart_extra_ip
91 #define UART_OPS &xil_uart_ops
93 #define DCACHE_INVALIDATE Xil_DCacheInvalidateRange
95 #define DMA_BASEADDR XPAR_AXI_AD463X_DMA_BASEADDR
96 #define SPI_ENGINE_BASEADDR XPAR_SPI_AD463X_SPI_AD463X_AXI_REGMAP_BASEADDR
97 #define RX_CLKGEN_BASEADDR XPAR_SPI_CLKGEN_BASEADDR
98 #define AXI_PWMGEN_BASEADDR XPAR_CNV_GENERATOR_BASEADDR
100 #define SAMPLES_PER_CHANNEL_PLATFORM 100000
101 #define MAX_SIZE_BASE_ADDR (SAMPLES_PER_CHANNEL_PLATFORM * 2 * sizeof(uint32_t))
103 #define SPI_ENG_REF_CLK_FREQ_HZ XPAR_PS7_SPI_0_SPI_CLK_FREQ_HZ
105 #define REFCLK_RATE 160000000
107 #define SPI_DEVICE_ID 0
108 #define SPI_OPS &spi_eng_platform_ops
109 #define SPI_EXTRA &spi_eng_init_param
111 #define SPI_BAUDRATE 80000000
113 #define NO_OS_PWM_ID 0
114 #define PWM_OPS &axi_pwm_ops
115 #define PWM_EXTRA &ad4630_axi_pwm_init
116 #define TRIGGER_PERIOD_NS 500
117 #define TRIGGER_DUTY_NS 10
119 #define AD400X_ADC_REF_VOLTAGE 5000
121 #define GPIO_OPS &xil_gpio_ops
122 #define GPIO_EXTRA &gpio_extra_param
123 #define GPIO_OFFSET 54
124 #define GPIO_RESETN_1 GPIO_OFFSET + 32
125 #define GPIO_RESETN_PORT 0
127 #define GPIO_PGIA_0 GPIO_OFFSET + 33
128 #define GPIO_PGIA_0_PORT 0
129 #define GPIO_PGIA_1 GPIO_OFFSET + 34
130 #define GPIO_PGIA_1_PORT 0
132 #define GPIO_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
Structure holding the initialization parameters for Xilinx platform specific UART parameters.
Definition: xilinx_uart.h:67
Structure holding the initialization parameters for axi PWM.
Definition: axi_pwm_extra.h:50
Structure containing the init parameters needed by the SPI engine.
Definition: spi_engine.h:83
Structure holding the initialization parameters for Xilinx platform specific GPIO parameters.
Definition: xilinx_gpio.h:64