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Macros | Variables
parameters.h File Reference

Definitions specific to xilinx platform used by ad463x_fmcz project. More...

#include <stdio.h>
#include <xparameters.h>
#include <xil_cache.h>
#include <xilinx_uart.h>
#include "xilinx_gpio.h"
#include "axi_pwm_extra.h"
#include "spi_engine.h"
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Macros

#define UART_DEVICE_ID   XPAR_AXI_UART_DEVICE_ID
 
#define INTC_DEVICE_ID   XPAR_INTC_SINGLE_DEVICE_ID
 
#define UART_IRQ_ID   XPAR_AXI_INTC_AXI_UART_INTERRUPT_INTR
 
#define UART_BAUDRATE   115200
 
#define UART_EXTRA   &uart_extra_ip
 
#define UART_OPS   &xil_uart_ops
 
#define DCACHE_INVALIDATE   Xil_DCacheInvalidateRange
 
#define DMA_BASEADDR   XPAR_AXI_AD463X_DMA_BASEADDR
 
#define SPI_ENGINE_BASEADDR   XPAR_SPI_AD463X_SPI_AD463X_AXI_REGMAP_BASEADDR
 
#define RX_CLKGEN_BASEADDR   XPAR_SPI_CLKGEN_BASEADDR
 
#define AXI_PWMGEN_BASEADDR   XPAR_CNV_GENERATOR_BASEADDR
 
#define SAMPLES_PER_CHANNEL_PLATFORM   100000
 
#define MAX_SIZE_BASE_ADDR   (SAMPLES_PER_CHANNEL_PLATFORM * 2 * sizeof(uint32_t))
 
#define SPI_ENG_REF_CLK_FREQ_HZ   XPAR_PS7_SPI_0_SPI_CLK_FREQ_HZ
 
#define REFCLK_RATE   160000000
 
#define SPI_DEVICE_ID   0
 
#define SPI_OPS   &spi_eng_platform_ops
 
#define SPI_EXTRA   &spi_eng_init_param
 
#define SPI_CS   0
 
#define SPI_BAUDRATE   80000000
 
#define NO_OS_PWM_ID   0
 
#define PWM_OPS   &axi_pwm_ops
 
#define PWM_EXTRA   &ad4630_axi_pwm_init
 
#define TRIGGER_PERIOD_NS   500
 
#define TRIGGER_DUTY_NS   10
 
#define AD400X_ADC_REF_VOLTAGE   5000
 
#define GPIO_OPS   &xil_gpio_ops
 
#define GPIO_EXTRA   &gpio_extra_param
 
#define GPIO_OFFSET   54
 
#define GPIO_RESETN_1   GPIO_OFFSET + 32
 
#define GPIO_RESETN_PORT   0
 
#define GPIO_PGIA_0   GPIO_OFFSET + 33
 
#define GPIO_PGIA_0_PORT   0
 
#define GPIO_PGIA_1   GPIO_OFFSET + 34
 
#define GPIO_PGIA_1_PORT   0
 
#define GPIO_DEVICE_ID   XPAR_PS7_GPIO_0_DEVICE_ID
 

Variables

struct xil_uart_init_param uart_extra_ip
 
struct spi_engine_init_param spi_eng_init_param
 
struct axi_pwm_init_param ad4630_axi_pwm_init
 
struct xil_gpio_init_param gpio_extra_param
 

Detailed Description

Definitions specific to xilinx platform used by ad463x_fmcz project.

Author
Antoniu Miclaus (anton.nosp@m.iu.m.nosp@m.iclau.nosp@m.s@an.nosp@m.alog..nosp@m.com)
Axel Haslam (ahasl.nosp@m.am@b.nosp@m.aylib.nosp@m.re.c.nosp@m.om)

Copyright 2024(c) Analog Devices, Inc.

All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Macro Definition Documentation

◆ AD400X_ADC_REF_VOLTAGE

#define AD400X_ADC_REF_VOLTAGE   5000

◆ AXI_PWMGEN_BASEADDR

#define AXI_PWMGEN_BASEADDR   XPAR_CNV_GENERATOR_BASEADDR

◆ DCACHE_INVALIDATE

#define DCACHE_INVALIDATE   Xil_DCacheInvalidateRange

◆ DMA_BASEADDR

#define DMA_BASEADDR   XPAR_AXI_AD463X_DMA_BASEADDR

◆ GPIO_DEVICE_ID

#define GPIO_DEVICE_ID   XPAR_PS7_GPIO_0_DEVICE_ID

◆ GPIO_EXTRA

#define GPIO_EXTRA   &gpio_extra_param

◆ GPIO_OFFSET

#define GPIO_OFFSET   54

◆ GPIO_OPS

#define GPIO_OPS   &xil_gpio_ops

◆ GPIO_PGIA_0

#define GPIO_PGIA_0   GPIO_OFFSET + 33

◆ GPIO_PGIA_0_PORT

#define GPIO_PGIA_0_PORT   0

◆ GPIO_PGIA_1

#define GPIO_PGIA_1   GPIO_OFFSET + 34

◆ GPIO_PGIA_1_PORT

#define GPIO_PGIA_1_PORT   0

◆ GPIO_RESETN_1

#define GPIO_RESETN_1   GPIO_OFFSET + 32

◆ GPIO_RESETN_PORT

#define GPIO_RESETN_PORT   0

◆ INTC_DEVICE_ID

#define INTC_DEVICE_ID   XPAR_INTC_SINGLE_DEVICE_ID

◆ MAX_SIZE_BASE_ADDR

#define MAX_SIZE_BASE_ADDR   (SAMPLES_PER_CHANNEL_PLATFORM * 2 * sizeof(uint32_t))

◆ NO_OS_PWM_ID

#define NO_OS_PWM_ID   0

◆ PWM_EXTRA

#define PWM_EXTRA   &ad4630_axi_pwm_init

◆ PWM_OPS

#define PWM_OPS   &axi_pwm_ops

◆ REFCLK_RATE

#define REFCLK_RATE   160000000

◆ RX_CLKGEN_BASEADDR

#define RX_CLKGEN_BASEADDR   XPAR_SPI_CLKGEN_BASEADDR

◆ SAMPLES_PER_CHANNEL_PLATFORM

#define SAMPLES_PER_CHANNEL_PLATFORM   100000

◆ SPI_BAUDRATE

#define SPI_BAUDRATE   80000000

◆ SPI_CS

#define SPI_CS   0

◆ SPI_DEVICE_ID

#define SPI_DEVICE_ID   0

◆ SPI_ENG_REF_CLK_FREQ_HZ

#define SPI_ENG_REF_CLK_FREQ_HZ   XPAR_PS7_SPI_0_SPI_CLK_FREQ_HZ

◆ SPI_ENGINE_BASEADDR

#define SPI_ENGINE_BASEADDR   XPAR_SPI_AD463X_SPI_AD463X_AXI_REGMAP_BASEADDR

◆ SPI_EXTRA

#define SPI_EXTRA   &spi_eng_init_param

◆ SPI_OPS

#define SPI_OPS   &spi_eng_platform_ops

◆ TRIGGER_DUTY_NS

#define TRIGGER_DUTY_NS   10

◆ TRIGGER_PERIOD_NS

#define TRIGGER_PERIOD_NS   500

◆ UART_BAUDRATE

#define UART_BAUDRATE   115200

◆ UART_DEVICE_ID

#define UART_DEVICE_ID   XPAR_AXI_UART_DEVICE_ID

◆ UART_EXTRA

#define UART_EXTRA   &uart_extra_ip

◆ UART_IRQ_ID

#define UART_IRQ_ID   XPAR_AXI_INTC_AXI_UART_INTERRUPT_INTR

◆ UART_OPS

#define UART_OPS   &xil_uart_ops

Variable Documentation

◆ ad4630_axi_pwm_init

struct axi_pwm_init_param ad4630_axi_pwm_init

◆ gpio_extra_param

struct xil_gpio_init_param gpio_extra_param

◆ spi_eng_init_param

struct spi_engine_init_param spi_eng_init_param

◆ uart_extra_ip

struct xil_uart_init_param uart_extra_ip