no-OS
ad5766_core.h
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1 /***************************************************************************/
33 #ifndef AD5766_CORE_H_
34 #define AD5766_CORE_H_
35 
36 /******************************************************************************/
37 /*************************** Types Declarations *******************************/
38 /******************************************************************************/
39 typedef struct {
40  uint32_t core_baseaddr;
41  uint32_t dma_baseaddr;
42  uint32_t dma_source_addr;
43  uint32_t rate_hz;
44  uint32_t spi_clk_hz;
45 } ad5766_core;
46 
47 typedef struct {
48  uint32_t core_baseaddr;
49  uint32_t dma_baseaddr;
50  uint32_t dma_source_addr;
51  uint32_t rate_hz;
52  uint32_t spi_clk_hz;
53 } ad5766_core_init_param;
54 
55 /******************************************************************************/
56 /************************ Functions Declarations ******************************/
57 /******************************************************************************/
58 int32_t ad5766_core_setup(struct spi_engine_desc *eng_desc,
59  ad5766_core **ad_core,
60  ad5766_core_init_param init_param);
61 #endif
NO_OS_SPI_MODE_1
@ NO_OS_SPI_MODE_1
Definition: no_os_spi.h:63
ad5758_default_init_param
struct ad5758_init_param ad5758_default_init_param
Definition: ad5758_sdz.c:82
no_os_alloc.h
no_os_gpio_init_param
Structure holding the parameters for GPIO initialization.
Definition: no_os_gpio.h:79
ad5766_core::dma_baseaddr
uint32_t dma_baseaddr
Definition: ad5766_core.h:41
GPIO_PS
@ GPIO_PS
Definition: xilinx_gpio.h:56
SPI_PS
@ SPI_PS
Definition: xilinx_spi.h:62
spi_extra
const struct xil_spi_init_param spi_extra
Definition: ad5758_sdz.c:53
SPI_ENGINE_CMD_ASSERT
#define SPI_ENGINE_CMD_ASSERT(delay, cs)
Definition: spi_engine_private.h:118
AD5758_SPI_CS
#define AD5758_SPI_CS
Definition: parameters.h:42
ad5766_core_setup
int32_t ad5766_core_setup(struct spi_engine_desc *eng_desc, ad5766_core **ad_core, ad5766_core_init_param init_param)
ad5766_core_setup
Definition: ad5766_core.c:163
ad5766_core_init_param::dma_source_addr
uint32_t dma_source_addr
Definition: ad5766_core.h:50
no_os_spi.h
Header file of SPI Interface.
spi_engine_desc
Structure representing an SPI engine device.
Definition: spi_engine.h:103
ad5766_core_init_param
Definition: ad5766_core.h:47
ad5758_dac_input_write
int32_t ad5758_dac_input_write(struct ad5758_dev *dev, uint16_t code)
Definition: ad5758.c:487
xil_gpio_ops
const struct no_os_gpio_platform_ops xil_gpio_ops
Xilinx platform specific GPIO platform ops structure.
Definition: xilinx_gpio.c:450
spi_ip
const struct no_os_spi_init_param spi_ip
Definition: ad5758_sdz.c:57
SPI_ENGINE_CONFIG_CPHA
#define SPI_ENGINE_CONFIG_CPHA
Definition: spi_engine_private.h:88
ad5766_core::spi_clk_hz
uint32_t spi_clk_hz
Definition: ad5766_core.h:44
no_os_gpio_init_param::number
int32_t number
Definition: no_os_gpio.h:83
ad5766_core_setup
int32_t ad5766_core_setup(struct spi_engine_desc *eng_desc, ad5766_core **ad_core, ad5766_core_init_param init_param)
ad5766_core_setup
Definition: ad5766_core.c:163
ad5766_core_read
void ad5766_core_read(ad5766_core *core, uint32_t reg_addr, uint32_t *reg_data)
ad5766_core_read
Definition: ad5766_core.c:131
RANGE_0V_10V
@ RANGE_0V_10V
Definition: ad5758.h:332
SPI_ENGINE_REG_OFFLOAD_CMD_MEM
#define SPI_ENGINE_REG_OFFLOAD_CMD_MEM(x)
Definition: spi_engine_private.h:107
ad5766_core_init_param::rate_hz
uint32_t rate_hz
Definition: ad5766_core.h:51
no_os_spi_init_param::device_id
uint32_t device_id
Definition: no_os_spi.h:142
ad5758.h
Header file for ad5758 Driver.
ad7616_init_param::core_baseaddr
uint32_t core_baseaddr
Definition: ad7616.h:224
no_os_error.h
Error codes definition.
SPI_ENGINE_CMD_TRANSFER
#define SPI_ENGINE_CMD_TRANSFER(readwrite, n)
Definition: spi_engine_private.h:114
DPC_VOLTAGE_MODE
@ DPC_VOLTAGE_MODE
Definition: ad5758.h:268
ad5766_core::dma_source_addr
uint32_t dma_source_addr
Definition: ad5766_core.h:42
ad5766_core.h
Header file of AD5766 Core Driver.
ad5766_core::rate_hz
uint32_t rate_hz
Definition: ad5766_core.h:43
spi_engine.h
ad5766_dma_read
void ad5766_dma_read(ad5766_core *core, uint32_t reg_addr, uint32_t *reg_data)
ad5766_core_read
Definition: ad5766_core.c:153
SPI_ENGINE_REG_OFFLOAD_CTRL
#define SPI_ENGINE_REG_OFFLOAD_CTRL(x)
Definition: spi_engine_private.h:104
SPI_ENGINE_REG_OFFLOAD_RESET
#define SPI_ENGINE_REG_OFFLOAD_RESET(x)
Definition: spi_engine_private.h:106
SPI_ENGINE_CMD_CONFIG
#define SPI_ENGINE_CMD_CONFIG(reg, val)
Definition: spi_engine_private.h:122
CLKOUT_DISABLE
@ CLKOUT_DISABLE
Definition: ad5758.h:287
GPIO_DEVICE_ID
#define GPIO_DEVICE_ID
Definition: parameters.h:84
gpio_extra
const struct xil_gpio_init_param gpio_extra
Definition: ad5758_sdz.c:67
xilinx_gpio.h
ad5758_init
int32_t ad5758_init(struct ad5758_dev **device, struct ad5758_init_param *init_param)
Definition: ad5758.c:767
xil_spi_init_param::type
enum xil_spi_type type
Definition: xilinx_spi.h:74
CLKOUT_FREQ_500_KHZ
@ CLKOUT_FREQ_500_KHZ
Definition: ad5758.h:296
SPI_ENGINE_CMD_SYNC
#define SPI_ENGINE_CMD_SYNC(id)
Definition: spi_engine_private.h:131
xil_spi_init_param
Structure holding the initialization parameters for Xilinx platform specific SPI parameters when usin...
Definition: xilinx_spi.h:72
ad5766_core_init_param::core_baseaddr
uint32_t core_baseaddr
Definition: ad5766_core.h:48
ad5758_init_param::spi_init
struct no_os_spi_init_param spi_init
Definition: ad5758.h:389
no_os_malloc
void * no_os_malloc(size_t size)
Allocate memory and return a pointer to it.
Definition: chibios_alloc.c:43
ad5766_core_write
int32_t ad5766_core_write(ad5766_core *core, uint32_t reg_addr, uint32_t reg_data)
ad5766_core_write
Definition: ad5766_core.c:119
NO_OS_BIT
#define NO_OS_BIT(x)
Definition: no_os_util.h:45
no_os_free
void no_os_free(void *ptr)
Deallocate memory previously allocated by a call to no_os_calloc or no_os_malloc.
Definition: chibios_alloc.c:69
ad5766_core
Definition: ad5766_core.h:39
NO_OS_SPI_BIT_ORDER_MSB_FIRST
@ NO_OS_SPI_BIT_ORDER_MSB_FIRST
Definition: no_os_spi.h:76
ILIMIT_200_mA
@ ILIMIT_200_mA
Definition: ad5758.h:323
ad5766_dma_write
int32_t ad5766_dma_write(ad5766_core *core, uint32_t reg_addr, uint32_t reg_data)
ad5766_core_write
Definition: ad5766_core.c:141
SPI_ENGINE_CMD_REG_CONFIG
#define SPI_ENGINE_CMD_REG_CONFIG
Definition: spi_engine_private.h:76
sine_lut
const uint16_t sine_lut[512]
Definition: ad5766_core.c:49
ad5766_core_init_param::dma_baseaddr
uint32_t dma_baseaddr
Definition: ad5766_core.h:49
main
int main()
Definition: ad5758_sdz.c:98
NULL
#define NULL
Definition: wrapper.h:64
ad5758_init_param
Definition: ad5758.h:387
xil_spi_ops
const struct no_os_spi_platform_ops xil_spi_ops
Spi engine platform specific SPI platform ops structure.
Definition: xilinx_spi.c:453
SPI_DEVICE_ID
#define SPI_DEVICE_ID
Definition: parameters.h:69
init_param
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:113
ad5766_core_init_param::spi_clk_hz
uint32_t spi_clk_hz
Definition: ad5766_core.h:52
ad5758_dev
Definition: ad5758.h:371
xil_gpio_init_param
Structure holding the initialization parameters for Xilinx platform specific GPIO parameters.
Definition: xilinx_gpio.h:64
no_os_gpio.h
Header file of GPIO Interface.
parameters.h
Parameters Definitions.
SR_CLOCK_240_KHZ
@ SR_CLOCK_240_KHZ
Definition: ad5758.h:303
ldac_ip
const struct no_os_gpio_init_param ldac_ip
Definition: ad5758_sdz.c:76
reset_ip
const struct no_os_gpio_init_param reset_ip
Definition: ad5758_sdz.c:71
SPI_ENGINE_CMD_REG_CLK_DIV
#define SPI_ENGINE_CMD_REG_CLK_DIV
Definition: spi_engine_private.h:75
spi_engine_private.h
ad5766_core::core_baseaddr
uint32_t core_baseaddr
Definition: ad5766_core.h:40
xilinx_spi.h
xil_gpio_init_param::type
enum xil_gpio_type type
Definition: xilinx_gpio.h:66
spi_engine_write
int32_t spi_engine_write(struct spi_engine_desc *desc, uint32_t reg_addr, uint32_t reg_data)
Write SPI Engine's axi registers.
Definition: spi_engine.c:90
GPIO_DAC_LDAC_N
#define GPIO_DAC_LDAC_N
Definition: parameters.h:47
GPIO_DAC_RESET_N
#define GPIO_DAC_RESET_N
Definition: parameters.h:46
no_os_spi_init_param
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:140
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