Header file of AD6673 Driver. More...

#include <stdint.h>
#include "no_os_spi.h"
#include "no_os_error.h"

Include dependency graph for ad6673.h:

Classes
struct	ad6673_platform_data
	Platform specific information. More...

struct	ad6673_jesd204b_cfg
	JESD204B interface configuration. More...

struct	ad6673_fast_detect_cfg
	Fast Detect module configuration. More...

struct	ad6673_type_band

struct	ad6673_state

struct	ad6673_dev

struct	ad6673_init_param

Macros
#define	AD6673_READ (1 << 15)

#define	AD6673_WRITE (0 << 15)

#define	AD6673_CNT(x)

#define	AD6673_ADDR(x)

#define	AD6673_R1B (1 << 8)

#define	AD6673_R2B (2 << 8)

#define	AD6673_R3B (3 << 8)

#define	AD6673_TRANSF_LEN(x)

#define	SHADOW(x)

#define	AD6673_REG_SPI_CFG (AD6673_R1B \| 0x00)

#define	AD6673_REG_CHIP_ID (AD6673_R1B \| 0x01)

#define	AD6673_REG_CHIP_INFO (AD6673_R1B \| 0x02)

#define	AD6673_REG_CH_INDEX (AD6673_R1B \| 0x05)

#define	AD6673_REG_DEVICE_UPDATE (AD6673_R1B \| 0xFF)

#define	AD6673_REG_PDWN (AD6673_R1B \| 0x08)

#define	AD6673_REG_CLOCK (AD6673_R1B \| 0x09 \| SHADOW(1))

#define	AD6673_REG_PLL_STAT (AD6673_R1B \| 0x0A)

#define	AD6673_REG_CLOCK_DIV (AD6673_R1B \| 0x0B \| SHADOW(2))

#define	AD6673_REG_TEST (AD6673_R1B \| 0x0D \| SHADOW(3))

#define	AD6673_REG_BIST (AD6673_R1B \| 0x0E \| SHADOW(4))

#define	AD6673_REG_OFFSET (AD6673_R1B \| 0x10 \| SHADOW(5))

#define	AD6673_REG_OUT_MODE (AD6673_R1B \| 0x14 \| SHADOW(6))

#define	AD6673_REG_CML (AD6673_R1B \| 0x15)

#define	AD6673_REG_VREF (AD6673_R1B \| 0x18 \| SHADOW(7))

#define	AD6673_REG_USER_TEST1 (AD6673_R2B \| 0x1A)

#define	AD6673_REG_USER_TEST2 (AD6673_R2B \| 0x1C)

#define	AD6673_REG_USER_TEST3 (AD6673_R2B \| 0x1E)

#define	AD6673_REG_USER_TEST4 (AD6673_R2B \| 0x20)

#define	AD6673_REG_PLL_ENCODE (AD6673_R1B \| 0x21)

#define	AD6673_REG_BIST_MISR (AD6673_R2B \| 0x25)

#define	AD6673_REG_SYS_CTRL (AD6673_R1B \| 0x3A \| SHADOW(8))

#define	AD6673_REG_NSR_CTRL (AD6673_R1B \| 0x3C \| SHADOW(9))

#define	AD6673_REG_NSR_TUNING (AD6673_R1B \| 0x3E \| SHADOW(10))

#define	AD6673_REG_DCC_CTRL (AD6673_R1B \| 0x40 \| SHADOW(11))

#define	AD6673_REG_DCC_VAL (AD6673_R2B \| 0x42 \| SHADOW(12))

#define	AD6673_REG_FAST_DETECT (AD6673_R1B \| 0x45 \| SHADOW(13))

#define	AD6673_REG_FD_UPPER_THD (AD6673_R2B \| 0x48 \| SHADOW(14))

#define	AD6673_REG_FD_LOWER_THD (AD6673_R2B \| 0x4A \| SHADOW(15))

#define	AD6673_REG_FD_DWELL_TIME (AD6673_R2B \| 0x4C \| SHADOW(16))

#define	AD6673_REG_204B_QUICK_CFG (AD6673_R1B \| 0x5E)

#define	AD6673_REG_204B_CTRL1 (AD6673_R1B \| 0x5F)

#define	AD6673_REG_204B_CTRL2 (AD6673_R1B \| 0x60)

#define	AD6673_REG_204B_CTRL3 (AD6673_R1B \| 0x61)

#define	AD6673_REG_204B_DID_CFG (AD6673_R1B \| 0x64)

#define	AD6673_REG_204B_BID_CFG (AD6673_R1B \| 0x65)

#define	AD6673_REG_204B_LID_CFG1 (AD6673_R1B \| 0x67)

#define	AD6673_REG_204B_LID_CFG2 (AD6673_R1B \| 0x68)

#define	AD6673_REG_204B_PARAM_SCR_L (AD6673_R1B \| 0x6E)

#define	AD6673_REG_204B_PARAM_F (AD6673_R1B \| 0x6F)

#define	AD6673_REG_204B_PARAM_K (AD6673_R1B \| 0x70)

#define	AD6673_REG_204B_PARAM_M (AD6673_R1B \| 0x71)

#define	AD6673_REG_204B_PARAM_CS_N (AD6673_R1B \| 0x72)

#define	AD6673_REG_204B_PARAM_NP (AD6673_R1B \| 0x73)

#define	AD6673_REG_204B_PARAM_S (AD6673_R1B \| 0x74)

#define	AD6673_REG_204B_PARAM_HD_CF (AD6673_R1B \| 0x75)

#define	AD6673_REG_204B_RESV1 (AD6673_R1B \| 0x76)

#define	AD6673_REG_204B_RESV2 (AD6673_R1B \| 0x77)

#define	AD6673_REG_204B_CHKSUM0 (AD6673_R1B \| 0x79)

#define	AD6673_REG_204B_CHKSUM1 (AD6673_R1B \| 0x7A)

#define	AD6673_REG_204B_LANE_ASSGN1 (AD6673_R1B \| 0x82)

#define	AD6673_REG_204B_LANE_ASSGN2 (AD6673_R1B \| 0x83)

#define	AD6673_REG_204B_LMFC_OFFSET (AD6673_R1B \| 0x8B)

#define	AD6673_REG_204B_PRE_EMPHASIS (AD6673_R1B \| 0xA8)

#define	AD6673_SPI_CFG_LSB_FIRST ((1 << 6) \| (1 << 1))

#define	AD6673_SPI_CFG_SOFT_RST ((1 << 5) \| (1 << 2))

#define	AD6673_CH_INDEX_ADC_A (1 << 0)

#define	AD6673_CH_INDEX_ADC_B (1 << 1)

#define	AD6673_DEVICE_UPDATE_SW (1 << 0)

#define	AD6673_PDWN_EXTERN (1 << 5)

#define	AD6673_PDWN_JTX (1 << 4)

#define	AD6673_PDWN_JESD204B(x)

#define	AD6673_PDWN_CHIP(x)

#define	AD6673_CLOCK_SELECTION(x)

#define	AD6673_CLOCK_DUTY_CYCLE (1 << 0)

#define	AD6673_PLL_STAT_LOCKED (1 << 7)

#define	AD6673_PLL_STAT_204B_LINK_RDY (1 << 0)

#define	AD6673_CLOCK_DIV_PHASE(x)

#define	AD6673_CLOCK_DIV_RATIO(x)

#define	AD6673_TEST_USER_TEST_MODE(x)

#define	AD6673_TEST_RST_PN_LONG (1 << 5)

#define	AD6673_TEST_RST_PN_SHOR (1 << 4)

#define	AD6673_TEST_OUTPUT_TEST(x)

#define	AD6673_BIST_RESET (1 << 2)

#define	AD6673_BIST_ENABLE (1 << 0)

#define	AD6673_REG_OFFSET_ADJUST(x)

#define	AD6673_OUT_MODE_JTX_BIT_ASSIGN(x)

#define	AD6673_OUT_MODE_DISABLE (1 << 4)

#define	AD6673_OUT_MODE_INVERT_DATA (1 << 3)

#define	AD6673_OUT_MODE_DATA_FORMAT(x)

#define	AD6673_CML_DIFF_OUT_LEVEL(x)

#define	AD6673_VREF_FS_ADJUST(x)

#define	AD6673_PLL_ENCODE(x)

#define	AD6673_SYS_CTRL_REALIGN_ON_SYNCINB (1 << 4)

#define	AD6673_SYS_CTRL_REALIGN_ON_SYSREF (1 << 3)

#define	AD6673_SYS_CTRL_SYSREF_MODE (1 << 2)

#define	AD6673_SYS_CTRL_SYSREF_EN (1 << 1)

#define	AD6673_SYS_CTRL_SYNCINB_EN (1 << 0)

#define	AD6673_NSR_CTRL_BW_MODE (1 << 1)

#define	AD6673_NSR_CTRL_ENABLE (1 << 0)

#define	AD6673_NSR_TUNING(x)

#define	AD6673_DCC_CTRL_FREEZE_DCC (1 << 6)

#define	AD6673_DCC_CTRL_DCC_BW(x)

#define	AD6673_DCC_CTRL_DCC_EN (1 << 1)

#define	AD6673_FAST_DETECT_PIN_FCT (1 << 4)

#define	AD6673_FAST_DETECT_FORCE_FDA_FDB_PIN (1 << 3)

#define	AD6673_FAST_DETECT_FORCE_FDA_FDB_VAL (1 << 2)

#define	AD6673_FAST_DETECT_OUTPUT_ENABLE (1 << 0)

#define	AD6673_204B_QUICK_CFG(x)

#define	AD6673_204B_CTRL1_TAIL_BITS (1 << 6)

#define	AD6673_204B_CTRL1_TEST_SAMPLE_EN (1 << 5)

#define	AD6673_204B_CTRL1_ILAS_MODE(x)

#define	AD6673_204B_CTRL1_POWER_DOWN (1 << 0)

#define	AD6673_204B_CTRL2_INVERT_JESD_BITS (1 << 1)

#define	AD6673_204B_CTRL3_TEST_DATA_INJ_PT(x)

#define	AD6673_204B_CTRL3_JESD_TEST_MODE(x)

#define	AD6673_204B_PARAM_SCR_L_SCRAMBLING (1 << 7)

#define	AD6673_204B_PARAM_SCR_L_LANES (1 << 0)

#define	AD6673_204B_PARAM_CS_N_NR_CTRL_BITS(x)

#define	AD6673_204B_PARAM_CS_N_ADC_RESOLUTION(x)

#define	AD6673_204B_PARAM_NP_JESD_SUBCLASS(x)

#define	AD6673_204B_PARAM_NP_JESD_N_VAL(x)

#define	AD6673_204B_PARAM_S(x)

#define	AD6673_204B_PARAM_HD_CF_HD_VAL (1 << 7)

#define	AD6673_204B_PARAM_HD_CF_CF_VAL(x)

#define	AD6673_204B_LANE_ASSGN1(x)

#define	AD6673_204B_LANE_ASSGN2(x)

#define	AD6673_204B_LMFC_OFFSET(x)

Enumerations
enum	shadow_registers { AD6673_SHD_REG_CLOCK = 1 , AD6673_SHD_REG_CLOCK_DIV , AD6673_SHD_REG_TEST , AD6673_SHD_REG_BIST , AD6673_SHD_REG_OFFSET , AD6673_SHD_REG_OUT_MODE , AD6673_SHD_REG_VREF , AD6673_SHD_REG_SYS_CTRL , AD6673_REG_SHD_NSR_CTRL , AD6673_REG_SHD_NSR_TUNING , AD6673_SHD_REG_DCC_CTRL , AD6673_SHD_REG_DCC_VAL , AD6673_SHD_REG_FAST_DETECT , AD6673_SHD_REG_FD_UPPER_THD , AD6673_SHD_REG_FD_LOWER_THD , AD6673_SHD_REG_FD_DWELL_TIME , SHADOW_REGISTER_COUNT }

Functions
int32_t	ad6673_setup (struct ad6673_dev **device, struct ad6673_init_param init_param)
	Configures the device.

int32_t	ad6673_remove (struct ad6673_dev *dev)
	Free the resources allocated by ad6673_setup().

int32_t	ad6673_read (struct ad6673_dev *dev, int32_t register_address)
	Reads the value of the selected register.

int32_t	ad6673_write (struct ad6673_dev *dev, int32_t register_address, int32_t register_value)
	Writes a value to the selected register.

int32_t	ad6673_transfer (struct ad6673_dev *dev)
	Initiates a transfer and waits for the operation to end. Note: This function may be called after a shadowed register was written, so that the internal update can actually take place.

int32_t	ad6673_soft_reset (struct ad6673_dev *dev)
	Resets all registers to their default values.

int32_t	ad6673_chip_pwr_mode (struct ad6673_dev *dev, int32_t mode)
	Configures the power mode of the chip.

int32_t	ad6673_select_channel_for_config (struct ad6673_dev *dev, int32_t channel)
	Selects a channel as the current channel for further configurations.

int32_t	ad6673_test_mode (struct ad6673_dev *dev, int32_t mode)
	Sets the ADC's test mode.

int32_t	ad6673_offset_adj (struct ad6673_dev *dev, int32_t adj)
	Sets the offset adjustment.

int32_t	ad6673_output_disable (struct ad6673_dev *dev, int32_t en)
	Disables (1) or enables (0) the data output. Note: This function modifies a shadowed register, therefore a call of ad6673_transfer() is required for the internal update to take place.

int32_t	ad6673_output_invert (struct ad6673_dev *dev, int32_t invert)
	Activates the inverted (1) or normal (0) output mode. Note: This function modifies a shadowed register, therefore a call of ad6673_transfer() is required for the internal update to take place.

int32_t	ad6673_output_format (struct ad6673_dev *dev, int32_t format)
	Specifies the output format. Note: This function modifies a shadowed register, therefore a call of ad6673_transfer() is required for the internal update to take place.

int32_t	ad6673_reset_pn9 (struct ad6673_dev *dev, int32_t rst)
	Sets (1) or clears (0) the reset short PN sequence bit(PN9).

int32_t	ad6673_reset_pn23 (struct ad6673_dev *dev, int32_t rst)
	Sets (1) or clears (0) the reset long PN sequence bit(PN23).

int32_t	ad6673_set_user_pattern (struct ad6673_dev *dev, int32_t pattern_no, int32_t user_pattern)
	Configures a User Test Pattern.

int32_t	ad6673_bist_enable (struct ad6673_dev *dev, int32_t enable)
	Enables the Build-In-Self-Test.

int32_t	ad6673_bist_reset (struct ad6673_dev *dev, int32_t reset)
	Resets the Build-In-Self-Test.

int32_t	ad6673_jesd204b_setup (struct ad6673_dev *dev)
	Configures the JESD204B interface.

int32_t	ad6673_jesd204b_pwr_mode (struct ad6673_dev *dev, int32_t mode)
	Configures the power mode of the JESD204B data transmit block.

int32_t	ad6673_jesd204b_select_test_injection_point (struct ad6673_dev *dev, int32_t inj_point)
	Selects the point in the processing path of a lane, where the test data will be inserted.

int32_t	ad6673_jesd204b_test_mode (struct ad6673_dev *dev, int32_t test_mode)
	Selects a JESD204B test mode.

int32_t	ad6673_jesd204b_invert_logic (struct ad6673_dev *dev, int32_t invert)
	Inverts the logic of JESD204B bits.

int32_t	ad6673_fast_detect_setup (struct ad6673_dev *dev)
	Configures the Fast-Detect module.

int32_t	ad6673_dcc_enable (struct ad6673_dev *dev, int32_t enable)
	Enables DC correction for use in the output data signal path.

int32_t	ad6673_dcc_bandwidth (struct ad6673_dev *dev, int32_t bw)
	Selects the bandwidth value for the DC correction circuit.

int32_t	ad6673_dcc_freeze (struct ad6673_dev *dev, int32_t freeze)
	Freezes DC correction value.

int32_t	ad6673_nsr_enable (struct ad6673_dev *dev, int32_t enable)
	Enables the Noise shaped requantizer(NRS).

int32_t	ad6673_nsr_bandwidth_mode (struct ad6673_dev *dev, int32_t mode)
	Selects the NSR Bandwidth mode.

int32_t	ad6673_nsr_tuning_freq (int64_t tune_freq, int64_t f_adc, struct ad6673_type_band *p_band)
	Sets the NSR frequency range.

Detailed Description

Header file of AD6673 Driver.

Author: DNechita (Dan.N.nosp@m.echi.nosp@m.ta@an.nosp@m.alog.nosp@m..com)

SPDX-License-Identifier: BSD-3-Clause

Macro Definition Documentation

◆ AD6673_204B_CTRL1_ILAS_MODE

#define AD6673_204B_CTRL1_ILAS_MODE ( x )

Value:

(((x) & 0x3) << 2)

◆ AD6673_204B_CTRL1_POWER_DOWN

#define AD6673_204B_CTRL1_POWER_DOWN (1 << 0)

◆ AD6673_204B_CTRL1_TAIL_BITS

#define AD6673_204B_CTRL1_TAIL_BITS (1 << 6)

◆ AD6673_204B_CTRL1_TEST_SAMPLE_EN

#define AD6673_204B_CTRL1_TEST_SAMPLE_EN (1 << 5)

◆ AD6673_204B_CTRL2_INVERT_JESD_BITS

#define AD6673_204B_CTRL2_INVERT_JESD_BITS (1 << 1)

◆ AD6673_204B_CTRL3_JESD_TEST_MODE

#define AD6673_204B_CTRL3_JESD_TEST_MODE ( x )

Value:

(((x) & 0xF) << 0)

◆ AD6673_204B_CTRL3_TEST_DATA_INJ_PT

#define AD6673_204B_CTRL3_TEST_DATA_INJ_PT ( x )

Value:

(((x) & 0x3) << 4)

◆ AD6673_204B_LANE_ASSGN1

#define AD6673_204B_LANE_ASSGN1 ( x )

Value:

(((x) & 0x3) << 4)

◆ AD6673_204B_LANE_ASSGN2

#define AD6673_204B_LANE_ASSGN2 ( x )

Value:

(((x) &0x3) << 0)

◆ AD6673_204B_LMFC_OFFSET

#define AD6673_204B_LMFC_OFFSET ( x )

Value:

(((x) & 0x1F) << 0)

◆ AD6673_204B_PARAM_CS_N_ADC_RESOLUTION

#define AD6673_204B_PARAM_CS_N_ADC_RESOLUTION ( x )

Value:

(((x) & 0xF) << 0)

◆ AD6673_204B_PARAM_CS_N_NR_CTRL_BITS

#define AD6673_204B_PARAM_CS_N_NR_CTRL_BITS ( x )

Value:

(((x) & 0x3) << 6)

◆ AD6673_204B_PARAM_HD_CF_CF_VAL

#define AD6673_204B_PARAM_HD_CF_CF_VAL ( x )

Value:

(((x) & 0x1F) << 0)

◆ AD6673_204B_PARAM_HD_CF_HD_VAL

#define AD6673_204B_PARAM_HD_CF_HD_VAL (1 << 7)

◆ AD6673_204B_PARAM_NP_JESD_N_VAL

#define AD6673_204B_PARAM_NP_JESD_N_VAL ( x )

Value:

(((x) & 0xF) << 0)

◆ AD6673_204B_PARAM_NP_JESD_SUBCLASS

#define AD6673_204B_PARAM_NP_JESD_SUBCLASS ( x )

Value:

(((x) & 0x3) << 5)

◆ AD6673_204B_PARAM_S

#define AD6673_204B_PARAM_S ( x )

Value:

(((x) << 0x1F) << 0)

◆ AD6673_204B_PARAM_SCR_L_LANES

#define AD6673_204B_PARAM_SCR_L_LANES (1 << 0)

◆ AD6673_204B_PARAM_SCR_L_SCRAMBLING

#define AD6673_204B_PARAM_SCR_L_SCRAMBLING (1 << 7)

◆ AD6673_204B_QUICK_CFG

#define AD6673_204B_QUICK_CFG ( x )

Value:

(((x) & 0xFF) << 0)

◆ AD6673_ADDR

#define AD6673_ADDR ( x )

Value:

((x) & 0xFF)

◆ AD6673_BIST_ENABLE

#define AD6673_BIST_ENABLE (1 << 0)

◆ AD6673_BIST_RESET

#define AD6673_BIST_RESET (1 << 2)

◆ AD6673_CH_INDEX_ADC_A

#define AD6673_CH_INDEX_ADC_A (1 << 0)

◆ AD6673_CH_INDEX_ADC_B

#define AD6673_CH_INDEX_ADC_B (1 << 1)

◆ AD6673_CLOCK_DIV_PHASE

#define AD6673_CLOCK_DIV_PHASE ( x )

Value:

(((x) & 0x7) << 3)

◆ AD6673_CLOCK_DIV_RATIO

#define AD6673_CLOCK_DIV_RATIO ( x )

Value:

(((x) & 0x7) << 0)

◆ AD6673_CLOCK_DUTY_CYCLE

#define AD6673_CLOCK_DUTY_CYCLE (1 << 0)

◆ AD6673_CLOCK_SELECTION

#define AD6673_CLOCK_SELECTION ( x )

Value:

(((x) & 0x3) << 4)

◆ AD6673_CML_DIFF_OUT_LEVEL

#define AD6673_CML_DIFF_OUT_LEVEL ( x )

Value:

(((x) & 0x7) << 0)

◆ AD6673_CNT

#define AD6673_CNT ( x )

Value:

((((x) & 0x3) - 1) << 13)

◆ AD6673_DCC_CTRL_DCC_BW

#define AD6673_DCC_CTRL_DCC_BW ( x )

Value:

(((x) & 0xF) << 2)

◆ AD6673_DCC_CTRL_DCC_EN

#define AD6673_DCC_CTRL_DCC_EN (1 << 1)

◆ AD6673_DCC_CTRL_FREEZE_DCC

#define AD6673_DCC_CTRL_FREEZE_DCC (1 << 6)

◆ AD6673_DEVICE_UPDATE_SW

#define AD6673_DEVICE_UPDATE_SW (1 << 0)

◆ AD6673_FAST_DETECT_FORCE_FDA_FDB_PIN

#define AD6673_FAST_DETECT_FORCE_FDA_FDB_PIN (1 << 3)

◆ AD6673_FAST_DETECT_FORCE_FDA_FDB_VAL

#define AD6673_FAST_DETECT_FORCE_FDA_FDB_VAL (1 << 2)

◆ AD6673_FAST_DETECT_OUTPUT_ENABLE

#define AD6673_FAST_DETECT_OUTPUT_ENABLE (1 << 0)

◆ AD6673_FAST_DETECT_PIN_FCT

#define AD6673_FAST_DETECT_PIN_FCT (1 << 4)

◆ AD6673_NSR_CTRL_BW_MODE

#define AD6673_NSR_CTRL_BW_MODE (1 << 1)

◆ AD6673_NSR_CTRL_ENABLE

#define AD6673_NSR_CTRL_ENABLE (1 << 0)

◆ AD6673_NSR_TUNING

#define AD6673_NSR_TUNING ( x )

Value:

(((x) & 0x3F) << 0)

◆ AD6673_OUT_MODE_DATA_FORMAT

#define AD6673_OUT_MODE_DATA_FORMAT ( x )

Value:

(((x) & 0x1) << 0)

◆ AD6673_OUT_MODE_DISABLE

#define AD6673_OUT_MODE_DISABLE (1 << 4)

◆ AD6673_OUT_MODE_INVERT_DATA

#define AD6673_OUT_MODE_INVERT_DATA (1 << 3)

◆ AD6673_OUT_MODE_JTX_BIT_ASSIGN

#define AD6673_OUT_MODE_JTX_BIT_ASSIGN ( x )

Value:

(((x) & 0x7) << 5)

◆ AD6673_PDWN_CHIP

#define AD6673_PDWN_CHIP ( x )

Value:

(((x) & 0x3) << 0)

◆ AD6673_PDWN_EXTERN

#define AD6673_PDWN_EXTERN (1 << 5)

◆ AD6673_PDWN_JESD204B

#define AD6673_PDWN_JESD204B ( x )

Value:

(((x) & 0x3) << 2)

◆ AD6673_PDWN_JTX

#define AD6673_PDWN_JTX (1 << 4)

◆ AD6673_PLL_ENCODE

#define AD6673_PLL_ENCODE ( x )

Value:

(((x) & 0x3) << 3)

◆ AD6673_PLL_STAT_204B_LINK_RDY

#define AD6673_PLL_STAT_204B_LINK_RDY (1 << 0)

◆ AD6673_PLL_STAT_LOCKED

#define AD6673_PLL_STAT_LOCKED (1 << 7)

◆ AD6673_R1B

#define AD6673_R1B (1 << 8)

◆ AD6673_R2B

#define AD6673_R2B (2 << 8)

◆ AD6673_R3B

#define AD6673_R3B (3 << 8)

◆ AD6673_READ

#define AD6673_READ (1 << 15)

◆ AD6673_REG_204B_BID_CFG

#define AD6673_REG_204B_BID_CFG (AD6673_R1B | 0x65)

◆ AD6673_REG_204B_CHKSUM0

#define AD6673_REG_204B_CHKSUM0 (AD6673_R1B | 0x79)

◆ AD6673_REG_204B_CHKSUM1

#define AD6673_REG_204B_CHKSUM1 (AD6673_R1B | 0x7A)

◆ AD6673_REG_204B_CTRL1

#define AD6673_REG_204B_CTRL1 (AD6673_R1B | 0x5F)

◆ AD6673_REG_204B_CTRL2

#define AD6673_REG_204B_CTRL2 (AD6673_R1B | 0x60)

◆ AD6673_REG_204B_CTRL3

#define AD6673_REG_204B_CTRL3 (AD6673_R1B | 0x61)

◆ AD6673_REG_204B_DID_CFG

#define AD6673_REG_204B_DID_CFG (AD6673_R1B | 0x64)

◆ AD6673_REG_204B_LANE_ASSGN1

#define AD6673_REG_204B_LANE_ASSGN1 (AD6673_R1B | 0x82)

◆ AD6673_REG_204B_LANE_ASSGN2

#define AD6673_REG_204B_LANE_ASSGN2 (AD6673_R1B | 0x83)

◆ AD6673_REG_204B_LID_CFG1

#define AD6673_REG_204B_LID_CFG1 (AD6673_R1B | 0x67)

◆ AD6673_REG_204B_LID_CFG2

#define AD6673_REG_204B_LID_CFG2 (AD6673_R1B | 0x68)

◆ AD6673_REG_204B_LMFC_OFFSET

#define AD6673_REG_204B_LMFC_OFFSET (AD6673_R1B | 0x8B)

◆ AD6673_REG_204B_PARAM_CS_N

#define AD6673_REG_204B_PARAM_CS_N (AD6673_R1B | 0x72)

◆ AD6673_REG_204B_PARAM_F

#define AD6673_REG_204B_PARAM_F (AD6673_R1B | 0x6F)

◆ AD6673_REG_204B_PARAM_HD_CF

#define AD6673_REG_204B_PARAM_HD_CF (AD6673_R1B | 0x75)

◆ AD6673_REG_204B_PARAM_K

#define AD6673_REG_204B_PARAM_K (AD6673_R1B | 0x70)

◆ AD6673_REG_204B_PARAM_M

#define AD6673_REG_204B_PARAM_M (AD6673_R1B | 0x71)

◆ AD6673_REG_204B_PARAM_NP

#define AD6673_REG_204B_PARAM_NP (AD6673_R1B | 0x73)

◆ AD6673_REG_204B_PARAM_S

#define AD6673_REG_204B_PARAM_S (AD6673_R1B | 0x74)

◆ AD6673_REG_204B_PARAM_SCR_L

#define AD6673_REG_204B_PARAM_SCR_L (AD6673_R1B | 0x6E)

◆ AD6673_REG_204B_PRE_EMPHASIS

#define AD6673_REG_204B_PRE_EMPHASIS (AD6673_R1B | 0xA8)

◆ AD6673_REG_204B_QUICK_CFG

#define AD6673_REG_204B_QUICK_CFG (AD6673_R1B | 0x5E)

◆ AD6673_REG_204B_RESV1

#define AD6673_REG_204B_RESV1 (AD6673_R1B | 0x76)

◆ AD6673_REG_204B_RESV2

#define AD6673_REG_204B_RESV2 (AD6673_R1B | 0x77)

◆ AD6673_REG_BIST

#define AD6673_REG_BIST (AD6673_R1B | 0x0E | SHADOW(4))

◆ AD6673_REG_BIST_MISR

#define AD6673_REG_BIST_MISR (AD6673_R2B | 0x25)

◆ AD6673_REG_CH_INDEX

#define AD6673_REG_CH_INDEX (AD6673_R1B | 0x05)

◆ AD6673_REG_CHIP_ID

#define AD6673_REG_CHIP_ID (AD6673_R1B | 0x01)

◆ AD6673_REG_CHIP_INFO

#define AD6673_REG_CHIP_INFO (AD6673_R1B | 0x02)

◆ AD6673_REG_CLOCK

#define AD6673_REG_CLOCK (AD6673_R1B | 0x09 | SHADOW(1))

◆ AD6673_REG_CLOCK_DIV

#define AD6673_REG_CLOCK_DIV (AD6673_R1B | 0x0B | SHADOW(2))

◆ AD6673_REG_CML

#define AD6673_REG_CML (AD6673_R1B | 0x15)

◆ AD6673_REG_DCC_CTRL

#define AD6673_REG_DCC_CTRL (AD6673_R1B | 0x40 | SHADOW(11))

◆ AD6673_REG_DCC_VAL

#define AD6673_REG_DCC_VAL (AD6673_R2B | 0x42 | SHADOW(12))

◆ AD6673_REG_DEVICE_UPDATE

#define AD6673_REG_DEVICE_UPDATE (AD6673_R1B | 0xFF)

◆ AD6673_REG_FAST_DETECT

#define AD6673_REG_FAST_DETECT (AD6673_R1B | 0x45 | SHADOW(13))

◆ AD6673_REG_FD_DWELL_TIME

#define AD6673_REG_FD_DWELL_TIME (AD6673_R2B | 0x4C | SHADOW(16))

◆ AD6673_REG_FD_LOWER_THD

#define AD6673_REG_FD_LOWER_THD (AD6673_R2B | 0x4A | SHADOW(15))

◆ AD6673_REG_FD_UPPER_THD

#define AD6673_REG_FD_UPPER_THD (AD6673_R2B | 0x48 | SHADOW(14))

◆ AD6673_REG_NSR_CTRL

#define AD6673_REG_NSR_CTRL (AD6673_R1B | 0x3C | SHADOW(9))

◆ AD6673_REG_NSR_TUNING

#define AD6673_REG_NSR_TUNING (AD6673_R1B | 0x3E | SHADOW(10))

◆ AD6673_REG_OFFSET

#define AD6673_REG_OFFSET (AD6673_R1B | 0x10 | SHADOW(5))

◆ AD6673_REG_OFFSET_ADJUST

#define AD6673_REG_OFFSET_ADJUST ( x )

Value:

(((x) & 0x3F) << 0)

◆ AD6673_REG_OUT_MODE

#define AD6673_REG_OUT_MODE (AD6673_R1B | 0x14 | SHADOW(6))

◆ AD6673_REG_PDWN

#define AD6673_REG_PDWN (AD6673_R1B | 0x08)

◆ AD6673_REG_PLL_ENCODE

#define AD6673_REG_PLL_ENCODE (AD6673_R1B | 0x21)

◆ AD6673_REG_PLL_STAT

#define AD6673_REG_PLL_STAT (AD6673_R1B | 0x0A)

◆ AD6673_REG_SPI_CFG

#define AD6673_REG_SPI_CFG (AD6673_R1B | 0x00)

◆ AD6673_REG_SYS_CTRL

#define AD6673_REG_SYS_CTRL (AD6673_R1B | 0x3A | SHADOW(8))

◆ AD6673_REG_TEST

#define AD6673_REG_TEST (AD6673_R1B | 0x0D | SHADOW(3))

◆ AD6673_REG_USER_TEST1

#define AD6673_REG_USER_TEST1 (AD6673_R2B | 0x1A)

◆ AD6673_REG_USER_TEST2

#define AD6673_REG_USER_TEST2 (AD6673_R2B | 0x1C)

◆ AD6673_REG_USER_TEST3

#define AD6673_REG_USER_TEST3 (AD6673_R2B | 0x1E)

◆ AD6673_REG_USER_TEST4

#define AD6673_REG_USER_TEST4 (AD6673_R2B | 0x20)

◆ AD6673_REG_VREF

#define AD6673_REG_VREF (AD6673_R1B | 0x18 | SHADOW(7))

◆ AD6673_SPI_CFG_LSB_FIRST

#define AD6673_SPI_CFG_LSB_FIRST ((1 << 6) | (1 << 1))

◆ AD6673_SPI_CFG_SOFT_RST

#define AD6673_SPI_CFG_SOFT_RST ((1 << 5) | (1 << 2))

◆ AD6673_SYS_CTRL_REALIGN_ON_SYNCINB

#define AD6673_SYS_CTRL_REALIGN_ON_SYNCINB (1 << 4)

◆ AD6673_SYS_CTRL_REALIGN_ON_SYSREF

#define AD6673_SYS_CTRL_REALIGN_ON_SYSREF (1 << 3)

◆ AD6673_SYS_CTRL_SYNCINB_EN

#define AD6673_SYS_CTRL_SYNCINB_EN (1 << 0)

◆ AD6673_SYS_CTRL_SYSREF_EN

#define AD6673_SYS_CTRL_SYSREF_EN (1 << 1)

◆ AD6673_SYS_CTRL_SYSREF_MODE

#define AD6673_SYS_CTRL_SYSREF_MODE (1 << 2)

◆ AD6673_TEST_OUTPUT_TEST

#define AD6673_TEST_OUTPUT_TEST ( x )

Value:

(((x) & 0xF) << 0)

◆ AD6673_TEST_RST_PN_LONG

#define AD6673_TEST_RST_PN_LONG (1 << 5)

◆ AD6673_TEST_RST_PN_SHOR

#define AD6673_TEST_RST_PN_SHOR (1 << 4)

◆ AD6673_TEST_USER_TEST_MODE

#define AD6673_TEST_USER_TEST_MODE ( x )

Value:

(((x) & 0x3) << 6)

◆ AD6673_TRANSF_LEN

#define AD6673_TRANSF_LEN ( x )

Value:

(((x) >> 8) & 0xFF)

◆ AD6673_VREF_FS_ADJUST

#define AD6673_VREF_FS_ADJUST ( x )

Value:

(((x) & 0x1F) << 0)

◆ AD6673_WRITE

#define AD6673_WRITE (0 << 15)

◆ SHADOW

#define SHADOW ( x )

Value:

((x) << 16)

Enumeration Type Documentation

◆ shadow_registers

enum shadow_registers

Enumerator
AD6673_SHD_REG_CLOCK
AD6673_SHD_REG_CLOCK_DIV
AD6673_SHD_REG_TEST
AD6673_SHD_REG_BIST
AD6673_SHD_REG_OFFSET
AD6673_SHD_REG_OUT_MODE
AD6673_SHD_REG_VREF
AD6673_SHD_REG_SYS_CTRL
AD6673_REG_SHD_NSR_CTRL
AD6673_REG_SHD_NSR_TUNING
AD6673_SHD_REG_DCC_CTRL
AD6673_SHD_REG_DCC_VAL
AD6673_SHD_REG_FAST_DETECT
AD6673_SHD_REG_FD_UPPER_THD
AD6673_SHD_REG_FD_LOWER_THD
AD6673_SHD_REG_FD_DWELL_TIME
SHADOW_REGISTER_COUNT

Function Documentation

◆ ad6673_bist_enable()

int32_t ad6673_bist_enable	(	struct ad6673_dev *	dev,
		int32_t	enable )

Enables the Build-In-Self-Test.

Parameters

dev	- The device structure.
enable	- enable option.

Returns: Returns negative error code or the state of the enable bit.

◆ ad6673_bist_reset()

int32_t ad6673_bist_reset	(	struct ad6673_dev *	dev,
		int32_t	reset )

Resets the Build-In-Self-Test.

Parameters

dev	- The device structure.
reset	- reset option.

Returns: Returns negative error code or the state of the reset bit.

◆ ad6673_chip_pwr_mode()

int32_t ad6673_chip_pwr_mode	(	struct ad6673_dev *	dev,
		int32_t	mode )

Configures the power mode of the chip.

Parameters

dev	- The device structure.
mode	- The power mode. Example: 00 � normal operation(default); 01 � power-down; 10 - standby.

Returns: Returns negative error code or the set power mode.

◆ ad6673_dcc_bandwidth()

int32_t ad6673_dcc_bandwidth	(	struct ad6673_dev *	dev,
		int32_t	bw )

Selects the bandwidth value for the DC correction circuit.

Parameters

dev	- The device structure.
bw	- DC correction bandwidth. Example: 0 - 2387.32 Hz at Sample Rate of 245.76 MSPS 1 - 1193.66 Hz at Sample Rate of 245.76 MSPS ... 13 - 0.29 Hz at Sample Rate of 245.76 MSPS

Returns: Returns negative error code or the state of the bandwidth bits.

◆ ad6673_dcc_enable()

int32_t ad6673_dcc_enable	(	struct ad6673_dev *	dev,
		int32_t	enable )

Enables DC correction for use in the output data signal path.

Parameters

dev	- The device structure.
enable	- enable option. Example: 0 - correction off 1 - correction on

Returns: Returns negative error code or the status of the enable bit.

◆ ad6673_dcc_freeze()

int32_t ad6673_dcc_freeze	(	struct ad6673_dev *	dev,
		int32_t	freeze )

Freezes DC correction value.

Parameters

dev	- The device structure.
freeze	- freeze option. Example: 0 - calculates the correction value 1 - freezes the DC correction at its current state

Returns: Returns negative error code or the status of the freeze bit.

◆ ad6673_fast_detect_setup()

int32_t ad6673_fast_detect_setup ( struct ad6673_dev * dev )

Configures the Fast-Detect module.

Parameters

dev	- The device structure.

Returns: Returns negative error code or 0 in case of success.

◆ ad6673_jesd204b_invert_logic()

int32_t ad6673_jesd204b_invert_logic	(	struct ad6673_dev *	dev,
		int32_t	invert )

Inverts the logic of JESD204B bits.

Parameters

dev	- The device structure.
invert	- Invert option. Example: 1 - Activates the inverted mode 0 - Activates the normal mode

Returns: Returns negative error code or the set mode.

◆ ad6673_jesd204b_pwr_mode()

int32_t ad6673_jesd204b_pwr_mode	(	struct ad6673_dev *	dev,
		int32_t	mode )

Configures the power mode of the JESD204B data transmit block.

Parameters

dev	- The device structure.
mode	- The power mode. Example: 00 � normal operation(default); 01 � power-down; 10 - standby.

Returns: Returns negative error code or the set power mode.

◆ ad6673_jesd204b_select_test_injection_point()

int32_t ad6673_jesd204b_select_test_injection_point	(	struct ad6673_dev *	dev,
		int32_t	inj_point )

Selects the point in the processing path of a lane, where the test data will be inserted.

Parameters

dev	- The device structure.
inj_point	- The point in the processing path of a lane. Example: 1 - a 10-bit data is inserted at 8B/10B ENCODER output 2 - a 8-bit at scrambler input

Returns: Returns negative error code or the status of the data injection point bit.

◆ ad6673_jesd204b_setup()

int32_t ad6673_jesd204b_setup ( struct ad6673_dev * dev )

Configures the JESD204B interface.

Parameters

dev	- The device structure.

Returns: Returns negative error code or 0 in case of success.

◆ ad6673_jesd204b_test_mode()

int32_t ad6673_jesd204b_test_mode	(	struct ad6673_dev *	dev,
		int32_t	test_mode )

Selects a JESD204B test mode.

Parameters

dev	- The device structure.
test_mode	- mode option. Example: 0 - test mode disabled 1 - alternating checker board 2 - 1/0 word toggle 3 - PN23 sequence 4 - PN9 sequence 5 - continuous/repeat user test mode 6 - single user test mode 7 - reserved 8 - modified RPAT test sequence 12 - PN7 sequence 13 - PN15 sequence

Returns: Returns the set test mode or negative error code.

◆ ad6673_nsr_bandwidth_mode()

int32_t ad6673_nsr_bandwidth_mode	(	struct ad6673_dev *	dev,
		int32_t	mode )

Selects the NSR Bandwidth mode.

Parameters

dev	- The device structure.
mode	- mode option. Example: 0 - 22% 1 - 33%

Returns: Returns negative error code or the status of the mode bit.

◆ ad6673_nsr_enable()

int32_t ad6673_nsr_enable	(	struct ad6673_dev *	dev,
		int32_t	enable )

Enables the Noise shaped requantizer(NRS).

Parameters

dev	- The device structure.
enable	- enable option. Example: 0 - disable 1 - enable

Returns: Returns negative error code or the status of the enable bit.

◆ ad6673_nsr_tuning_freq()

int32_t ad6673_nsr_tuning_freq	(	int64_t	tune_freq,
		int64_t	f_adc,
		struct ad6673_type_band *	p_band )

Sets the NSR frequency range.

Parameters

tune_freq	- The center frequency of noise transfer function(NTF)
f_adc	- ADC sample rate
p_band	- A pointer to a ad6673_typeBand structure. This parameter acts as an output parameter that returns the values of the center frequency, f0 frequency and f1 frequency set by this function

Returns: Returns the set tune word.

◆ ad6673_offset_adj()

int32_t ad6673_offset_adj	(	struct ad6673_dev *	dev,
		int32_t	adj )

Sets the offset adjustment.

Parameters

dev	- The device structure.
adj	- The offset adjust value in LSBs from +31 to -32.

Returns: Returns negative error code or the set offset adjustment.

◆ ad6673_output_disable()

int32_t ad6673_output_disable	(	struct ad6673_dev *	dev,
		int32_t	en )

Disables (1) or enables (0) the data output. Note: This function modifies a shadowed register, therefore a call of ad6673_transfer() is required for the internal update to take place.

Disables (1) or enables (0) the data output.

Parameters

dev	- The device structure.
en	- Enable option. Example: 1 - Disables the data output; 0 - Enables the data output(default).

Returns: Returns negative error code or the output disable state.

◆ ad6673_output_format()

int32_t ad6673_output_format	(	struct ad6673_dev *	dev,
		int32_t	format )

Specifies the output format. Note: This function modifies a shadowed register, therefore a call of ad6673_transfer() is required for the internal update to take place.

Specifies the output format.

Parameters

dev	- The device structure.
format	- The output format. Example: 0 � offset binary(default); 1 � two's complement;

Returns: Returns negative error code or the set output format.

◆ ad6673_output_invert()

int32_t ad6673_output_invert	(	struct ad6673_dev *	dev,
		int32_t	invert )

Activates the inverted (1) or normal (0) output mode. Note: This function modifies a shadowed register, therefore a call of ad6673_transfer() is required for the internal update to take place.

Activates the inverted (1) or normal (0) output mode.

Parameters

dev	- The device structure.
invert	- Invert option. Example: 1 - Activates the inverted output mode; 0 - Activates the normal output mode(default).

Returns: Returns negative error code or the set output mode.

◆ ad6673_read()

int32_t ad6673_read	(	struct ad6673_dev *	dev,
		int32_t	register_address )

Reads the value of the selected register.

Parameters

dev	- The device structure.
register_address	- The address of the register to read.

Returns: reg_value - The register's value or negative error code.

◆ ad6673_remove()

int32_t ad6673_remove ( struct ad6673_dev * dev )

Free the resources allocated by ad6673_setup().

Parameters

dev	- The device structure.

Returns: 0 in case of success, negative error code otherwise.

◆ ad6673_reset_pn23()

int32_t ad6673_reset_pn23	(	struct ad6673_dev *	dev,
		int32_t	rst )

Sets (1) or clears (0) the reset long PN sequence bit(PN23).

Parameters

dev	- The device structure.
rst	- Reset option. Example: 1 - The PN sequence is held in reset; 0 - The PN sequence resumes from the seed value(0x3AFF).

Returns: Returns negative error code or the set PN23 status.

◆ ad6673_reset_pn9()

int32_t ad6673_reset_pn9	(	struct ad6673_dev *	dev,
		int32_t	rst )

Sets (1) or clears (0) the reset short PN sequence bit(PN9).

Parameters

dev	- The device structure.
rst	- Reset option. Example: 1 - The PN sequence is held in reset; 0 - The PN sequence resumes from the seed value(0x92).

Returns: Returns negative error code or the set PN9 status.

◆ ad6673_select_channel_for_config()

int32_t ad6673_select_channel_for_config	(	struct ad6673_dev *	dev,
		int32_t	channel )

Selects a channel as the current channel for further configurations.

Parameters

dev	- The device structure.
channel	- Channel option. Example 1 - channel A 2 - channel B 3 - channel A and channel B

Returns: Returns negative error code or the selected channel.

◆ ad6673_set_user_pattern()

int32_t ad6673_set_user_pattern	(	struct ad6673_dev *	dev,
		int32_t	pattern_no,
		int32_t	user_pattern )

Configures a User Test Pattern.

Parameters

dev	- The device structure.
pattern_no	- Selects the patterns to be configured. Range 1..4.
user_pattern	- Users's pattern.

Returns: Returns negative error code or the selected user pattern.

◆ ad6673_setup()

int32_t ad6673_setup	(	struct ad6673_dev **	device,
		struct ad6673_init_param	init_param )

Configures the device.

Parameters

device	- The device structure.
init_param	- The structure that contains the device initial parameters.

Returns: Returns negative error code or 0 in case of success.

◆ ad6673_soft_reset()

int32_t ad6673_soft_reset ( struct ad6673_dev * dev )

Resets all registers to their default values.

Parameters

dev	- The device structure.

Returns: Returns negative error code or 0 in case of success.

◆ ad6673_test_mode()

int32_t ad6673_test_mode	(	struct ad6673_dev *	dev,
		int32_t	mode )

Sets the ADC's test mode.

Parameters

dev	- The device structure.
mode	- ADC test mode. Example: 0 -> off(default) 1 -> midscale short 2 -> +FS short 3 -> -FS short 4 -> checkerboard output 5 -> PN sequence long 6 -> PN 9 short 7 -> one/zero word toggle 8 -> user test mode 9 to 14 -> unused 15 -> ramp output

Returns: Returns the set test mode or negative error code.

◆ ad6673_transfer()

int32_t ad6673_transfer ( struct ad6673_dev * dev )

Initiates a transfer and waits for the operation to end. Note: This function may be called after a shadowed register was written, so that the internal update can actually take place.

Initiates a transfer and waits for the operation to end.

Parameters

dev	- The device structure.

Returns: Negative error code or 0 in case of success.

◆ ad6673_write()

int32_t ad6673_write	(	struct ad6673_dev *	dev,
		int32_t	register_address,
		int32_t	register_value )

Writes a value to the selected register.

Parameters

dev	- The device structure.
register_address	- The address of the register to write to.
register_value	- The value to write to the register.

Returns: Returns 0 in case of success or negative error code.

Classes

Macros

Enumerations

Functions

Detailed Description

Macro Definition Documentation

◆ AD6673_204B_CTRL1_ILAS_MODE

◆ AD6673_204B_CTRL1_POWER_DOWN

◆ AD6673_204B_CTRL1_TAIL_BITS

◆ AD6673_204B_CTRL1_TEST_SAMPLE_EN

◆ AD6673_204B_CTRL2_INVERT_JESD_BITS

◆ AD6673_204B_CTRL3_JESD_TEST_MODE

◆ AD6673_204B_CTRL3_TEST_DATA_INJ_PT

◆ AD6673_204B_LANE_ASSGN1

◆ AD6673_204B_LANE_ASSGN2

◆ AD6673_204B_LMFC_OFFSET

◆ AD6673_204B_PARAM_CS_N_ADC_RESOLUTION

◆ AD6673_204B_PARAM_CS_N_NR_CTRL_BITS

◆ AD6673_204B_PARAM_HD_CF_CF_VAL

◆ AD6673_204B_PARAM_HD_CF_HD_VAL

◆ AD6673_204B_PARAM_NP_JESD_N_VAL

◆ AD6673_204B_PARAM_NP_JESD_SUBCLASS

◆ AD6673_204B_PARAM_S

◆ AD6673_204B_PARAM_SCR_L_LANES

◆ AD6673_204B_PARAM_SCR_L_SCRAMBLING

◆ AD6673_204B_QUICK_CFG

◆ AD6673_ADDR

◆ AD6673_BIST_ENABLE

◆ AD6673_BIST_RESET

◆ AD6673_CH_INDEX_ADC_A

◆ AD6673_CH_INDEX_ADC_B

◆ AD6673_CLOCK_DIV_PHASE

◆ AD6673_CLOCK_DIV_RATIO

◆ AD6673_CLOCK_DUTY_CYCLE

◆ AD6673_CLOCK_SELECTION

◆ AD6673_CML_DIFF_OUT_LEVEL

◆ AD6673_CNT

◆ AD6673_DCC_CTRL_DCC_BW

◆ AD6673_DCC_CTRL_DCC_EN

◆ AD6673_DCC_CTRL_FREEZE_DCC

◆ AD6673_DEVICE_UPDATE_SW

◆ AD6673_FAST_DETECT_FORCE_FDA_FDB_PIN

◆ AD6673_FAST_DETECT_FORCE_FDA_FDB_VAL

◆ AD6673_FAST_DETECT_OUTPUT_ENABLE

◆ AD6673_FAST_DETECT_PIN_FCT

◆ AD6673_NSR_CTRL_BW_MODE

◆ AD6673_NSR_CTRL_ENABLE

◆ AD6673_NSR_TUNING

◆ AD6673_OUT_MODE_DATA_FORMAT

◆ AD6673_OUT_MODE_DISABLE

◆ AD6673_OUT_MODE_INVERT_DATA

◆ AD6673_OUT_MODE_JTX_BIT_ASSIGN

◆ AD6673_PDWN_CHIP

◆ AD6673_PDWN_EXTERN

◆ AD6673_PDWN_JESD204B

◆ AD6673_PDWN_JTX

◆ AD6673_PLL_ENCODE

◆ AD6673_PLL_STAT_204B_LINK_RDY

◆ AD6673_PLL_STAT_LOCKED

◆ AD6673_R1B

◆ AD6673_R2B

◆ AD6673_R3B

◆ AD6673_READ

◆ AD6673_REG_204B_BID_CFG

◆ AD6673_REG_204B_CHKSUM0

◆ AD6673_REG_204B_CHKSUM1

◆ AD6673_REG_204B_CTRL1

◆ AD6673_REG_204B_CTRL2

◆ AD6673_REG_204B_CTRL3

◆ AD6673_REG_204B_DID_CFG

◆ AD6673_REG_204B_LANE_ASSGN1

◆ AD6673_REG_204B_LANE_ASSGN2

◆ AD6673_REG_204B_LID_CFG1

◆ AD6673_REG_204B_LID_CFG2

◆ AD6673_REG_204B_LMFC_OFFSET

◆ AD6673_REG_204B_PARAM_CS_N

◆ AD6673_REG_204B_PARAM_F

◆ AD6673_REG_204B_PARAM_HD_CF

◆ AD6673_REG_204B_PARAM_K

◆ AD6673_REG_204B_PARAM_M