Header file for the ad713x Driver. More...

#include <stdbool.h>
#include <stdio.h>
#include "no_os_spi.h"
#include "no_os_gpio.h"
#include "no_os_util.h"

Include dependency graph for ad713x.h:

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Go to the source code of this file.

Classes
struct	ad713x_dev
	AD713x driver handler structure. More...

struct	ad713x_init_param
	AD713x driver initialization structure. More...

Macros
#define	AD713X_REG_INTERFACE_CONFIG_A 0x00

#define	AD713X_REG_INTERFACE_CONFIG_B 0x01

#define	AD713X_REG_DEVICE_CONFIG 0x02

#define	AD713X_REG_CHIP_TYPE 0x03

#define	AD713X_REG_PRODUCT_ID_LSB 0x04

#define	AD713X_REG_PRODUCT_ID_MSB 0x05

#define	AD713X_REG_CHIP_GRADE 0x06

#define	AD713X_REG_CHIP_INDEX 0x07

#define	AD713X_REG_SCTATCH_PAD 0x0A

#define	AD713X_REG_SPI_REVISION 0x0B

#define	AD713X_REG_VENDOR_ID_LSB 0x0C

#define	AD713X_REG_VENDOR_ID_MSB 0x0D

#define	AD713X_REG_STREAM_MODE 0x0E

#define	AD713X_REG_TRANSFER_REGISTER 0x0F

#define	AD713X_REG_DEVICE_CONFIG1 0x10

#define	AD713X_REG_DATA_PACKET_CONFIG 0x11

#define	AD713X_REG_DIGITAL_INTERFACE_CONFIG 0x12

#define	AD713X_REG_POWER_DOWN_CONTROL 0x13

#define	AD713X_REG_AIN_RANGE_SELECT 0x14

#define	AD713X_REG_DEVICE_STATUS 0x15

#define	AD713X_REG_ODR_VAL_INT_LSB 0x16

#define	AD713X_REG_ODR_VAL_INT_MID 0x17

#define	AD713X_REG_ODR_VAL_INT_MSB 0x18

#define	AD713X_REG_ODR_VAL_FLT_LSB 0x19

#define	AD713X_REG_ODR_VAL_FLT_MID0 0x1A

#define	AD713X_REG_ODR_VAL_FLT_MID1 0x1B

#define	AD713X_REG_ODR_VAL_FLT_MSB 0x1C

#define	AD713X_REG_CHANNEL_ODR_SELECT 0x1D

#define	AD713X_REG_CHAN_DIG_FILTER_SEL 0x1E

#define	AD713X_REG_FIR_BW_SEL 0x1F

#define	AD713X_REG_GPIO_DIR_CTRL 0x20

#define	AD713X_REG_GPIO_DATA 0x21

#define	AD713X_REG_ERROR_PIN_SRC_CONTROL 0x22

#define	AD713X_REG_ERROR_PIN_CONTROL 0x23

#define	AD713X_REG_VCMBUF_CTRL 0x24

#define	AD713X_REG_DIAGNOSTIC_CONTROL 0x25

#define	AD713X_REG_MPC_CONFIG 0x26

#define	AD713X_REG_CH0_GAIN_LSB 0x27

#define	AD713X_REG_CH0_GAIN_MID 0x28

#define	AD713X_REG_CH0_GAIN_MSB 0x29

#define	AD713X_REG_CH0_OFFSET_LSB 0x2A

#define	AD713X_REG_CH0_OFFSET_MID 0x2B

#define	AD713X_REG_CH0_OFFSET_MSB 0x2C

#define	AD713X_REG_CH1_GAIN_LSB 0x2D

#define	AD713X_REG_CH1_GAIN_MID 0x2E

#define	AD713X_REG_CH1_GAIN_MSB 0x2F

#define	AD713X_REG_CH1_OFFSET_LSB 0x30

#define	AD713X_REG_CH1_OFFSET_MID 0x31

#define	AD713X_REG_CH1_OFFSET_MSB 0x32

#define	AD713X_REG_CH2_GAIN_LSB 0x33

#define	AD713X_REG_CH2_GAIN_MID 0x34

#define	AD713X_REG_CH2_GAIN_MSB 0x35

#define	AD713X_REG_CH2_OFFSET_LSB 0x36

#define	AD713X_REG_CH2_OFFSET_MID 0x37

#define	AD713X_REG_CH2_OFFSET_MSB 0x38

#define	AD713X_REG_CH3_GAIN_LSB 0x39

#define	AD713X_REG_CH3_GAIN_MID 0x3A

#define	AD713X_REG_CH3_GAIN_MSB 0x3B

#define	AD713X_REG_CH3_OFFSET_LSB 0x3C

#define	AD713X_REG_CH3_OFFSET_MID 0x3D

#define	AD713X_REG_CH3_OFFSET_MSB 0x3E

#define	AD713X_REG_MCLK_COUNTER 0x3F

#define	AD713X_REG_DIG_FILTER_OFUF 0x40

#define	AD713X_REG_DIG_FILTER_SETTLED 0x41

#define	AD713X_REG_INTERNAL_ERROR 0x42

#define	AD713X_REG_POWER_OV_ERROR_1 0x43

#define	AD713X_REG_POWER_UV_ERROR_1 0x44

#define	AD713X_REG_POWER_OV_ERROR_2 0x45

#define	AD713X_REG_POWER_UV_ERROR_2 0x46

#define	AD713X_REG_SPI_ERROR 0x47

#define	AD713X_REG_AIN_OR_ERROR 0x48

#define	AD713X_REG_AVDD5_VALUE 0x49

#define	AD713X_REG_DVDD5_VALUE 0x4A

#define	AD713X_REG_VREF_VALUE 0x4B

#define	AD713X_REG_LDOIN_VALUE 0x4C

#define	AD713X_REG_AVDD1V8_VALUE 0x4D

#define	AD713X_REG_DVDD1V8_VALUE 0x4E

#define	AD713X_REG_CLKVDD_VALUE 0x4F

#define	AD713X_REG_IOVDD_VALUE 0x50

#define	AD713X_REG_TEMPERATURE_DATA 0x51

#define	AD713X_INT_CONFIG_A_SOFT_RESET_MSK NO_OS_BIT(7)

#define	AD713X_INT_CONFIG_A_ADDR_ASC_BIT_MSK NO_OS_BIT(5)

#define	AD713X_INT_CONFIG_A_SDO_ACTIVE_BIT_MSK NO_OS_BIT(4)

#define	AD713X_INT_CONFIG_A_SOFT_RESET_MIRR_MSK NO_OS_BIT(0)

#define	AD713X_INT_CONFIG_A_ADDR_ASC_MIRR_MSK NO_OS_BIT(2)

#define	AD713X_INT_CONFIG_A_SDO_ACTIVE_MIRR_MSK NO_OS_BIT(3)

#define	AD713X_INT_CONFIG_B_SINGLE_INSTR_MSK NO_OS_BIT(7)

#define	AD713X_INT_CONFIG_B_M_S_RD_CTRL_MSK NO_OS_BIT(5)

#define	AD713X_INT_CONFIG_B_DIG_IF_RST_MSK NO_OS_BIT(1)

#define	AD713X_DEV_CONFIG_OP_IN_PROGRESS_MSK NO_OS_BIT(5)

#define	AD713X_DEV_CONFIG_NO_CHIP_ERR_MSK NO_OS_BIT(4)

#define	AD713X_DEV_CONFIG_PWR_MODE_MSK NO_OS_BIT(0)

#define	AD713X_CHIP_TYPE_BITS_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_CHIP_TYPE_BITS_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_CHIP_TYPE 0x07

#define	AD713X_PRODUCT_ID_LSB_BITS_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_PRODUCT_ID_LSB_BITS_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_PRODUCT_ID_MSB_BITS_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_PRODUCT_ID_MSB_BITS_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_CHIP_GRADE_PROD_GRADE_BITS_MSK NO_OS_GENMASK(7, 4)

#define	AD713X_CHIP_GRADE_PROD_GRADE_BITS_MODE(x) (((x) & 0x0F) << 4)

#define	AD713X_CHIP_GRADE_DEV_VERSION_BITS_MSK NO_OS_GENMASK(3, 0)

#define	AD713X_CHIP_GRADE_DEV_VERSION_BITS_MODE(x) (((x) & 0x0F) << 0)

#define	AD713X_SILICON_REV_ID_BITS_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_SILICON_REV_ID_BITS_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_SCRATCH_PAD_BITS_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_SCRATCH_PAD_BITS_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_SPI_REVISION_BITS_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_SPI_REVISION_BITS_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_VENDOR_ID_LSB_BITS_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_VENDOR_ID_LSB_BITS_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_VENDOR_ID_MSB_BITS_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_VENDOR_ID_MSB_BITS_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_STREAM_MODE_BITS_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_STREAM_MODE_BITS_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_TRANSFER_MASTER_SLAVE_TX_BIT_MSK NO_OS_BIT(0)

#define	AD713X_DEV_CONFIG1_MPC_MAGPHA_EN_MSK NO_OS_BIT(6)

#define	AD713X_DEV_CONFIG1_MPC_MAG_EN_MSK NO_OS_BIT(5)

#define	AD713X_DEV_CONFIG1_AA_MODE_MSK NO_OS_BIT(4)

#define	AD713X_DEV_CONFIG1_SDO_PIN_SRC_SEL_MSK NO_OS_BIT(2)

#define	AD713X_DEV_CONFIG1_REF_GAIN_CORR_EN_MSK NO_OS_BIT(1)

#define	AD713X_DEV_CONFIG1_CLKOUT_EN_MSK NO_OS_BIT(0)

#define	AD713X_DATA_PACKET_CONFIG_CRC_POLY_RST_MSK NO_OS_BIT(7)

#define	AD713X_DATA_PACKET_CONFIG_FRAME_MSK NO_OS_GENMASK(6, 4)

#define	AD713X_DATA_PACKET_CONFIG_FRAME_MODE(x) (((x) & 0x7) << 4)

#define	AD713X_DATA_PACKET_CONFIG_DCLK_FREQ_MSK NO_OS_GENMASK(3, 0)

#define	AD713X_DATA_PACKET_CONFIG_DCLK_FREQ_MODE(x) (((x) & 0xF) << 0)

#define	AD713X_DIG_INT_CONFIG_DAISY_CHAIN_NUM_MSK NO_OS_GENMASK(7, 4)

#define	AD713X_DIG_INT_CONFIG_DAISY_CHAIN_NUM_MODE(x) (((x) & 0xF) << 4)

#define	AD713X_DIG_INT_CONFIG_AVG_SEL_MSK NO_OS_GENMASK(3, 2)

#define	AD713X_DIG_INT_CONFIG_AVG_SEL_MODE(x) (((x) & 0x3) << 2)

#define	AD713X_DIG_INT_CONFIG_FORMAT_MSK NO_OS_GENMASK(1, 0)

#define	AD713X_DIG_INT_CONFIG_FORMAT_MODE(x) (((x) & 0x3) << 0)

#define	AD713X_PWRDN_CTRL_PWRDN_CH_MSK(ch) NO_OS_BIT(ch)

#define	AD713X_PWRDN_CTRL_PWRDN_AUXADC_MSK NO_OS_BIT(2)

#define	AD713X_PWRDN_CTRL_PWRDN_LDO_MSK NO_OS_BIT(1)

#define	AD713X_PWRDN_CTRL_PWRDN_SLEEP_MODE_EN_MSK NO_OS_BIT(0)

#define	AD713X_AIN_RANGE_SEL_CH_MSK(ch) NO_OS_BIT(ch)

#define	AD713X_DEV_STAT_DCLKMODE_MSK NO_OS_BIT(5)

#define	AD713X_DEV_STAT_DCLKIO_MSK NO_OS_BIT(4)

#define	AD713X_DEV_STAT_MODE_MSK NO_OS_BIT(3)

#define	AD713X_DEV_STAT_CLKSEL_MSK NO_OS_BIT(2)

#define	AD713X_DEV_STAT_FUSE_ECC_MSK NO_OS_BIT(1)

#define	AD713X_DEV_STAT_PLL_LOCK_MSK NO_OS_BIT(0)

#define	AD713X_ODR_VAL_INT_LSB_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_ODR_VAL_INT_LSB_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_ODR_VAL_INT_MID_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_ODR_VAL_INT_MID_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_ODR_VAL_INT_MSB_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_ODR_VAL_INT_MSB_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_ODR_VAL_FLT_LSB_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_ODR_VAL_FLT_LSB_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_ODR_VAL_FLT_MID0_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_ODR_VAL_FLT_MID0_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_ODR_VAL_FLT_MID1_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_ODR_VAL_FLT_MID1_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_ODR_VAL_FLT_MSB_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_ODR_VAL_FLT_MSB_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_ODR_RATE_SEL_CH_MSK(ch) (NO_OS_GENMASK(1, 0) << (2 * ch))

#define	AD713X_ODR_RATE_SEL_CH_MODE(x, ch) (((x) & 0x3) << (2 * ch))

#define	AD713X_DIGFILTER_SEL_CH_MSK(ch) (NO_OS_GENMASK(1, 0) << (2 * ch))

#define	AD713X_DIGFILTER_SEL_CH_MODE(x, ch) (((x) & 0x3) << (2 * ch))

#define	AD713X_FIR_BW_SEL_CH_MSK(ch) NO_OS_BIT(ch)

#define	AD713X_GPIO_IO_CTRL_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_GPIO_IO_CTRL_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_GPIO_DATA_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_GPIO_DATA_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_ERR_PIN_EN_OR_AIN_MSK NO_OS_BIT(5)

#define	AD713X_ERR_PIN_EN_INTERNAL_MSK NO_OS_BIT(4)

#define	AD713X_ERR_PIN_EN_SPI_MSK NO_OS_BIT(3)

#define	AD713X_ERR_PIN_EN_LDO_XOSC_MSK NO_OS_BIT(2)

#define	AD713X_ERR_PIN_EN_TEMP_MSK NO_OS_BIT(1)

#define	AD713X_ERR_PIN_EN_PWR_MSK NO_OS_BIT(0)

#define	AD713X_ERR_PIN_IN_STATUS_MSK NO_OS_BIT(2)

#define	AD713X_ERR_PIN_IN_EN_MSK NO_OS_BIT(1)

#define	AD713X_ERR_PIN_OUT_EN_MSK NO_OS_BIT(0)

#define	AD713X_VCMBUF_CTRL_PWRDN_MSK NO_OS_BIT(6)

#define	AD713X_VCMBUF_CTRL_REF_DIV_SEL_MSK NO_OS_GENMASK(5, 1)

#define	AD713X_VCMBUF_CTRL_REF_DIV_SEL_MODE(x) (((x) & 0x1F) << 1)

#define	AD713X_VCMBUF_CTRL_REF_SEL_MSK NO_OS_BIT(0)

#define	AD713X_DIAGCTRL_ERR_OR_AIN_EN_MSK NO_OS_BIT(5)

#define	AD713X_DIAGCTRL_ERR_PWR_MON_EN_MSK NO_OS_BIT(4)

#define	AD713X_DIAGCTRL_MCLK_CNT_EN_MSK NO_OS_BIT(3)

#define	AD713X_DIAGCTRL_ERR_SPI_CRC_EN_MSK NO_OS_BIT(2)

#define	AD713X_DIAGCTRL_ERR_MM_CRC_EN_MSK NO_OS_BIT(1)

#define	AD713X_DIAGCTRL_FUSE_CRC_CHECK_MSK NO_OS_BIT(0)

#define	AD713X_MPC_CLKDEL_EN_CH_MSK(ch) (NO_OS_GENMASK(1, 0) << (2 * ch))

#define	AD713X_MPC_CLKDEL_EN_CH_MODE(x, ch) (((x) & 0x3) << (2 * ch))

#define	AD713X_CH_GAIN_LSB_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_CH_GAIN_LSB_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_CH_GAIN_MID_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_CH_GAIN_MID_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_CH_GAIN_CAL_SEL_MSK NO_OS_BIT(4)

#define	AD713X_CH_GAIN_MSB_MSK NO_OS_GENMASK(3, 0)

#define	AD713X_CH_GAIN_MSB_MODE(x) (((x) & 0xF) << 0)

#define	AD713X_CH_OFFSET_LSB_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_CH_OFFSET_LSB_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_CH_OFFSET_MID_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_CH_OFFSET_MID_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_CH_OFFSET_CAL_EN_MSK NO_OS_BIT(7)

#define	AD713X_CH_OFFSET_MSB_MSK NO_OS_GENMASK(6, 0)

#define	AD713X_CH_OFFSET_MSB_MODE(x) (((x) & 0x7F) << 0)

#define	AD713X_MCLK_COUNT_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_MCLK_COUNT_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_DIGFILTER_ERR_OFUF_CH_MSK(ch) NO_OS_BIT(ch)

#define	AD713X_DIGFILTER_CH_SETTLED_MSK(ch) NO_OS_BIT(ch)

#define	AD713X_INT_ERR_NO_CLOCK_MSK NO_OS_BIT(5)

#define	AD713X_INT_ERR_TEMP_MSK NO_OS_BIT(4)

#define	AD713X_INT_ERR_DCLK_MSK NO_OS_BIT(3)

#define	AD713X_INT_ERR_FUSE_CRC_MSK NO_OS_BIT(2)

#define	AD713X_INT_ERR_ASRC_MSK NO_OS_BIT(1)

#define	AD713X_INT_ERR_MM_CRC_MSK NO_OS_BIT(0)

#define	AD713X_POWER_ERR_OV_IOVDD_MSK NO_OS_BIT(3)

#define	AD713X_POWER_ERR_OV_CLKVDD_MSK NO_OS_BIT(2)

#define	AD713X_POWER_ERR_OV_DVDD1V8_MSK NO_OS_BIT(1)

#define	AD713X_POWER_ERR_OV_AVDD1V8_MSK NO_OS_BIT(0)

#define	AD713X_POWER_ERR_UV_IOVDD_MSK NO_OS_BIT(3)

#define	AD713X_POWER_ERR_UV_CLKVDD_MSK NO_OS_BIT(2)

#define	AD713X_POWER_ERR_UV_DVDD1V8_MSK NO_OS_BIT(1)

#define	AD713X_POWER_ERR_UV_AVDD1V8_MSK NO_OS_BIT(0)

#define	AD713X_POWER_ERR_OV_VREF_MSK NO_OS_BIT(3)

#define	AD713X_POWER_ERR_OV_LDOIN_MSK NO_OS_BIT(2)

#define	AD713X_POWER_ERR_OV_DVDD5_MSK NO_OS_BIT(1)

#define	AD713X_POWER_ERR_OV_AVDD5_MSK NO_OS_BIT(0)

#define	AD713X_POWER_ERR_UV_VREF_MSK NO_OS_BIT(3)

#define	AD713X_POWER_ERR_UV_LDOIN_MSK NO_OS_BIT(2)

#define	AD713X_POWER_ERR_UV_DVDD5_MSK NO_OS_BIT(1)

#define	AD713X_POWER_ERR_UV_AVDD5_MSK NO_OS_BIT(0)

#define	AD713X_SPI_ERROR_CRC_MSK NO_OS_BIT(3)

#define	AD713X_SPI_ERROR_SCLK_CNT_MSK NO_OS_BIT(2)

#define	AD713X_SPI_ERROR_WRITE_MSK NO_OS_BIT(1)

#define	AD713X_SPI_ERROR_READ_MSK NO_OS_BIT(0)

#define	AD713X_ERR_OR_AIN_MSK(ch) NO_OS_BIT(ch)

#define	AD713X_AVDD5_VALUE_PIN_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_AVDD5_VALUE_PIN_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_DVDD5_VALUE_PIN_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_DVDD5_VALUE_PIN_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_VREF_VALUE_PIN_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_VREF_VALUE_PIN_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_LDOIN_VALUE_PIN_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_LDOIN_VALUE_PIN_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_AVDD1V8_VALUE_PIN_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_AVDD1V8_VALUE_PIN_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_DVDD1V8_VALUE_PIN_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_DVDD1V8_VALUE_PIN_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_CLKVDD_VALUE_PIN_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_CLKVDD_VALUE_PIN_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_IOVDD_VALUE_PIN_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_IOVDD_VALUE_PIN_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_TEMP_DATA_MSK NO_OS_GENMASK(7, 0)

#define	AD713X_TEMP_DATA_MODE(x) (((x) & 0xFF) << 0)

#define	AD713X_REG_READ(x) ((1 << 7) \| (x & 0x7F))

Enumerations
enum	ad713x_supported_dev_ids { ID_AD7132, ID_AD7134, ID_AD7136, ID_AD4134 }
	ID of devices supported by the driver. More...

enum	ad713x_power_mode { LOW_POWER, HIGH_POWER }
	AD713x power modes. More...

enum	ad713x_adc_data_len { ADC_16_BIT_DATA, ADC_24_BIT_DATA, ADC_32_BIT_DATA, INVALID }
	AD713x possible number of bits per data sample. More...

enum	ad713x_crc_header { NO_CRC, CRC_6, CRC_8 }
	AD713x possible data CRC header choices. More...

enum	ad713x_doutx_format { SINGLE_CH_DC, DUAL_CH_DC, QUAD_CH_PO, CH_AVG_MODE }
	AD713x list for possible output modes. More...

enum	ad713x_dig_filter_sel { FIR, SINC6, SINC3, SINC3_50_60_REJ }
	AD713x list of input filters. More...

enum	ad713x_channels { CH0, CH1, CH2, CH3, AD713X_CH_MAX }
	AD713x list of channels. More...

enum	ad717x_mpc_clkdel { DELAY_NONE, DELAY_1_CLOCKS, DELAY_2_CLOCKS }
	AD713x list of clock delays. More...

Functions
int32_t	ad713x_spi_reg_read (struct ad713x_dev dev, uint8_t reg_addr, uint8_t reg_data)
	Read from device. More...

int32_t	ad713x_spi_reg_write (struct ad713x_dev *dev, uint8_t reg_addr, uint8_t reg_data)
	Write to device. More...

int32_t	ad713x_spi_write_mask (struct ad713x_dev *dev, uint8_t reg_addr, uint32_t mask, uint8_t data)
	SPI write to device using a mask. More...

int32_t	ad713x_set_power_mode (struct ad713x_dev *dev, enum ad713x_power_mode mode)
	Device power mode control. More...

int32_t	ad713x_set_out_data_frame (struct ad713x_dev *dev, enum ad713x_adc_data_len adc_data_len, enum ad713x_crc_header crc_header)
	ADC conversion data output frame control. More...

int32_t	ad713x_dout_format_config (struct ad713x_dev *dev, enum ad713x_doutx_format format)
	DOUTx output format configuration. More...

int32_t	ad713x_mag_phase_clk_delay (struct ad713x_dev *dev, bool clk_delay_en)
	Magnitude and phase matching calibration clock delay enable for all channels at 2 clock delay. This function is kept for backwards compatibility with the current application source, but it is deprecated. Use ad713x_mag_phase_clk_delay_chan(). More...

int32_t	ad713x_dig_filter_sel_ch (struct ad713x_dev *dev, enum ad713x_dig_filter_sel filter, enum ad713x_channels ch)
	Digital filter type selection for each channel. More...

int32_t	ad713x_clkout_output_en (struct ad713x_dev *dev, bool enable)
	Enable/Disable CLKOUT output. More...

int32_t	ad713x_ref_gain_correction_en (struct ad713x_dev *dev, bool enable)
	Enable/Disable reference gain correction. More...

int32_t	ad713x_wideband_bw_sel (struct ad713x_dev *dev, enum ad713x_channels ch, uint8_t wb_opt)
	Select the wideband filter bandwidth for a channel. The option is relative to ODR, so it's a fraction of it. More...

int32_t	ad713x_init (struct ad713x_dev *device, struct ad713x_init_param init_param)
	Initialize the device. More...

int32_t	ad713x_remove (struct ad713x_dev *dev)
	Free the resources allocated by ad713x_init(). More...

int32_t	ad713x_spi_reg_dump (struct ad713x_dev *dev)
	Print all registers values for the AD4134 device. Register map has gaps, reg dump function specific for AD4134 dev. More...

int32_t	ad713x_channel_sync (struct ad713x_dev *dev)
	Multidevice synchronization between channels on different devices. More...

Detailed Description

Header file for the ad713x Driver.

Author: SPopa (stefa.nosp@m.n.po.nosp@m.pa@an.nosp@m.alog.nosp@m..com); Andrei Drimbarean (andre.nosp@m.i.dr.nosp@m.imbar.nosp@m.ean@.nosp@m.analo.nosp@m.g.co.nosp@m.m)

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
Neither the name of Analog Devices, Inc. nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Macro Definition Documentation

◆ AD713X_AIN_RANGE_SEL_CH_MSK

#define AD713X_AIN_RANGE_SEL_CH_MSK ( ch ) NO_OS_BIT(ch)

◆ AD713X_AVDD1V8_VALUE_PIN_MODE

#define AD713X_AVDD1V8_VALUE_PIN_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_AVDD1V8_VALUE_PIN_MSK

#define AD713X_AVDD1V8_VALUE_PIN_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_AVDD5_VALUE_PIN_MODE

#define AD713X_AVDD5_VALUE_PIN_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_AVDD5_VALUE_PIN_MSK

#define AD713X_AVDD5_VALUE_PIN_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_CH_GAIN_CAL_SEL_MSK

#define AD713X_CH_GAIN_CAL_SEL_MSK NO_OS_BIT(4)

◆ AD713X_CH_GAIN_LSB_MODE

#define AD713X_CH_GAIN_LSB_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_CH_GAIN_LSB_MSK

#define AD713X_CH_GAIN_LSB_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_CH_GAIN_MID_MODE

#define AD713X_CH_GAIN_MID_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_CH_GAIN_MID_MSK

#define AD713X_CH_GAIN_MID_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_CH_GAIN_MSB_MODE

#define AD713X_CH_GAIN_MSB_MODE ( x ) (((x) & 0xF) << 0)

◆ AD713X_CH_GAIN_MSB_MSK

#define AD713X_CH_GAIN_MSB_MSK NO_OS_GENMASK(3, 0)

◆ AD713X_CH_OFFSET_CAL_EN_MSK

#define AD713X_CH_OFFSET_CAL_EN_MSK NO_OS_BIT(7)

◆ AD713X_CH_OFFSET_LSB_MODE

#define AD713X_CH_OFFSET_LSB_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_CH_OFFSET_LSB_MSK

#define AD713X_CH_OFFSET_LSB_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_CH_OFFSET_MID_MODE

#define AD713X_CH_OFFSET_MID_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_CH_OFFSET_MID_MSK

#define AD713X_CH_OFFSET_MID_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_CH_OFFSET_MSB_MODE

#define AD713X_CH_OFFSET_MSB_MODE ( x ) (((x) & 0x7F) << 0)

◆ AD713X_CH_OFFSET_MSB_MSK

#define AD713X_CH_OFFSET_MSB_MSK NO_OS_GENMASK(6, 0)

◆ AD713X_CHIP_GRADE_DEV_VERSION_BITS_MODE

#define AD713X_CHIP_GRADE_DEV_VERSION_BITS_MODE ( x ) (((x) & 0x0F) << 0)

◆ AD713X_CHIP_GRADE_DEV_VERSION_BITS_MSK

#define AD713X_CHIP_GRADE_DEV_VERSION_BITS_MSK NO_OS_GENMASK(3, 0)

◆ AD713X_CHIP_GRADE_PROD_GRADE_BITS_MODE

#define AD713X_CHIP_GRADE_PROD_GRADE_BITS_MODE ( x ) (((x) & 0x0F) << 4)

◆ AD713X_CHIP_GRADE_PROD_GRADE_BITS_MSK

#define AD713X_CHIP_GRADE_PROD_GRADE_BITS_MSK NO_OS_GENMASK(7, 4)

◆ AD713X_CHIP_TYPE

#define AD713X_CHIP_TYPE 0x07

◆ AD713X_CHIP_TYPE_BITS_MODE

#define AD713X_CHIP_TYPE_BITS_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_CHIP_TYPE_BITS_MSK

#define AD713X_CHIP_TYPE_BITS_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_CLKVDD_VALUE_PIN_MODE

#define AD713X_CLKVDD_VALUE_PIN_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_CLKVDD_VALUE_PIN_MSK

#define AD713X_CLKVDD_VALUE_PIN_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_DATA_PACKET_CONFIG_CRC_POLY_RST_MSK

#define AD713X_DATA_PACKET_CONFIG_CRC_POLY_RST_MSK NO_OS_BIT(7)

◆ AD713X_DATA_PACKET_CONFIG_DCLK_FREQ_MODE

#define AD713X_DATA_PACKET_CONFIG_DCLK_FREQ_MODE ( x ) (((x) & 0xF) << 0)

◆ AD713X_DATA_PACKET_CONFIG_DCLK_FREQ_MSK

#define AD713X_DATA_PACKET_CONFIG_DCLK_FREQ_MSK NO_OS_GENMASK(3, 0)

◆ AD713X_DATA_PACKET_CONFIG_FRAME_MODE

#define AD713X_DATA_PACKET_CONFIG_FRAME_MODE ( x ) (((x) & 0x7) << 4)

◆ AD713X_DATA_PACKET_CONFIG_FRAME_MSK

#define AD713X_DATA_PACKET_CONFIG_FRAME_MSK NO_OS_GENMASK(6, 4)

◆ AD713X_DEV_CONFIG1_AA_MODE_MSK

#define AD713X_DEV_CONFIG1_AA_MODE_MSK NO_OS_BIT(4)

◆ AD713X_DEV_CONFIG1_CLKOUT_EN_MSK

#define AD713X_DEV_CONFIG1_CLKOUT_EN_MSK NO_OS_BIT(0)

◆ AD713X_DEV_CONFIG1_MPC_MAG_EN_MSK

#define AD713X_DEV_CONFIG1_MPC_MAG_EN_MSK NO_OS_BIT(5)

◆ AD713X_DEV_CONFIG1_MPC_MAGPHA_EN_MSK

#define AD713X_DEV_CONFIG1_MPC_MAGPHA_EN_MSK NO_OS_BIT(6)

◆ AD713X_DEV_CONFIG1_REF_GAIN_CORR_EN_MSK

#define AD713X_DEV_CONFIG1_REF_GAIN_CORR_EN_MSK NO_OS_BIT(1)

◆ AD713X_DEV_CONFIG1_SDO_PIN_SRC_SEL_MSK

#define AD713X_DEV_CONFIG1_SDO_PIN_SRC_SEL_MSK NO_OS_BIT(2)

◆ AD713X_DEV_CONFIG_NO_CHIP_ERR_MSK

#define AD713X_DEV_CONFIG_NO_CHIP_ERR_MSK NO_OS_BIT(4)

◆ AD713X_DEV_CONFIG_OP_IN_PROGRESS_MSK

#define AD713X_DEV_CONFIG_OP_IN_PROGRESS_MSK NO_OS_BIT(5)

◆ AD713X_DEV_CONFIG_PWR_MODE_MSK

#define AD713X_DEV_CONFIG_PWR_MODE_MSK NO_OS_BIT(0)

◆ AD713X_DEV_STAT_CLKSEL_MSK

#define AD713X_DEV_STAT_CLKSEL_MSK NO_OS_BIT(2)

◆ AD713X_DEV_STAT_DCLKIO_MSK

#define AD713X_DEV_STAT_DCLKIO_MSK NO_OS_BIT(4)

◆ AD713X_DEV_STAT_DCLKMODE_MSK

#define AD713X_DEV_STAT_DCLKMODE_MSK NO_OS_BIT(5)

◆ AD713X_DEV_STAT_FUSE_ECC_MSK

#define AD713X_DEV_STAT_FUSE_ECC_MSK NO_OS_BIT(1)

◆ AD713X_DEV_STAT_MODE_MSK

#define AD713X_DEV_STAT_MODE_MSK NO_OS_BIT(3)

◆ AD713X_DEV_STAT_PLL_LOCK_MSK

#define AD713X_DEV_STAT_PLL_LOCK_MSK NO_OS_BIT(0)

◆ AD713X_DIAGCTRL_ERR_MM_CRC_EN_MSK

#define AD713X_DIAGCTRL_ERR_MM_CRC_EN_MSK NO_OS_BIT(1)

◆ AD713X_DIAGCTRL_ERR_OR_AIN_EN_MSK

#define AD713X_DIAGCTRL_ERR_OR_AIN_EN_MSK NO_OS_BIT(5)

◆ AD713X_DIAGCTRL_ERR_PWR_MON_EN_MSK

#define AD713X_DIAGCTRL_ERR_PWR_MON_EN_MSK NO_OS_BIT(4)

◆ AD713X_DIAGCTRL_ERR_SPI_CRC_EN_MSK

#define AD713X_DIAGCTRL_ERR_SPI_CRC_EN_MSK NO_OS_BIT(2)

◆ AD713X_DIAGCTRL_FUSE_CRC_CHECK_MSK

#define AD713X_DIAGCTRL_FUSE_CRC_CHECK_MSK NO_OS_BIT(0)

◆ AD713X_DIAGCTRL_MCLK_CNT_EN_MSK

#define AD713X_DIAGCTRL_MCLK_CNT_EN_MSK NO_OS_BIT(3)

◆ AD713X_DIG_INT_CONFIG_AVG_SEL_MODE

#define AD713X_DIG_INT_CONFIG_AVG_SEL_MODE ( x ) (((x) & 0x3) << 2)

◆ AD713X_DIG_INT_CONFIG_AVG_SEL_MSK

#define AD713X_DIG_INT_CONFIG_AVG_SEL_MSK NO_OS_GENMASK(3, 2)

◆ AD713X_DIG_INT_CONFIG_DAISY_CHAIN_NUM_MODE

#define AD713X_DIG_INT_CONFIG_DAISY_CHAIN_NUM_MODE ( x ) (((x) & 0xF) << 4)

◆ AD713X_DIG_INT_CONFIG_DAISY_CHAIN_NUM_MSK

#define AD713X_DIG_INT_CONFIG_DAISY_CHAIN_NUM_MSK NO_OS_GENMASK(7, 4)

◆ AD713X_DIG_INT_CONFIG_FORMAT_MODE

#define AD713X_DIG_INT_CONFIG_FORMAT_MODE ( x ) (((x) & 0x3) << 0)

◆ AD713X_DIG_INT_CONFIG_FORMAT_MSK

#define AD713X_DIG_INT_CONFIG_FORMAT_MSK NO_OS_GENMASK(1, 0)

◆ AD713X_DIGFILTER_CH_SETTLED_MSK

#define AD713X_DIGFILTER_CH_SETTLED_MSK ( ch ) NO_OS_BIT(ch)

◆ AD713X_DIGFILTER_ERR_OFUF_CH_MSK

#define AD713X_DIGFILTER_ERR_OFUF_CH_MSK ( ch ) NO_OS_BIT(ch)

◆ AD713X_DIGFILTER_SEL_CH_MODE

#define AD713X_DIGFILTER_SEL_CH_MODE	(	x,
		ch
	)	(((x) & 0x3) << (2 * ch))

◆ AD713X_DIGFILTER_SEL_CH_MSK

#define AD713X_DIGFILTER_SEL_CH_MSK ( ch ) (NO_OS_GENMASK(1, 0) << (2 * ch))

◆ AD713X_DVDD1V8_VALUE_PIN_MODE

#define AD713X_DVDD1V8_VALUE_PIN_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_DVDD1V8_VALUE_PIN_MSK

#define AD713X_DVDD1V8_VALUE_PIN_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_DVDD5_VALUE_PIN_MODE

#define AD713X_DVDD5_VALUE_PIN_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_DVDD5_VALUE_PIN_MSK

#define AD713X_DVDD5_VALUE_PIN_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_ERR_OR_AIN_MSK

#define AD713X_ERR_OR_AIN_MSK ( ch ) NO_OS_BIT(ch)

◆ AD713X_ERR_PIN_EN_INTERNAL_MSK

#define AD713X_ERR_PIN_EN_INTERNAL_MSK NO_OS_BIT(4)

◆ AD713X_ERR_PIN_EN_LDO_XOSC_MSK

#define AD713X_ERR_PIN_EN_LDO_XOSC_MSK NO_OS_BIT(2)

◆ AD713X_ERR_PIN_EN_OR_AIN_MSK

#define AD713X_ERR_PIN_EN_OR_AIN_MSK NO_OS_BIT(5)

◆ AD713X_ERR_PIN_EN_PWR_MSK

#define AD713X_ERR_PIN_EN_PWR_MSK NO_OS_BIT(0)

◆ AD713X_ERR_PIN_EN_SPI_MSK

#define AD713X_ERR_PIN_EN_SPI_MSK NO_OS_BIT(3)

◆ AD713X_ERR_PIN_EN_TEMP_MSK

#define AD713X_ERR_PIN_EN_TEMP_MSK NO_OS_BIT(1)

◆ AD713X_ERR_PIN_IN_EN_MSK

#define AD713X_ERR_PIN_IN_EN_MSK NO_OS_BIT(1)

◆ AD713X_ERR_PIN_IN_STATUS_MSK

#define AD713X_ERR_PIN_IN_STATUS_MSK NO_OS_BIT(2)

◆ AD713X_ERR_PIN_OUT_EN_MSK

#define AD713X_ERR_PIN_OUT_EN_MSK NO_OS_BIT(0)

◆ AD713X_FIR_BW_SEL_CH_MSK

#define AD713X_FIR_BW_SEL_CH_MSK ( ch ) NO_OS_BIT(ch)

◆ AD713X_GPIO_DATA_MODE

#define AD713X_GPIO_DATA_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_GPIO_DATA_MSK

#define AD713X_GPIO_DATA_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_GPIO_IO_CTRL_MODE

#define AD713X_GPIO_IO_CTRL_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_GPIO_IO_CTRL_MSK

#define AD713X_GPIO_IO_CTRL_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_INT_CONFIG_A_ADDR_ASC_BIT_MSK

#define AD713X_INT_CONFIG_A_ADDR_ASC_BIT_MSK NO_OS_BIT(5)

◆ AD713X_INT_CONFIG_A_ADDR_ASC_MIRR_MSK

#define AD713X_INT_CONFIG_A_ADDR_ASC_MIRR_MSK NO_OS_BIT(2)

◆ AD713X_INT_CONFIG_A_SDO_ACTIVE_BIT_MSK

#define AD713X_INT_CONFIG_A_SDO_ACTIVE_BIT_MSK NO_OS_BIT(4)

◆ AD713X_INT_CONFIG_A_SDO_ACTIVE_MIRR_MSK

#define AD713X_INT_CONFIG_A_SDO_ACTIVE_MIRR_MSK NO_OS_BIT(3)

◆ AD713X_INT_CONFIG_A_SOFT_RESET_MIRR_MSK

#define AD713X_INT_CONFIG_A_SOFT_RESET_MIRR_MSK NO_OS_BIT(0)

◆ AD713X_INT_CONFIG_A_SOFT_RESET_MSK

#define AD713X_INT_CONFIG_A_SOFT_RESET_MSK NO_OS_BIT(7)

◆ AD713X_INT_CONFIG_B_DIG_IF_RST_MSK

#define AD713X_INT_CONFIG_B_DIG_IF_RST_MSK NO_OS_BIT(1)

◆ AD713X_INT_CONFIG_B_M_S_RD_CTRL_MSK

#define AD713X_INT_CONFIG_B_M_S_RD_CTRL_MSK NO_OS_BIT(5)

◆ AD713X_INT_CONFIG_B_SINGLE_INSTR_MSK

#define AD713X_INT_CONFIG_B_SINGLE_INSTR_MSK NO_OS_BIT(7)

◆ AD713X_INT_ERR_ASRC_MSK

#define AD713X_INT_ERR_ASRC_MSK NO_OS_BIT(1)

◆ AD713X_INT_ERR_DCLK_MSK

#define AD713X_INT_ERR_DCLK_MSK NO_OS_BIT(3)

◆ AD713X_INT_ERR_FUSE_CRC_MSK

#define AD713X_INT_ERR_FUSE_CRC_MSK NO_OS_BIT(2)

◆ AD713X_INT_ERR_MM_CRC_MSK

#define AD713X_INT_ERR_MM_CRC_MSK NO_OS_BIT(0)

◆ AD713X_INT_ERR_NO_CLOCK_MSK

#define AD713X_INT_ERR_NO_CLOCK_MSK NO_OS_BIT(5)

◆ AD713X_INT_ERR_TEMP_MSK

#define AD713X_INT_ERR_TEMP_MSK NO_OS_BIT(4)

◆ AD713X_IOVDD_VALUE_PIN_MODE

#define AD713X_IOVDD_VALUE_PIN_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_IOVDD_VALUE_PIN_MSK

#define AD713X_IOVDD_VALUE_PIN_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_LDOIN_VALUE_PIN_MODE

#define AD713X_LDOIN_VALUE_PIN_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_LDOIN_VALUE_PIN_MSK

#define AD713X_LDOIN_VALUE_PIN_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_MCLK_COUNT_MODE

#define AD713X_MCLK_COUNT_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_MCLK_COUNT_MSK

#define AD713X_MCLK_COUNT_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_MPC_CLKDEL_EN_CH_MODE

#define AD713X_MPC_CLKDEL_EN_CH_MODE	(	x,
		ch
	)	(((x) & 0x3) << (2 * ch))

◆ AD713X_MPC_CLKDEL_EN_CH_MSK

#define AD713X_MPC_CLKDEL_EN_CH_MSK ( ch ) (NO_OS_GENMASK(1, 0) << (2 * ch))

◆ AD713X_ODR_RATE_SEL_CH_MODE

#define AD713X_ODR_RATE_SEL_CH_MODE	(	x,
		ch
	)	(((x) & 0x3) << (2 * ch))

◆ AD713X_ODR_RATE_SEL_CH_MSK

#define AD713X_ODR_RATE_SEL_CH_MSK ( ch ) (NO_OS_GENMASK(1, 0) << (2 * ch))

◆ AD713X_ODR_VAL_FLT_LSB_MODE

#define AD713X_ODR_VAL_FLT_LSB_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_ODR_VAL_FLT_LSB_MSK

#define AD713X_ODR_VAL_FLT_LSB_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_ODR_VAL_FLT_MID0_MODE

#define AD713X_ODR_VAL_FLT_MID0_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_ODR_VAL_FLT_MID0_MSK

#define AD713X_ODR_VAL_FLT_MID0_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_ODR_VAL_FLT_MID1_MODE

#define AD713X_ODR_VAL_FLT_MID1_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_ODR_VAL_FLT_MID1_MSK

#define AD713X_ODR_VAL_FLT_MID1_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_ODR_VAL_FLT_MSB_MODE

#define AD713X_ODR_VAL_FLT_MSB_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_ODR_VAL_FLT_MSB_MSK

#define AD713X_ODR_VAL_FLT_MSB_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_ODR_VAL_INT_LSB_MODE

#define AD713X_ODR_VAL_INT_LSB_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_ODR_VAL_INT_LSB_MSK

#define AD713X_ODR_VAL_INT_LSB_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_ODR_VAL_INT_MID_MODE

#define AD713X_ODR_VAL_INT_MID_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_ODR_VAL_INT_MID_MSK

#define AD713X_ODR_VAL_INT_MID_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_ODR_VAL_INT_MSB_MODE

#define AD713X_ODR_VAL_INT_MSB_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_ODR_VAL_INT_MSB_MSK

#define AD713X_ODR_VAL_INT_MSB_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_POWER_ERR_OV_AVDD1V8_MSK

#define AD713X_POWER_ERR_OV_AVDD1V8_MSK NO_OS_BIT(0)

◆ AD713X_POWER_ERR_OV_AVDD5_MSK

#define AD713X_POWER_ERR_OV_AVDD5_MSK NO_OS_BIT(0)

◆ AD713X_POWER_ERR_OV_CLKVDD_MSK

#define AD713X_POWER_ERR_OV_CLKVDD_MSK NO_OS_BIT(2)

◆ AD713X_POWER_ERR_OV_DVDD1V8_MSK

#define AD713X_POWER_ERR_OV_DVDD1V8_MSK NO_OS_BIT(1)

◆ AD713X_POWER_ERR_OV_DVDD5_MSK

#define AD713X_POWER_ERR_OV_DVDD5_MSK NO_OS_BIT(1)

◆ AD713X_POWER_ERR_OV_IOVDD_MSK

#define AD713X_POWER_ERR_OV_IOVDD_MSK NO_OS_BIT(3)

◆ AD713X_POWER_ERR_OV_LDOIN_MSK

#define AD713X_POWER_ERR_OV_LDOIN_MSK NO_OS_BIT(2)

◆ AD713X_POWER_ERR_OV_VREF_MSK

#define AD713X_POWER_ERR_OV_VREF_MSK NO_OS_BIT(3)

◆ AD713X_POWER_ERR_UV_AVDD1V8_MSK

#define AD713X_POWER_ERR_UV_AVDD1V8_MSK NO_OS_BIT(0)

◆ AD713X_POWER_ERR_UV_AVDD5_MSK

#define AD713X_POWER_ERR_UV_AVDD5_MSK NO_OS_BIT(0)

◆ AD713X_POWER_ERR_UV_CLKVDD_MSK

#define AD713X_POWER_ERR_UV_CLKVDD_MSK NO_OS_BIT(2)

◆ AD713X_POWER_ERR_UV_DVDD1V8_MSK

#define AD713X_POWER_ERR_UV_DVDD1V8_MSK NO_OS_BIT(1)

◆ AD713X_POWER_ERR_UV_DVDD5_MSK

#define AD713X_POWER_ERR_UV_DVDD5_MSK NO_OS_BIT(1)

◆ AD713X_POWER_ERR_UV_IOVDD_MSK

#define AD713X_POWER_ERR_UV_IOVDD_MSK NO_OS_BIT(3)

◆ AD713X_POWER_ERR_UV_LDOIN_MSK

#define AD713X_POWER_ERR_UV_LDOIN_MSK NO_OS_BIT(2)

◆ AD713X_POWER_ERR_UV_VREF_MSK

#define AD713X_POWER_ERR_UV_VREF_MSK NO_OS_BIT(3)

◆ AD713X_PRODUCT_ID_LSB_BITS_MODE

#define AD713X_PRODUCT_ID_LSB_BITS_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_PRODUCT_ID_LSB_BITS_MSK

#define AD713X_PRODUCT_ID_LSB_BITS_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_PRODUCT_ID_MSB_BITS_MODE

#define AD713X_PRODUCT_ID_MSB_BITS_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_PRODUCT_ID_MSB_BITS_MSK

#define AD713X_PRODUCT_ID_MSB_BITS_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_PWRDN_CTRL_PWRDN_AUXADC_MSK

#define AD713X_PWRDN_CTRL_PWRDN_AUXADC_MSK NO_OS_BIT(2)

◆ AD713X_PWRDN_CTRL_PWRDN_CH_MSK

#define AD713X_PWRDN_CTRL_PWRDN_CH_MSK ( ch ) NO_OS_BIT(ch)

◆ AD713X_PWRDN_CTRL_PWRDN_LDO_MSK

#define AD713X_PWRDN_CTRL_PWRDN_LDO_MSK NO_OS_BIT(1)

◆ AD713X_PWRDN_CTRL_PWRDN_SLEEP_MODE_EN_MSK

#define AD713X_PWRDN_CTRL_PWRDN_SLEEP_MODE_EN_MSK NO_OS_BIT(0)

◆ AD713X_REG_AIN_OR_ERROR

#define AD713X_REG_AIN_OR_ERROR 0x48

◆ AD713X_REG_AIN_RANGE_SELECT

#define AD713X_REG_AIN_RANGE_SELECT 0x14

◆ AD713X_REG_AVDD1V8_VALUE

#define AD713X_REG_AVDD1V8_VALUE 0x4D

◆ AD713X_REG_AVDD5_VALUE

#define AD713X_REG_AVDD5_VALUE 0x49

◆ AD713X_REG_CH0_GAIN_LSB

#define AD713X_REG_CH0_GAIN_LSB 0x27

◆ AD713X_REG_CH0_GAIN_MID

#define AD713X_REG_CH0_GAIN_MID 0x28

◆ AD713X_REG_CH0_GAIN_MSB

#define AD713X_REG_CH0_GAIN_MSB 0x29

◆ AD713X_REG_CH0_OFFSET_LSB

#define AD713X_REG_CH0_OFFSET_LSB 0x2A

◆ AD713X_REG_CH0_OFFSET_MID

#define AD713X_REG_CH0_OFFSET_MID 0x2B

◆ AD713X_REG_CH0_OFFSET_MSB

#define AD713X_REG_CH0_OFFSET_MSB 0x2C

◆ AD713X_REG_CH1_GAIN_LSB

#define AD713X_REG_CH1_GAIN_LSB 0x2D

◆ AD713X_REG_CH1_GAIN_MID

#define AD713X_REG_CH1_GAIN_MID 0x2E

◆ AD713X_REG_CH1_GAIN_MSB

#define AD713X_REG_CH1_GAIN_MSB 0x2F

◆ AD713X_REG_CH1_OFFSET_LSB

#define AD713X_REG_CH1_OFFSET_LSB 0x30

◆ AD713X_REG_CH1_OFFSET_MID

#define AD713X_REG_CH1_OFFSET_MID 0x31

◆ AD713X_REG_CH1_OFFSET_MSB

#define AD713X_REG_CH1_OFFSET_MSB 0x32

◆ AD713X_REG_CH2_GAIN_LSB

#define AD713X_REG_CH2_GAIN_LSB 0x33

◆ AD713X_REG_CH2_GAIN_MID

#define AD713X_REG_CH2_GAIN_MID 0x34

◆ AD713X_REG_CH2_GAIN_MSB

#define AD713X_REG_CH2_GAIN_MSB 0x35

◆ AD713X_REG_CH2_OFFSET_LSB

#define AD713X_REG_CH2_OFFSET_LSB 0x36

◆ AD713X_REG_CH2_OFFSET_MID

#define AD713X_REG_CH2_OFFSET_MID 0x37

◆ AD713X_REG_CH2_OFFSET_MSB

#define AD713X_REG_CH2_OFFSET_MSB 0x38

◆ AD713X_REG_CH3_GAIN_LSB

#define AD713X_REG_CH3_GAIN_LSB 0x39

◆ AD713X_REG_CH3_GAIN_MID

#define AD713X_REG_CH3_GAIN_MID 0x3A

◆ AD713X_REG_CH3_GAIN_MSB

#define AD713X_REG_CH3_GAIN_MSB 0x3B

◆ AD713X_REG_CH3_OFFSET_LSB

#define AD713X_REG_CH3_OFFSET_LSB 0x3C

◆ AD713X_REG_CH3_OFFSET_MID

#define AD713X_REG_CH3_OFFSET_MID 0x3D

◆ AD713X_REG_CH3_OFFSET_MSB

#define AD713X_REG_CH3_OFFSET_MSB 0x3E

◆ AD713X_REG_CHAN_DIG_FILTER_SEL

#define AD713X_REG_CHAN_DIG_FILTER_SEL 0x1E

◆ AD713X_REG_CHANNEL_ODR_SELECT

#define AD713X_REG_CHANNEL_ODR_SELECT 0x1D

◆ AD713X_REG_CHIP_GRADE

#define AD713X_REG_CHIP_GRADE 0x06

◆ AD713X_REG_CHIP_INDEX

#define AD713X_REG_CHIP_INDEX 0x07

◆ AD713X_REG_CHIP_TYPE

#define AD713X_REG_CHIP_TYPE 0x03

◆ AD713X_REG_CLKVDD_VALUE

#define AD713X_REG_CLKVDD_VALUE 0x4F

◆ AD713X_REG_DATA_PACKET_CONFIG

#define AD713X_REG_DATA_PACKET_CONFIG 0x11

◆ AD713X_REG_DEVICE_CONFIG

#define AD713X_REG_DEVICE_CONFIG 0x02

◆ AD713X_REG_DEVICE_CONFIG1

#define AD713X_REG_DEVICE_CONFIG1 0x10

◆ AD713X_REG_DEVICE_STATUS

#define AD713X_REG_DEVICE_STATUS 0x15

◆ AD713X_REG_DIAGNOSTIC_CONTROL

#define AD713X_REG_DIAGNOSTIC_CONTROL 0x25

◆ AD713X_REG_DIG_FILTER_OFUF

#define AD713X_REG_DIG_FILTER_OFUF 0x40

◆ AD713X_REG_DIG_FILTER_SETTLED

#define AD713X_REG_DIG_FILTER_SETTLED 0x41

◆ AD713X_REG_DIGITAL_INTERFACE_CONFIG

#define AD713X_REG_DIGITAL_INTERFACE_CONFIG 0x12

◆ AD713X_REG_DVDD1V8_VALUE

#define AD713X_REG_DVDD1V8_VALUE 0x4E

◆ AD713X_REG_DVDD5_VALUE

#define AD713X_REG_DVDD5_VALUE 0x4A

◆ AD713X_REG_ERROR_PIN_CONTROL

#define AD713X_REG_ERROR_PIN_CONTROL 0x23

◆ AD713X_REG_ERROR_PIN_SRC_CONTROL

#define AD713X_REG_ERROR_PIN_SRC_CONTROL 0x22

◆ AD713X_REG_FIR_BW_SEL

#define AD713X_REG_FIR_BW_SEL 0x1F

◆ AD713X_REG_GPIO_DATA

#define AD713X_REG_GPIO_DATA 0x21

◆ AD713X_REG_GPIO_DIR_CTRL

#define AD713X_REG_GPIO_DIR_CTRL 0x20

◆ AD713X_REG_INTERFACE_CONFIG_A

#define AD713X_REG_INTERFACE_CONFIG_A 0x00

◆ AD713X_REG_INTERFACE_CONFIG_B

#define AD713X_REG_INTERFACE_CONFIG_B 0x01

◆ AD713X_REG_INTERNAL_ERROR

#define AD713X_REG_INTERNAL_ERROR 0x42

◆ AD713X_REG_IOVDD_VALUE

#define AD713X_REG_IOVDD_VALUE 0x50

◆ AD713X_REG_LDOIN_VALUE

#define AD713X_REG_LDOIN_VALUE 0x4C

◆ AD713X_REG_MCLK_COUNTER

#define AD713X_REG_MCLK_COUNTER 0x3F

◆ AD713X_REG_MPC_CONFIG

#define AD713X_REG_MPC_CONFIG 0x26

◆ AD713X_REG_ODR_VAL_FLT_LSB

#define AD713X_REG_ODR_VAL_FLT_LSB 0x19

◆ AD713X_REG_ODR_VAL_FLT_MID0

#define AD713X_REG_ODR_VAL_FLT_MID0 0x1A

◆ AD713X_REG_ODR_VAL_FLT_MID1

#define AD713X_REG_ODR_VAL_FLT_MID1 0x1B

◆ AD713X_REG_ODR_VAL_FLT_MSB

#define AD713X_REG_ODR_VAL_FLT_MSB 0x1C

◆ AD713X_REG_ODR_VAL_INT_LSB

#define AD713X_REG_ODR_VAL_INT_LSB 0x16

◆ AD713X_REG_ODR_VAL_INT_MID

#define AD713X_REG_ODR_VAL_INT_MID 0x17

◆ AD713X_REG_ODR_VAL_INT_MSB

#define AD713X_REG_ODR_VAL_INT_MSB 0x18

◆ AD713X_REG_POWER_DOWN_CONTROL

#define AD713X_REG_POWER_DOWN_CONTROL 0x13

◆ AD713X_REG_POWER_OV_ERROR_1

#define AD713X_REG_POWER_OV_ERROR_1 0x43

◆ AD713X_REG_POWER_OV_ERROR_2

#define AD713X_REG_POWER_OV_ERROR_2 0x45

◆ AD713X_REG_POWER_UV_ERROR_1

#define AD713X_REG_POWER_UV_ERROR_1 0x44

◆ AD713X_REG_POWER_UV_ERROR_2

#define AD713X_REG_POWER_UV_ERROR_2 0x46

◆ AD713X_REG_PRODUCT_ID_LSB

#define AD713X_REG_PRODUCT_ID_LSB 0x04

◆ AD713X_REG_PRODUCT_ID_MSB

#define AD713X_REG_PRODUCT_ID_MSB 0x05

◆ AD713X_REG_READ

#define AD713X_REG_READ ( x ) ((1 << 7) | (x & 0x7F))

◆ AD713X_REG_SCTATCH_PAD

#define AD713X_REG_SCTATCH_PAD 0x0A

◆ AD713X_REG_SPI_ERROR

#define AD713X_REG_SPI_ERROR 0x47

◆ AD713X_REG_SPI_REVISION

#define AD713X_REG_SPI_REVISION 0x0B

◆ AD713X_REG_STREAM_MODE

#define AD713X_REG_STREAM_MODE 0x0E

◆ AD713X_REG_TEMPERATURE_DATA

#define AD713X_REG_TEMPERATURE_DATA 0x51

◆ AD713X_REG_TRANSFER_REGISTER

#define AD713X_REG_TRANSFER_REGISTER 0x0F

◆ AD713X_REG_VCMBUF_CTRL

#define AD713X_REG_VCMBUF_CTRL 0x24

◆ AD713X_REG_VENDOR_ID_LSB

#define AD713X_REG_VENDOR_ID_LSB 0x0C

◆ AD713X_REG_VENDOR_ID_MSB

#define AD713X_REG_VENDOR_ID_MSB 0x0D

◆ AD713X_REG_VREF_VALUE

#define AD713X_REG_VREF_VALUE 0x4B

◆ AD713X_SCRATCH_PAD_BITS_MODE

#define AD713X_SCRATCH_PAD_BITS_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_SCRATCH_PAD_BITS_MSK

#define AD713X_SCRATCH_PAD_BITS_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_SILICON_REV_ID_BITS_MODE

#define AD713X_SILICON_REV_ID_BITS_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_SILICON_REV_ID_BITS_MSK

#define AD713X_SILICON_REV_ID_BITS_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_SPI_ERROR_CRC_MSK

#define AD713X_SPI_ERROR_CRC_MSK NO_OS_BIT(3)

◆ AD713X_SPI_ERROR_READ_MSK

#define AD713X_SPI_ERROR_READ_MSK NO_OS_BIT(0)

◆ AD713X_SPI_ERROR_SCLK_CNT_MSK

#define AD713X_SPI_ERROR_SCLK_CNT_MSK NO_OS_BIT(2)

◆ AD713X_SPI_ERROR_WRITE_MSK

#define AD713X_SPI_ERROR_WRITE_MSK NO_OS_BIT(1)

◆ AD713X_SPI_REVISION_BITS_MODE

#define AD713X_SPI_REVISION_BITS_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_SPI_REVISION_BITS_MSK

#define AD713X_SPI_REVISION_BITS_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_STREAM_MODE_BITS_MODE

#define AD713X_STREAM_MODE_BITS_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_STREAM_MODE_BITS_MSK

#define AD713X_STREAM_MODE_BITS_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_TEMP_DATA_MODE

#define AD713X_TEMP_DATA_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_TEMP_DATA_MSK

#define AD713X_TEMP_DATA_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_TRANSFER_MASTER_SLAVE_TX_BIT_MSK

#define AD713X_TRANSFER_MASTER_SLAVE_TX_BIT_MSK NO_OS_BIT(0)

◆ AD713X_VCMBUF_CTRL_PWRDN_MSK

#define AD713X_VCMBUF_CTRL_PWRDN_MSK NO_OS_BIT(6)

◆ AD713X_VCMBUF_CTRL_REF_DIV_SEL_MODE

#define AD713X_VCMBUF_CTRL_REF_DIV_SEL_MODE ( x ) (((x) & 0x1F) << 1)

◆ AD713X_VCMBUF_CTRL_REF_DIV_SEL_MSK

#define AD713X_VCMBUF_CTRL_REF_DIV_SEL_MSK NO_OS_GENMASK(5, 1)

◆ AD713X_VCMBUF_CTRL_REF_SEL_MSK

#define AD713X_VCMBUF_CTRL_REF_SEL_MSK NO_OS_BIT(0)

◆ AD713X_VENDOR_ID_LSB_BITS_MODE

#define AD713X_VENDOR_ID_LSB_BITS_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_VENDOR_ID_LSB_BITS_MSK

#define AD713X_VENDOR_ID_LSB_BITS_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_VENDOR_ID_MSB_BITS_MODE

#define AD713X_VENDOR_ID_MSB_BITS_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_VENDOR_ID_MSB_BITS_MSK

#define AD713X_VENDOR_ID_MSB_BITS_MSK NO_OS_GENMASK(7, 0)

◆ AD713X_VREF_VALUE_PIN_MODE

#define AD713X_VREF_VALUE_PIN_MODE ( x ) (((x) & 0xFF) << 0)

◆ AD713X_VREF_VALUE_PIN_MSK

#define AD713X_VREF_VALUE_PIN_MSK NO_OS_GENMASK(7, 0)

Enumeration Type Documentation

◆ ad713x_adc_data_len

enum ad713x_adc_data_len

AD713x possible number of bits per data sample.

Enumerator
ADC_16_BIT_DATA	16 bit data sample
ADC_24_BIT_DATA	24 bit data sample
ADC_32_BIT_DATA	32 bit data sample
INVALID	To know when to stop when cycling between them

◆ ad713x_channels

enum ad713x_channels

AD713x list of channels.

Enumerator
CH0	Channel 0
CH1	Channel 1
CH2	Channel 2
CH3	Channel 3
AD713X_CH_MAX	Max number of channels

◆ ad713x_crc_header

enum ad713x_crc_header

AD713x possible data CRC header choices.

Enumerator
NO_CRC	Data sample comes with no CRC attached
CRC_6	Data sample comes with 6-bit CRC attached
CRC_8	Data sample comes with 8-bit CRC attached

◆ ad713x_dig_filter_sel

enum ad713x_dig_filter_sel

AD713x list of input filters.

Enumerator
FIR	Wideband filter (Finite impulse response)
SINC6	Sinc6 filter
SINC3	Sinc3 filter
SINC3_50_60_REJ	Sinc3 filter with 50Hz and 60Hz rejection

◆ ad713x_doutx_format

enum ad713x_doutx_format

AD713x list for possible output modes.

Enumerator
SINGLE_CH_DC	Single channel Daisy-chain mode
DUAL_CH_DC	Dual channel Daisy-chain mode
QUAD_CH_PO	Quad-channel parallel output mode
CH_AVG_MODE	Channel average mode

◆ ad713x_power_mode

enum ad713x_power_mode

AD713x power modes.

Enumerator
LOW_POWER	Low power mode option
HIGH_POWER	Full power mode option

◆ ad713x_supported_dev_ids

enum ad713x_supported_dev_ids

ID of devices supported by the driver.

Enumerator
ID_AD7132
ID_AD7134
ID_AD7136
ID_AD4134

◆ ad717x_mpc_clkdel

enum ad717x_mpc_clkdel

AD713x list of clock delays.

Enumerator
DELAY_NONE	No delay
DELAY_1_CLOCKS	One clock cycle delay
DELAY_2_CLOCKS	Two clock cycles delay

Function Documentation

◆ ad713x_channel_sync()

int32_t ad713x_channel_sync ( struct ad713x_dev * dev )

Multidevice synchronization between channels on different devices.

Multidevice synchronization

Parameters

dev	- The device structure.

Returns: 0 in case of success, -1 otherwise.

◆ ad713x_clkout_output_en()

int32_t ad713x_clkout_output_en	(	struct ad713x_dev *	dev,
		bool	enable
	)

Enable/Disable CLKOUT output.

Parameters

[in]	dev	- The device structure.
[in]	enable	- true to enable the clkout output; false to disable the clkout output.

Returns: 0 in case of success, -1 otherwise.

◆ ad713x_dig_filter_sel_ch()

int32_t ad713x_dig_filter_sel_ch	(	struct ad713x_dev *	dev,
		enum ad713x_dig_filter_sel	filter,
		enum ad713x_channels	ch
	)

Digital filter type selection for each channel.

Parameters

dev	- The device structure.
filter	- Type of filter: Wideband, Sinc6, Sinc3, Sinc3 filter with simultaneous 50Hz and 60Hz rejection. Accepted values: FIR SINC6 SINC3 SINC3_50_60_REJ
ch	- Channel to apply the filter to Accepted values: CH0 CH1 CH2 CH3

Returns: 0 in case of success, -1 otherwise.

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◆ ad713x_dout_format_config()

int32_t ad713x_dout_format_config	(	struct ad713x_dev *	dev,
		enum ad713x_doutx_format	format
	)

DOUTx output format configuration.

Parameters

dev	- The device structure.
format	- Single channel daisy chain mode. Dual channel daisy chain mode. Quad channel parallel output mode. Channel data averaging mode. Accepted values: SINGLE_CH_DC DUAL_CH_DC QUAD_CH_PO CH_AVG_MODE

Returns: 0 in case of success, -1 otherwise.

◆ ad713x_init()

int32_t ad713x_init	(	struct ad713x_dev **	device,
		struct ad713x_init_param *	init_param
	)

Initialize the device.

Parameters

device	- The device structure.
init_param	- The structure that contains the device initial parameters.

Returns: 0 in case of success, -1 otherwise.

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◆ ad713x_mag_phase_clk_delay()

int32_t ad713x_mag_phase_clk_delay	(	struct ad713x_dev *	dev,
		bool	clk_delay_en
	)

Magnitude and phase matching calibration clock delay enable for all channels at 2 clock delay. This function is kept for backwards compatibility with the current application source, but it is deprecated. Use ad713x_mag_phase_clk_delay_chan().

Magnitude and phase matching calibration clock delay enable for all channels at 2 clock delay.

Parameters

dev	- The device structure.
clk_delay_en	- Enable or disable Mag/Phase clock delay. Accepted values: true false

Returns: 0 in case of success, -1 otherwise.

◆ ad713x_ref_gain_correction_en()

int32_t ad713x_ref_gain_correction_en	(	struct ad713x_dev *	dev,
		bool	enable
	)

Enable/Disable reference gain correction.

Parameters

[in]	dev	- The device structure.
[in]	enable	- true to enable the reference gain correction; false to disable the reference gain correction.

Returns: 0 in case of success, -1 otherwise.

◆ ad713x_remove()

int32_t ad713x_remove ( struct ad713x_dev * dev )

Free the resources allocated by ad713x_init().

Parameters

dev	- The device structure.

Returns: 0 in case of success, negative error code otherwise.

◆ ad713x_set_out_data_frame()

int32_t ad713x_set_out_data_frame	(	struct ad713x_dev *	dev,
		enum ad713x_adc_data_len	adc_data_len,
		enum ad713x_crc_header	crc_header
	)

ADC conversion data output frame control.

Parameters

dev	- The device structure.
adc_data_len	- Data conversion length Accepted values: ADC_16_BIT_DATA ADC_24_BIT_DATA ADC_32_BIT_DATA
crc_header	- CRC header Accepted values: NO_CRC CRC_6 CRC_8

Returns: 0 in case of success, -1 otherwise.

◆ ad713x_set_power_mode()

int32_t ad713x_set_power_mode	(	struct ad713x_dev *	dev,
		enum ad713x_power_mode	mode
	)

Device power mode control.

Parameters

dev	- The device structure.
mode	- Type of power mode Accepted values: LOW_POWER HIGH_POWER

Returns: 0 in case of success, -1 otherwise.

◆ ad713x_spi_reg_dump()

int32_t ad713x_spi_reg_dump ( struct ad713x_dev * dev )

Print all registers values for the AD4134 device. Register map has gaps, reg dump function specific for AD4134 dev.

Print reg dump for the specific reg map of AD4134 dev

Parameters

[in] dev - AD713X device handler.

Returns: 0 in case of success, -1 otherwise.

◆ ad713x_spi_reg_read()

int32_t ad713x_spi_reg_read	(	struct ad713x_dev *	dev,
		uint8_t	reg_addr,
		uint8_t *	reg_data
	)

Read from device.

Parameters

dev	- The device structure.
reg_addr	- The register address.
reg_data	- The register data.

Returns: 0 in case of success, -1 otherwise.

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◆ ad713x_spi_reg_write()

int32_t ad713x_spi_reg_write	(	struct ad713x_dev *	dev,
		uint8_t	reg_addr,
		uint8_t	reg_data
	)

Write to device.

Parameters

dev	- The device structure.
reg_addr	- The register address.
reg_data	- The register data.

Returns: 0 in case of success, -1 otherwise.

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◆ ad713x_spi_write_mask()

int32_t ad713x_spi_write_mask	(	struct ad713x_dev *	dev,
		uint8_t	reg_addr,
		uint32_t	mask,
		uint8_t	data
	)

SPI write to device using a mask.

Parameters

dev	- The device structure.
reg_addr	- The register address.
mask	- The mask.
data	- The register data.

Returns: 0 in case of success, -1 otherwise.

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◆ ad713x_wideband_bw_sel()

int32_t ad713x_wideband_bw_sel	(	struct ad713x_dev *	dev,
		enum ad713x_channels	ch,
		uint8_t	wb_opt
	)

Select the wideband filter bandwidth for a channel. The option is relative to ODR, so it's a fraction of it.

Select the wideband filter bandwidth for a channel.

Parameters

[in]	dev	- The device structure.
[in]	ch	- Number of the channel to which to set the wideband filter option.
[in]	wb_opt	- Option to set the wideband filter: Values are: 0 - bandwidth of 0.443 * ODR; 1 - bandwidth of 0.10825 * ODR.

Returns: 0 in case of success, -1 otherwise.

Classes

Macros

Enumerations

Functions

Detailed Description

Macro Definition Documentation

◆ AD713X_AIN_RANGE_SEL_CH_MSK

◆ AD713X_AVDD1V8_VALUE_PIN_MODE

◆ AD713X_AVDD1V8_VALUE_PIN_MSK

◆ AD713X_AVDD5_VALUE_PIN_MODE

◆ AD713X_AVDD5_VALUE_PIN_MSK

◆ AD713X_CH_GAIN_CAL_SEL_MSK

◆ AD713X_CH_GAIN_LSB_MODE

◆ AD713X_CH_GAIN_LSB_MSK

◆ AD713X_CH_GAIN_MID_MODE

◆ AD713X_CH_GAIN_MID_MSK

◆ AD713X_CH_GAIN_MSB_MODE

◆ AD713X_CH_GAIN_MSB_MSK

◆ AD713X_CH_OFFSET_CAL_EN_MSK

◆ AD713X_CH_OFFSET_LSB_MODE

◆ AD713X_CH_OFFSET_LSB_MSK

◆ AD713X_CH_OFFSET_MID_MODE

◆ AD713X_CH_OFFSET_MID_MSK

◆ AD713X_CH_OFFSET_MSB_MODE

◆ AD713X_CH_OFFSET_MSB_MSK

◆ AD713X_CHIP_GRADE_DEV_VERSION_BITS_MODE

◆ AD713X_CHIP_GRADE_DEV_VERSION_BITS_MSK

◆ AD713X_CHIP_GRADE_PROD_GRADE_BITS_MODE

◆ AD713X_CHIP_GRADE_PROD_GRADE_BITS_MSK

◆ AD713X_CHIP_TYPE

◆ AD713X_CHIP_TYPE_BITS_MODE

◆ AD713X_CHIP_TYPE_BITS_MSK

◆ AD713X_CLKVDD_VALUE_PIN_MODE

◆ AD713X_CLKVDD_VALUE_PIN_MSK

◆ AD713X_DATA_PACKET_CONFIG_CRC_POLY_RST_MSK

◆ AD713X_DATA_PACKET_CONFIG_DCLK_FREQ_MODE

◆ AD713X_DATA_PACKET_CONFIG_DCLK_FREQ_MSK

◆ AD713X_DATA_PACKET_CONFIG_FRAME_MODE

◆ AD713X_DATA_PACKET_CONFIG_FRAME_MSK

◆ AD713X_DEV_CONFIG1_AA_MODE_MSK

◆ AD713X_DEV_CONFIG1_CLKOUT_EN_MSK

◆ AD713X_DEV_CONFIG1_MPC_MAG_EN_MSK

◆ AD713X_DEV_CONFIG1_MPC_MAGPHA_EN_MSK

◆ AD713X_DEV_CONFIG1_REF_GAIN_CORR_EN_MSK

◆ AD713X_DEV_CONFIG1_SDO_PIN_SRC_SEL_MSK

◆ AD713X_DEV_CONFIG_NO_CHIP_ERR_MSK

◆ AD713X_DEV_CONFIG_OP_IN_PROGRESS_MSK

◆ AD713X_DEV_CONFIG_PWR_MODE_MSK

◆ AD713X_DEV_STAT_CLKSEL_MSK

◆ AD713X_DEV_STAT_DCLKIO_MSK

◆ AD713X_DEV_STAT_DCLKMODE_MSK

◆ AD713X_DEV_STAT_FUSE_ECC_MSK

◆ AD713X_DEV_STAT_MODE_MSK

◆ AD713X_DEV_STAT_PLL_LOCK_MSK

◆ AD713X_DIAGCTRL_ERR_MM_CRC_EN_MSK

◆ AD713X_DIAGCTRL_ERR_OR_AIN_EN_MSK

◆ AD713X_DIAGCTRL_ERR_PWR_MON_EN_MSK

◆ AD713X_DIAGCTRL_ERR_SPI_CRC_EN_MSK

◆ AD713X_DIAGCTRL_FUSE_CRC_CHECK_MSK

◆ AD713X_DIAGCTRL_MCLK_CNT_EN_MSK

◆ AD713X_DIG_INT_CONFIG_AVG_SEL_MODE

◆ AD713X_DIG_INT_CONFIG_AVG_SEL_MSK

◆ AD713X_DIG_INT_CONFIG_DAISY_CHAIN_NUM_MODE

◆ AD713X_DIG_INT_CONFIG_DAISY_CHAIN_NUM_MSK

◆ AD713X_DIG_INT_CONFIG_FORMAT_MODE

◆ AD713X_DIG_INT_CONFIG_FORMAT_MSK

◆ AD713X_DIGFILTER_CH_SETTLED_MSK

◆ AD713X_DIGFILTER_ERR_OFUF_CH_MSK

◆ AD713X_DIGFILTER_SEL_CH_MODE

◆ AD713X_DIGFILTER_SEL_CH_MSK

◆ AD713X_DVDD1V8_VALUE_PIN_MODE

◆ AD713X_DVDD1V8_VALUE_PIN_MSK

◆ AD713X_DVDD5_VALUE_PIN_MODE

◆ AD713X_DVDD5_VALUE_PIN_MSK

◆ AD713X_ERR_OR_AIN_MSK

◆ AD713X_ERR_PIN_EN_INTERNAL_MSK

◆ AD713X_ERR_PIN_EN_LDO_XOSC_MSK

◆ AD713X_ERR_PIN_EN_OR_AIN_MSK

◆ AD713X_ERR_PIN_EN_PWR_MSK

◆ AD713X_ERR_PIN_EN_SPI_MSK