35#ifndef __PARAMETERS_H__
36#define __PARAMETERS_H__
39#include <xparameters.h>
46#ifdef _XPARAMETERS_PS_H_
47#define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID
48#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
50#ifdef XPS_BOARD_ZCU102
51#define UART_IRQ_ID XPAR_XUARTPS_0_INTR
53#define UART_IRQ_ID XPAR_XUARTPS_1_INTR
57#define UART_DEVICE_ID XPAR_AXI_UART_DEVICE_ID
58#define INTC_DEVICE_ID XPAR_INTC_SINGLE_DEVICE_ID
59#define UART_IRQ_ID XPAR_AXI_INTC_AXI_UART_INTERRUPT_INTR
62#define UART_BAUDRATE 115200
63#define UART_EXTRA &uart_extra_ip
65#define DMA_BASEADDR XPAR_AXI_AD738X_DMA_BASEADDR
66#define SPI_ENGINE_BASEADDR XPAR_SPI_AD738X_ADC_SPI_AD738X_ADC_AXI_REGMAP_BASEADDR
67#define RX_CLKGEN_BASEADDR XPAR_SPI_CLKGEN_BASEADDR
68#define AXI_PWMGEN_BASEADDR XPAR_SPI_TRIGGER_GEN_BASEADDR
70#define SPI_DEVICE_ID 0
72#define SPI_BAUDRATE 80000000
73#define SPI_EXTRA &spi_eng_init_param
75#define TRIGGER_PWM_ID 0
76#define TRIGGER_PERIOD_NS 250
77#define TRIGGER_DUTY_NS 10
78#define TRIGGER_PWM_EXTRA &axi_pwm_init_param
80#define SAMPLES_PER_CHANNEL 1000
81#define BYTES_PER_SAMPLE 2
82#define MAX_SIZE_BASE_ADDR (SAMPLES_PER_CHANNEL * 2 * BYTES_PER_SAMPLE)
84#define DCACHE_INVALIDATE Xil_DCacheInvalidateRange
92#define SPI_OPS &spi_eng_platform_ops
93#define PWM_OPS &axi_pwm_ops
94#define UART_OPS &xil_uart_ops
95#define CLKGEN_INIT &clkgen_init
96#define OFFLOAD_INIT &spi_engine_offload_init_param
struct axi_clkgen_init clkgen_init
Definition common_data.c:74
Definition clk_axi_clkgen.h:44
Structure holding the initialization parameters for axi PWM.
Definition axi_pwm_extra.h:44
Structure containing the init parameters needed by the SPI engine.
Definition spi_engine.h:71
Structure containing the init parameters needed by the offload module.
Definition spi_engine.h:131
Structure holding the initialization parameters for Xilinx platform specific UART parameters.
Definition xilinx_uart.h:56